Datasheet HD74LV164A Datasheet (HIT)

HD74LV164A

8-bit Parallel-out Serial-in Shift Register

ADE-205-266 (Z)

1st Edition

March 1999

Description

The HD74LV164A is 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type
master/slave flip-flop. Inputs A & B permit complete control over the incoming data. A low at either or
both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A
high level on one input enables the other input which will then determine the state of the first flip-flop.
Data at the serial inputs may be changed while the clock is high or low, but only information meeting the
setup and hold time but only information meeting the setup and hold time requirements will be entered.
Data is serially shifted in and out of the 8-bit register during the positive going transition of the clock pulse.
Clear is independent of the clock and accomplished by low level at the clear input.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.

Features

• VCC = 2.0 V to 5.5 V operation

• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)

• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)

• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)

• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)

HD74LV164A

2

Function Table

Inputs Outputs
CLR CLK A B QA QB ... QD

L X X X L L ... L
H ↓ XXQA0Q

B0

... Q

H0

H ↑ HHHQAn... Q

Gn

H ↑ LXLQAn... Q

Gn

H ↑ XLLQAn... Q

Gn

Note: H: High level

L: Low level
X: Immaterial

↑: Low to high transition
↓: High to low transition

Q

AD

, QB0...QH0: Outputs remain unchanged.

Q

An

, QBn...QGn: Data shifted from the previous stage on a positive edge at the clock input.

Pin Arrangement

11

12

9

10

13

14

8

V

CC

Q

H

Q

G

Q

F

Q

E

CLR

1

2

3
4
5

6

7

A
B
Q

A

Q

B

Q

C

Q

D

GND

CLK

(Top view)

HD74LV164A

3

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage range V

CC

–0.5 to 7.0 V

Input voltage range*

1

V

I

–0.5 to 7.0 V

Output voltage range*

1, 2

V

O

–0.5 to VCC + 0.5 V Output: H or L
–0.5 to 7.0 VCC: OFF

Input clamp current I

IK

–20 mA VI < 0

Output clamp current I

OK

±50 mA VO < 0 or VO > V

CC

Continuous output current I

O

±25 mA VO = 0 to V

CC

Continuous current through
V

CC

or GND

I

CC

or I

GND

±50 mA

Maximum power dissipation
at Ta = 25°C (in still air)*

3

P

T

785 mW SOP

500 TSSOP

Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,

no two of which may be realized at the same time.

1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.

2. This value is limited to 5.5 V maximum.

3. The maximum package power dissipation was calculated using a junction temperature of 150°C.

HD74LV164A

4

Recommended Operating Conditions

Item Symbol Min Max Unit Conditions

Supply voltage range V

CC

2.0 5.5 V

Input voltage range V

I

0 5.5 V

Output voltage range V

O

0VCCV H or L

Output current I

OH

— –50 µAV

CC

= 2.0 V

—–2 mAV

CC

= 2.3 to 2.7 V

—–6 V

CC

= 3.0 to 3.6 V

— –12 VCC = 4.5 to 5.5 V

I

OL

—50 µAV

CC

= 2.0 V
— 2 mA VCC = 2.3 to 2.7 V
—6 V

CC

= 3.0 to 3.6 V
—12 V

CC

= 4.5 to 5.5 V

Input transition rise or fall rate ∆t /∆v 0 200 ns/V VCC = 2.3 to 2.7 V

0 100 VCC = 3.0 to 3.6 V
020 V

CC

= 4.5 to 5.5 V

Operating free-air temperature Ta –40 85 °C
Note: Unused or floating inputs must be held high or low.

HD74LV164A

5

Logic Diagram

CLK

A
B

CLR

C1

1D
R

Q

A

3

C1

1D
R

Q

B

4

C1

1D
R

Q

C

5

C1

1D
R

Q

D

6

C1

1D
R

Q

E

10

C1

1D
R

Q

F

11

C1

1D
R

Q

G

12

C1

1D
R

Q

H

13

8

1
2

9

Timing Diagram

CLR

Clear Clear

CLK

Q

A

Q

B

Q

C

Q

D

Q

E

Q

F

Q

G

Q

H

A
B

HD74LV164A

6

DC Electrical Characteristics

• Ta = –40 to 85°C

Item Symbol VCC (V)* Min Typ Max Unit Test Conditions

Input voltage V

IH

2.0 1.5 — — V

2.3 to 2.7 VCC × 0.7 — —

3.0 to 3.6 VCC × 0.7 — —

4.5 to 5.5 VCC × 0.7 — —

V

IL

2.0 — — 0.5

2.3 to 2.7 — — VCC × 0.3

3.0 to 3.6 — — VCC × 0.3

4.5 to 5.5 — — VCC × 0.3

Output voltage V

OH

Min to
Max

VCC – 0.1 — — V IOL = –50 µA

2.3 2.0 — — IOL = –2 mA

3.0 2.48 — — IOL = –6 mA

4.5 3.8 — — IOL = –12 mA

V

OL

Min to
Max

— — 0.1 IOL = 50 µA

2.3 — — 0.4 IOL = 2 mA

3.0 — — 0.44 IOL = 6 mA

4.5 — — 0.55 IOL = 12 mA

Input current I

IN

0 to 5.5 — — ±1 µAV

I

= 5.5 V or GND

Quiescent
supply current

I

CC

5.5 — — 20 µAV

I

= VCC or GND, IO = 0

Output leakage
current

I

OFF

0——5 µAV

I

or VO = 0 V to 5.5 V

Input
capacitance

C

IN

3.3 — 2.2 — pF VI = VCC or GND

Note: For conditions shown as Min or Max, use the appropriate values under recommended operating

conditions.

HD74LV164A

7

Switching Characteristics

• VCC = 2.5 ± 0.2 V

Ta = 25°C Ta = –40 to 85°C

Item Symbol Min Typ Max Min Max Unit Test Conditions

FROM
(Input)

TO
(Output)

Maximum
clock
frequency

fmax 55 105 — 50 — MHz CL = 15 pF

45 85 — 40 — CL = 50 pF

Propa­gation
delay time

t

PLH/tPHL

— 9.2 17.6 1.0 20.0 ns CL = 15 pF CLK Q

— 11.5 21.1 1.0 24.0 CL = 50 pF

t

PHL

— 8.6 16.0 1.0 18.0 CL = 15 pF CLR
— 10.8 19.5 1.0 22.0 CL = 50 pF

Setup time t

su

6.5 — — 8.5 — ns Data before CLK ↑

3.0 — — 3.0 — CLR inactive before
CLK ↑

Hold time t

h

–0.5 — — 0.0 — ns Data after CLK ↑

Pulse
width

t

w

6.0 — — 6.5 — ns CLR L

6.5 — — 7.5 — CLK H or L

HD74LV164A

8

Switching Characteristics (cont)

• VCC = 3.3 ± 0.3 V

Ta = 25°C Ta = –40 to 85°C

Item Symbol Min Typ Max Min Max Unit Test Conditions

FROM
(Input)

TO
(Output)

Maximum
clock
frequency

fmax 80 155 — 65 — MHz CL = 15 pF

50 120 — 45 — CL = 50 pF

Propa­gation
delay time

t

PLH/tPHL

— 6.4 12.8 1.0 15.0 ns CL = 15 pF CLK Q

— 8.3 16.3 1.0 18.5 CL = 50 pF

t

PHL

— 6.0 12.8 1.0 15.0 CL = 15 pF CLR
— 7.9 16.3 1.0 18.5 CL = 50 pF

Setup time t

su

5.0 — — 6.0 — ns Data before CLK ↑

2.5 — — 2.5 — CLR inactive before
CLK ↑

Hold time t

h

0.0 — — 0.0 — ns Data after CLK ↑

Pulse
width

t

w

5.0 — — 5.0 — ns CLR L

5.0 — — 5.0 — CLK H or L

HD74LV164A

9

Switching Characteristics (cont)

• VCC = 5.0 ± 0.5 V

Ta = 25°C Ta = –40 to 85°C

Item Symbol Min Typ Max Min Max Unit Test Conditions

FROM
(Input)

TO
(Output)

Maximum
clock
frequency

fmax 125 220 — 105 — MHz CL = 15 pF

85 165 — 75 — CL = 50 pF

Propa­gation
delay time

t

PLH/tPHL

— 4.5 9.0 1.0 10.5 ns CL = 15 pF CLK Q

— 6.0 11.0 1.0 12.5 CL = 50 pF

t

PHL

— 4.2 8.6 1.0 10.0 CL = 15 pF CLR
— 5.8 10.6 1.0 12.0 CL = 50 pF

Setup time t

su

45 — — 4.5 — ns Data before CLK ↑

2.5 — — 2.5 — CLR inactive before
CLK ↑

Hold time t

h

1.0 — — 1.0 — ns Data after CLK ↑

Pulse
width

t

w

5.0 — — 5.0 — ns CLR L

5.0 — — 5.0 — CLK H or L

HD74LV164A

10

Operating Characteristics

• CL = 50 pF

Ta = 25°C

Item Symbol V

CC

(V) Min Typ Max Unit Test Conditions

Power
dissipation
capacitance

C

PD

3.3 — 48.1 — pF f = 10 MHz

5.0 — 47.5 —

Noise Characteristics

• CL = 50 pF

Ta = 25°C

Item Symbol V

CC

(V) Min Typ Max Unit Test Conditions

Quiet output,
maximum
dynamic V

OL

V

OL (P)

3.3 — 0.3 0.8 V

Quiet output,
minimum
dynamic V

OL

V

OL (V)

3.3 — –0.2 –0.8

Quiet output,
minimum
dynamic V

OH

V

OH (V)

3.3 — 3.1 —

High-level
dynamic
input voltage

V

IH (D)

3.3 2.31 — — V

Low-level
dynamic
inout voltage

V

IL (D)

3.3 — — 0.99

HD74LV164A

11

Test Circuit

L

*

Note: C includes the probe and jig capacitance.

Measurement point

C

L

HD74LV164A

12

Waveform

t

PLH

t

PHL

V

OH

V

OL

0 V

V

CC

V

OH

V

OL

t

PHL

t

PLH

10%

90%

CC

50 % V

CC

50% V

CC

50% V

CC

50% V

CC

50% V

CC

50% V

10 %

90%

Input

In phase output

Out of phase output

t

r

t

f

t

su

t

h

0 V

V

CC

0 V

V

CC

0 V

V

CC

t

w

CC

50% V

CC

50% V

CC

50% V

CC

50% V

Timing input

Data input

Input

10%

90%

CC

50% V

CC

50% V

10%

90%

t

r

t

f

• Waveform – 1

• Waveform – 2

1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, t ≤ 3 ns, t ≤ 3 ns

2. The output are measured one at a time with one transition per measurement.

Notes:

rf

HD74LV164A

13

Package Dimensions

Hitachi Code
JEDEC
EIAJ
Weight

(reference value)

FP-16DA
—
Conforms

0.24 g

0.22 ± 0.05

0.42 ± 0.08

0.12

0.15

M

2.20 Max

5.5

10.06

0.80 Max

16

9

1

8

10.5 Max

+ 0.20
– 0.30

7.80

0.70 ± 0.20

0

° – 8°

0.10 ± 0.10

1.15

1.27

0.40

± 0.06

0.20 ± 0.04

Dimension including the plating thickness

Base material dimension

HD74LV164A

14

Hitachi Code
JEDEC
EIAJ
Weight

(reference value)

FP-16DN
Conforms
Conforms

0.15 g

Unit: mm

*Dimension including the plating thickness

Base material dimension

1.27

16

9

1

8

0.15

0.25

M

1.75 Max

3.95

*0.22 ± 0.03

9.9

0° – 8°

10.3 Max

+ 0.10
– 0.30

6.10

+ 0.67
– 0.20

0.60

+ 0.11

– 0.04

0.14

*0.42 ± 0.08

0.635 Max

0.40 ± 0.06

0.20 ± 0.03

1.08

HD74LV164A

15

0.50 ± 0.10

0° – 8°

0.17 ± 0.05

6.40 ± 0.20

0.10

1.10 Max

0.13

M

0.65

18

16 9

4.40

5.0

5.3 Max

0.07

+0.03

–0.04

0.65 Max

1.0

Hitachi Code
JEDEC
EIAJ
Weight

(reference value)

TTP-16DA
—
—

0.05 g

0.20 ± 0.06

+ 0.08
– 0.07

0.22

0.15 ± 0.04

Dimension including the plating thickness

Base material dimension

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of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail­safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.

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