Page 1
HD74LV163A
Synchronous 4-bit Binary Counter (Synchronous Clear)
ADE-205-265B (Z)
3rd Edition
April 2000
Description
The HD74LV163A is 4-bit binary counters. All flip flops are clocked simultaneously on the low to high to
transition (positive edge) of the clock input waceform. These counters may be preset using the load input.
Presetting of all four flip flops is synchronous to the rising edge of clock. When load is held low counting
is disabled and the data on the A, B, C and D inputs is loaded into the counter on the rising edge clock. If
the load input is taken high before the positive edge of clock the count operation will be unaffected.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
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HD74LV163A
Function Table
Inputs Outputs
CLR LOAD ENP ENT CLK QA QB QC QD
LXXX↑ LLLL
HLX X↑ ABCD
HHXL ↑ No change
HHL X↑ No change
HHHH↑ Count up
XXXX↓ No change
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
A, B, C, D: Data input
Carry = ENT • QA • QB • QC • QD
Pin Arrangement
CLR
CK
ENP
GND
V
1
2
3
A
4
B
5
C
6
D
7
8
(Top view)
16
15
14
13
12
11
10
9
CC
CARRY
OUTPUT
QA
QB
QC
QD
ENT
LOAD
2
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HD74LV163A
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage range V
Input voltage range*
Output voltage range*
1
1, 2
Input clamp current I
Output clamp current I
Continuous output current I
Continuous current through
V
or GND
CC
Maximum power dissipation
at Ta = 25°C (in still air)*
3
CC
V
I
V
O
IK
OK
O
or I
I
CC
GND
P
T
Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
–0.5 to 7.0 V
–0.5 to 7.0 V
–0.5 to VCC + 0.5 V Output: H or L
–0.5 to 7.0 VCC: OFF
–20 mA VI < 0
±50 mA VO < 0 or VO > V
±25 mA VO = 0 to V
CC
±50 mA
785 mW SOP
500 TSSOP
CC
3
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HD74LV163A
Recommended Operating Conditions
Item Symbol Min Max Unit Conditions
Supply voltage range V
Input voltage range V
Output voltage range V
Output current I
CC
I
O
OH
I
OL
Input transition rise or fall rate ∆t /∆v 0 200 ns/V VCC = 2.3 to 2.7 V
Operating free-air temperature Ta –40 85 °C
Note: Unused or floating inputs must be held high or low.
2.0 5.5 V
0 5.5 V
0VCCV H or L
— –50 µAV
—–2 mAV
—–6 V
= 2.0 V
CC
= 2.3 to 2.7 V
CC
= 3.0 to 3.6 V
CC
— –12 VCC = 4.5 to 5.5 V
—50 µAV
= 2.0 V
CC
— 2 mA VCC = 2.3 to 2.7 V
—6 V
—12 V
= 3.0 to 3.6 V
CC
= 4.5 to 5.5 V
CC
0 100 VCC = 3.0 to 3.6 V
020 V
= 4.5 to 5.5 V
CC
4
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Logic Diagram
HD74LV163A
Enable
Data
Inputs
CLK
CLR
LOAD
DCKQ
Q
A
Q
P
T
A
Output
Output
DCKQ
Q
Q
B
B
Output
DCKQ
Q
Q
C
C
Output
DCKQ
Q
Q
D
D
Carry
Output
5
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HD74LV163A
Timing Diagram
CLR
LOAD
A
Data
Inputs
Out
puts
CLK
ENP
ENT
Q
Q
Q
Q
Carry
B
C
D
A
B
C
D
12 13 14 15 0
Count
PresetClear
12
Inhibit
6
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HD74LV163A
DC Electrical Characteristics
• Ta = –40 to 85°C
Item Symbol VCC (V)* Min Typ Max Unit Test Conditions
Input voltage V
Output voltage V
Input current I
Quiescent
IH
V
IL
OH
V
OL
IN
I
CC
supply current
Output leakage
I
OFF
current
Input
C
IN
capacitance
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
2.0 1.5 — — V
2.3 to 2.7 VCC × 0.7 — —
3.0 to 3.6 VCC × 0.7 — —
4.5 to 5.5 VCC × 0.7 — —
2.0 — — 0.5
2.3 to 2.7 — — VCC × 0.3
3.0 to 3.6 — — VCC × 0.3
4.5 to 5.5 — — VCC × 0.3
Min to
VCC – 0.1 — — V IOL = –50 µA
Max
2.3 2.0 — — IOL = –2 mA
3.0 2.48 — — IOL = –6 mA
4.5 3.8 — — IOL = –12 mA
Min to
— — 0.1 IOL = 50 µA
Max
2.3 — — 0.4 IOL = 2 mA
3.0 — — 0.44 IOL = 6 mA
4.5 — — 0.55 IOL = 12 mA
0 to 5.5 — — ±1 µAVIN = 5.5 V or GND
5.5 — — 20 µAVIN = VCC or GND, IO = 0
0——5 µAVO = 5.5 V
3.3 — 1.7 — pF VI = VCC or GND
7
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HD74LV163A
Switching Characteristics
• VCC = 2.5 ± 0.2 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test Conditions
Maximum
clock
frequency
Propagation
delay time
Setup time t
Hold time t
Pulse
width
fmax 50 90 — 40 — MHz CL = 15 pF
30 60 — 25 — CL = 50 pF
t
PLH/tPHL
— 11.1 16.2 1.0 19.5 ns CL = 15 pF CLK Q
— 14.3 19.2 1.0 22.5 CL = 50 pF
t
PLH/tPHL
Count
— 11.5 17.0 1.0 20.5 CL = 15 pF CLK Carry
— 14.7 20.0 1.0 23.5 CL = 50 pF
mode
t
PLH/tPHL
Load
— 13.8 20.6 1.0 24.5 CL = 15 pF CLK Carry
— 17.0 23.6 1.0 27.5 CL = 50 pF
mode
t
PLH/tPHL
— 10.3 15.7 1.0 19.0 CL = 15 pF ENT Carry
— 14.0 18.7 1.0 22.0 CL = 50 pF
su
7.5 — — 8.5 — ns Data before CLK ↑
10.0 — — 11.5 — LOAD before CLK ↑
9.5 — — 11.0 — ENT, ENP before
6.0 — — 6.0 — CLR before CLK ↑
h
1.5 — — 1.5 — ns
1.5 — — 1.5 — CLR after CLK ↑
t
w
7.0 — — 7.0 — ns CLK H or L
FROM
(Input)
CLK ↑
TO
(Output)
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Switching Characteristics (cont)
• VCC = 3.3 ± 0.3 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test Conditions
Maximum
clock
frequency
Propagation
delay time
Setup time t
Hold time t
Pulse
width
t
max
t
PLH/tPHL
t
PLH/tPHL
Count
mode
t
PLH/tPHL
Load
mode
t
PLH/tPHL
su
h
t
w
80 130 — 70 — MHz CL = 15 pF
55 85 — 50 — CL = 50 pF
— 8.3 12.8 1.0 15.0 ns CL = 15 pF CLK Q
— 10.8 16.3 1.0 18.5 CL = 50 pF
— 8.7 13.6 1.0 16.0 CL = 15 pF CLK Carry
— 11.2 17.1 1.0 19.5 CL = 50 pF
— 11.0 17.2 1.0 20.0 CL = 15 pF CLK Carry
— 13.5 20.7 1.0 23.5 CL = 50 pF
— 7.5 12.3 1.0 14.5 CL = 15 pF ENT Carry
— 10.5 15.8 1.0 18.0 CL = 50 pF
5.5 — — 6.5 — ns Data before CLK ↑
8.0 — — 9.5 — LOAD before CLK ↑
7.5 — — 9.0 — ENT, ENP before
4.0 — — 4.0 — CLR before CLK ↑
1.0 — — 1.0 — ns
1.0 — — 1.0 — CLR after CLK ↑
5.0 — — 5.0 — ns CLK H or L
HD74LV163A
FROM
(Input)TO(Output)
CLK ↑
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Page 10
HD74LV163A
Switching Characteristics (cont)
• VCC = 5.0 ± 0.5 V
Ta = 25°C Ta = –40 to 85°C
Item Symbol Min Typ Max Min Max Unit Test Conditions
Maximum
clock
frequency
Propagation
delay time
Setup time t
Hold time t
Pulse
width
t
max
t
PLH/tPHL
t
PLH/tPHL
Count
mode
t
PLH/tPHL
Load
mode
t
PLH/tPHL
su
h
t
w
135 185 — 115 — MHz CL = 15 pF
95 125 — 85 — CL = 50 pF
— 4.9 8.1 1.0 9.5 ns CL = 15 pF CLK Q
— 8.7 10.1 1.0 11.5 CL = 50 pF
— 4.9 8.1 1.0 9.5 CL = 15 pF CLK Carry
— 6.4 10.1 1.0 20.0 CL = 50 pF
— 6.2 10.3 1.0 12.0 CL = 15 pF CLK Carry
— 7.7 12.3 1.0 14.0 CL = 50 pF
— 4.9 8.1 1.0 9.5 CL = 15 pF ENT Carry
— 6.4 10.1 1.0 11.5 CL = 50 pF
4.5 — — 4.5 — ns Data before CLK ↑
5.0 — — 6.0 — LOAD before CLK ↑
5.0 — — 6.0 — ENT, ENP before
3.5 — — 3.5 — CLR before CLK ↑
1.0 — — 1.0 — ns
1.5 — — 1.5 — CLR after CLK ↑
5.0 — — 5.0 — ns CLK H or L
FROM
(Input)TO(Output)
CLK ↑
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Operating Characteristics
• CL = 50 pF
Item Symbol V
Power
C
PD
dissipation
capacitance
(V) Min Typ Max Unit Test Conditions
CC
3.3 — 17.3 — pF f = 10 MHz
5.0 — 20.6 —
Noise Characteristics
• CL = 50 pF
Item Symbol V
Quiet output,
V
OL (P)
maximum
dynamic V
Quiet output,
OL
V
OL (V)
minimum
dynamic V
Quiet output,
OL
V
OH (V)
minimum
dynamic V
High-level
OH
V
IH (D)
dynamic
input voltage
Low-level
V
IL (D)
dynamic
input voltage
(V) Min Typ Max Unit Test Conditions
CC
3.3 — 0.3 0.8 V
3.3 — –0.3 –0.8
3.3 — 3.0 —
3.3 2.31 — — V
3.3 — — 0.99
HD74LV163A
Ta = 25°C
Ta = 25°C
11
Page 12
HD74LV163A
Test Circuit
Measurement point
*
C
L
1. C includes the probe and jig capacitance.Note:
L
12
Page 13
Waveform
Waveform – 1
Count mode
CLK
Q, CARRY
Waveform – 2
Preset mode
LOAD
t
WH
50% 50%
t
pLH
50%
t
WL
t
pHL
50%
HD74LV163A
V
CC
GND
V
OH
50%50%
V
OL
V
CC
A to D
CLK
Q, CARRY
t
su
t
suth
t
h
50%
50%
t
pLH, tpHL
50%
t
t
su
h
50%
GND
V
CC
GND
V
OH
V
OL
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HD74LV163A
Waveform – 3
Waveform – 4
Count enable mode
ENP
ENT
CLK
Q
Clear mode
50%
t
su
50%
t
h
50% 50%
t
t
su
h
V
CC
GND
V
CC
GND
V
OH
V
OL
CLR
CLK
Q, CARRY
50% 50%
t
suth
50%
V
CC
GND
V
CC
GND
V
OH
V
OL
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Page 15
Waveform – 5
Cascade mode
(set to maximum count number)
HD74LV163A
V
CC
Application
Cascade circuitry
H: COUNT
L: DISABLE
ENT
50% 50%
GND
V
CARRY
t
pLH
Note: 1. Input waveform: PRR≤1 MHz, duty cycle 50%, t ≤3 ns, t ≤3 ns
INPUTS
INPUTS
50% 50%
t
pHL
r
INPUTS
V
OH
OL
f
H: COUNT
L: DISABLE
CLR
CLK
LD A B C D
ENP
ENT CARRY
CK
CLR
QA QB QC QD
OUTPUT
LD A B C D
ENP
ENT CARRY
CK
CLR
QA QB QC QD
OUTPUT
LD A B C D
ENP
ENT CARRY
CK
CLR
QA QB QC QD
OUTPUT
to next stages
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HD74LV163A
Package Dimensions
16
10.06
10.5 Max
9
5.5
1
0.80 Max
1.27
0.42 ± 0.08
± 0.06
0.40
Dimension including the plating thickness
Base material dimension
8
0.12
0.10 ± 0.10
0.15
M
2.20 Max
7.80
0.22 ± 0.05
0.20 ± 0.04
0.70 ± 0.20
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
+ 0.20
– 0.30
1.15
0
° – 8°
FP-16DA
—
Conforms
0.24 g
16
Page 17
16
HD74LV163A
Unit: mm
9.9
10.3 Max
9
1
1.27
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.25
+ 0.11
– 0.04
0.14
0.15
3.95
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
0.60
Hitachi Code
JEDEC
EIAJ
Weight
+ 0.10
– 0.30
0° – 8°
+ 0.67
– 0.20
(reference value)
FP-16DN
Conforms
Conforms
0.15 g
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HD74LV163A
+ 0.08
0.22
– 0.07
0.20 ± 0.06
5.0
5.3 Max
16 9
4.40
18
0.65
M
0.13
0.65 Max
1.0
6.40 ± 0.20
0.10
1.10 Max
Dimension including the plating thickness
Base material dimension
0.17 ± 0.05
0.15 ± 0.04
+0.03
–0.04
0.07
0° – 8°
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
0.50 ± 0.10
TTP-16DA
—
—
0.05 g
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HD74LV163A
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as in aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safe
devices, so that the equipment incorporating the Hitachi product does not cause bodily injury, fire or
other consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL NorthAmerica : http:semiconductor.hitachi.com/
For further information write to:
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Tel: <1> (408) 433-1990
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Electronic components Group
Dornacher Stra§e 3
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Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
Electronic Components Group.
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Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
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Tel: 535-2100
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Taipei Branch Office
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Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Copyright ' Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
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7/F., North Tower, World Finance Centre,
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