Page 1
HD74HCT564/HD74HCT574
Octal D-type Flip-Flops (with 3-state outputs)
Description
These devices are positive edge triggered flip-flops. The difference between HD74HCT564 and
HD74HCT574 is only that the former has inverting outputs and the latter has non-inverting outputs.
Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs
on positive going transitions of the clock (CK) input. When a high logic level is applied to the output
control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the
other inputs and the state of the storage elements.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (D to Q, Q) = 15 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Outputs
Output Control Clock Data HD74HCT564 HD74HCT574
L HLH
L LHL
LL X Q
HX X Z Z
0
Q
0
Page 2
HD74HCT564/HD74HCT574
Pin Arrangement
HD74HCT564
Output
Control
1D
2D
3D
4D
5D
6D
7D
8D
GND
10
V
OE
OE
OE
OE
20
CC
19
18
17
16
15
14
13
12
11
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Clock
QD
QD
QD
QD
1
2
OE
3
QD
4
OE
5
QD
6
OE
7
QD
8
OE
9
QD
(Top view)
2
Page 3
HD74HCT574
HD74HCT564/HD74HCT574
Output
Control
1D
2D
3D
4D
5D
6D
7D
8D
GND
10
V
OE
OE
OE
OE
20
CC
19
18
17
16
15
14
13
12
11
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Clock
QD
QD
QD
QD
1
2
OE
3
QD
4
OE
5
QD
6
OE
7
QD
8
OE
9
QD
(Top view)
3
Page 4
HD74HCT564/HD74HCT574
Block Diagram
HD74HCT564
CLK
OC
1D
2D
3D
4D
5D
6D
7D
8D
D
CQ
C
D
CQ
C
D
CQ
C
D
CQ
C
D
CQ
C
D
CQ
C
D
CQ
C
D
CQ
C
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
4
Page 5
HD74HCT574
HD74HCT564/HD74HCT574
Absolute Maximum Ratings
CLK
OC
1D
2D
3D
4D
5D
6D
7D
8D
D
C Q
C
D
C Q
C
D
C Q
C
D
C Q
C
D
C Q
C
D
C Q
C
D
C Q
C
D
C Q
C
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Item Symbol Rating Unit
Supply voltage range V
Input voltage V
Output voltage V
DC current drain per pin I
CC
IN
OUT
OUT
DC current drain per VCC, GND ICC, I
DC input diode current I
DC output diode current I
Power dissipation per package P
IK
OK
T
GND
–0.5 to +7.0 V
–0.5 to VCC + 0.5 V
–0.5 to VCC + 0.5 V
±35 mA
±75 mA
±20 mA
±20 mA
500 mW
Storage temperature Tstg –65 to +150 °C
5
Page 6
HD74HCT564/HD74HCT574
DC Characteristics
Ta = –40 to
Ta = 25°C
Item Symbol Min Typ Max Min Max Unit V
Input voltage V
Output voltage V
IH
V
IL
OH
2.0 — — 2.0 — V 4.5 to
— — 0.8 — 0.8 V 4.5 to
4.4 — — 4.4 — V 4.5 Vin = VIH or VILIOH = –20 µA
4.18 — — 4.13 — 4.5 IOH = –6 mA
V
OL
— — 0.1 — 0.1 V 4.5 Vin = VIH or VILIOL = 20 µA
— — 0.26 — 0.33 4.5 IOL = 6 mA
Off-state output
I
OZ
——±0.5 — ±5.0 µA 5.5 Vin = VIH or VIL,
current
Input current Iin — — ±0.1 — ±1.0 µA 5.5 Vin = VCC or GND
Quiescent current I
CC
— — 4.0 — 40 µA 5.5 Vin = VCC or GND, Iout = 0 µA
+85°C Test Conditions
(V)
CC
5.5
5.5
Vout = V
or GND
CC
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = –40 to
Ta = 25°C
Item Symbol Min Typ Max Min Max Unit V
Maximum clock
f
max
— — 30 — 24 ns 4.5
frequency
Propagation delay t
time t
Output enable t
time t
Output disable t
time t
Setup time t
Hold time t
Pulse width t
Output rise/fall t
time t
PLH
PHL
ZL
ZH
LZ
HZ
su
h
w
TLH
THL
— 14 31 — 39 ns 4.5
— 15 31 — 39 4.5
— 16 30 — 38 ns 4.5
— 16 30 — 38 4.5
— 15 30 — 38 ns 4.5
— 18 30 — 38 4.5
12 3 — 25 — ns 4.5
5 –2 — 5 — ns 4.5
16 7 — 20 — ns 4.5
— 4 12 — 15 ns 4.5
— 4 12 — 15 4.5
Input capacitance Cin — 5 10 — 10 pF —
+85°C Test Conditions
(V)
CC
6
Page 7
24.50
25.40 Max
Unit: mm
1120
6.30
1
0.89
1.27 Max
2.54 ± 0.25
1.30
10
0.48 ± 0.10
7.00 Max
0.51 Min
2.54 Min 5.08 Max
Hitachi Code
JEDEC
EIAJ
Weight
7.62
+ 0.11
0.25
– 0.05
0° – 15°
(reference value)
DP-20N
—
Conforms
1.26 g
Page 8
20
Unit: mm
12.6
13 Max
11
5.5
1
0.80 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
10
0.12
0.10 ± 0.10
0.15
M
2.20 Max
7.80
0.20 ± 0.04
*0.22 ± 0.05
0.70 ± 0.20
Hitachi Code
JEDEC
EIAJ
Weight
(reference value)
+ 0.20
– 0.30
1.15
0° – 8°
FP-20DA
—
Conforms
0.31 g
Page 9
20
Unit: mm
12.8
13.2 Max
11
7.50
1
0.935 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
10
0.12
0.20 ± 0.10
0.15
2.65 Max
M
10.40
0.25 ± 0.04
*0.27 ± 0.05
0.70
Hitachi Code
JEDEC
EIAJ
Weight
+ 0.25
– 0.40
1.45
+ 0.57
– 0.30
(reference value)
0° – 8°
FP-20DB
Conforms
—
0.52 g
Page 10
20 11
110
+0.08
*0.22
–0.07
0.20 ± 0.06
6.50
6.80 Max
0.65 Max
0.65
0.13
Unit: mm
4.40
1.0
M
6.40 ± 0.20
0.10
1.10 Max
*Dimension including the plating thickness
Base material dimension
0.15 ± 0.04
*0.17 ± 0.05
+0.03
–0.04
0.07
0° – 8°
Hitachi Code
JEDEC
EIAJ
(reference value)
Weight
0.50 ± 0.10
TTP-20DA
—
—
0.07 g
Page 11
Cautions
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received the latest product standards or specifications before final design, purchase or use.
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contact Hitachi’s sales office before using the product in an application that demands especially high
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of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
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failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
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