Datasheet HD74HC73 Datasheet (HIT)

Page 1
HD74HC73
Dual J-K Flip-Flops (with Clear)
Description
The flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each flip-flop has independent, J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and accomplished by a low level on the input.
Features
• High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C)
Function Table
Inputs Outputs Clear Clock J K Q Q
LX X X L H H L L No change
H LHLH H HL HL H H H Toggle H L X X No change
H H X X No change H X X No change
Page 2
HD74HC73
Pin Arrangement
Block Diagram
CLR
J
K
1CK
1CLR
1K
V
CC
2CK
2CLR
2J
14
13
12
11
10
1J
1Q
1Q
GND
2K
9
2Q
8
2Q
Q
Q
CK
1
2
3
4
5
6
7
CK
CK
CLR
J
CK
K
K
CK
J
CLR
(Top view)
CK
Q
Q
Q
Q
CK
CK
CK
CK
CK
2
CK
CK
Page 3
HD74HC73
DC Characteristics
Ta = –40 to
Ta = 25°C
Item Symbol V
Input voltage V
IH
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 1.5 — — 1.5 — V
4.5 3.15 — — 3.15 —
6.0 4.2 — — 4.2 —
V
IL
2.0 — — 0.5 — 0.5 V
4.5 — — 1.35 — 1.35
6.0 — — 1.8 — 1.8
Output voltage V
OH
2.0 1.9 2.0 — 1.9 — V Vin = VIH or VILIOH = –20 µA
4.5 4.4 4.5 — 4.4 —
6.0 5.9 6.0 — 5.9 —
4.5 4.18 — — 4.13 — IOH = –4 mA
6.0 5.68 — — 5.63 — IOH = –5.2 mA
V
OL
2.0 — 0.0 0.1 — 0.1 V Vin = VIH or VILIOL = 20 µA
4.5 — 0.0 0.1 — 0.1
6.0 — 0.0 0.1 — 0.1
4.5 — — 0.26 — 0.33 IOL = 4 mA
6.0 — — 0.26 — 0.33 IOL = 5.2 mA Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply
I
CC
6.0 — — 2.0 — 20 µA Vin = VCC or GND, Iout = 0 µA current
+85°C
3
Page 4
HD74HC73
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = –40 to
Ta = 25°C
Item Symbol V
Maximum clock f
max
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 — — 6 — 5 MHz frequency 4.5 — — 30 — 24
6.0 — — 35 — 28 Propagation delay t time t
PLH
PHL
2.0 — — 150 — 190 ns Clock to Q or Q
4.5 — 18 30 — 38
6.0 — — 26 — 33
2.0 — — 140 — 175 Clear to Q or Q
4.5 — 18 28 — 35
6.0 — — 24 — 30 Pulse width t
w
2.0 80 — — 100 — ns Clock, Clear
4.5 16 8 — 20 —
6.0 14 — — 17 — Setup time t
su
2.0 100 — — 125 — ns Data to clock
4.5 20 3 — 25 —
6.0 17 — — 21 — Hold time t
h
2.0 5 — — 5 — ns Clock to data
4.5 5 –2 — 5 —
6.0 5 — — 5 — Removal time t
rem
2.0 100 — — 125 — ns Clear to clock
4.5 20 –3 — 25 —
6.0 17 — — 21 — Output rise/fall t time t
TLH
THL
2.0 — — 75 — 95 ns
4.5 — 5 15 — 19
6.0 — — 13 — 16 Input capacitance Cin — — 5 10 — 10 pF
+85°C
4
Page 5
1
19.20
20.32 Max
1.30
Unit: mm
814
6.30
7.40 Max
7
2.54 ± 0.25
2.39 Max
0.48 ± 0.10
2.54 Min 5.06 Max
0.51 Min
Hitachi Code JEDEC EIAJ Weight
7.62
+ 0.10
0.25
– 0.05
0° – 15°
(reference value)
DP-14 Conforms Conforms
0.97 g
Page 6
14
1.27
10.5 Max
1
1.42 Max
10.06
Unit: mm
8
5.5
7
+ 0.20
7.80
– 0.30
2.20 Max *0.22 ± 0.05
1.15
0.20 ± 0.04 0° – 8°
0.70 ± 0.20
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
0.12
0.10 ± 0.10
0.15
M
Hitachi Code JEDEC EIAJ
(reference value)
Weight
FP-14DA — Conforms
0.23 g
Page 7
9.05 Max
14
Unit: mm
8.65
8
*Pd plating
1
0.635 Max
1.27
*0.40 ± 0.06
7
+ 0.11
– 0.04
0.14
0.25
3.95
1.75 Max
0.15
M
6.10
1.08
*0.20 ± 0.05
+ 0.67
0.60
– 0.20
Hitachi Code JEDEC EIAJ Weight
+ 0.10 – 0.30
0° – 8°
(reference value)
FP-14DN Conforms Conforms
0.13 g
Page 8
5.30 Max
14 8
17
+0.08
*0.22
–0.07
0.20 ± 0.06
5.00
0.83 Max
0.65
0.13
Unit: mm
4.40
1.0
M
6.40 ± 0.20
0.10
1.10 Max
*Dimension including the plating thickness
Base material dimension
0.15 ± 0.04
*0.17 ± 0.05
+0.03
–0.04
0.07
0° – 8°
Hitachi Code JEDEC EIAJ
(reference value)
Weight
0.50 ± 0.10
TTP-14D — —
0.05 g
Page 9
Cautions
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4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail­safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.
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