Datasheet HD74HC670 Datasheet (HIT)

Page 1
HD74HC670
4-by-4 Register File (with 3-state outputs)
Description
The HD74HC670, 16-bit register file is organized as 4 words of 4 bits each and separate on-chip decoding is provided for addressing the four word locations to either write-in or retrieve data.
This permits simultaneous writing into one location and reading from another word location. Four data inputs are available which are used to supply the 4-bit word to be stored. Location of the word is determined by the write-address inputs A and B in conjunction with a write-enable signal. Data applied at the inputs should be in its true form. That is, if a high-level signal is desired from the output, a high-level is applied at the data input for that particular bit location. The latch inputs are arranged so that new data will be accepted only if both internal address gate inputs are high. When this condition exists, data at the D input is transferred to the latch output. When the write-enable input, (GW) is high, the data inputs are inhibited and their levels can cuase no change in the information stored in the internal latches. When the read-enable input, (GR) is high, the data outputs are inhibited and go into the high-impedance state. The individual address lines permit direct acquisition of data stored in any four of the latches. Four individual decoding gates are used to complete the address for reading a word. when the read address is made in conjunction with the read-enable signal, the word appears at the four outputs.
Features
High Speed Operation: tpd (Read Select to Q) = 21 ns typ (CL = 50 pF)
High Output Current: Fanout of 15 LSTTL Loads
Wide Operating Voltage: VCC = 2 to 6 V
Low Input Current: 1 µA max
Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Page 2
HD74HC670
Function Table
Write Inputs Word W
B
W
A
L L L Q = D Q LH L Q HL L Q HH L Q XX H Q
Read Inputs Outputs R
B
R
A
LL L W LH L W HL L W HH L W XXHZZZZ
H : high level L : low level X : irrelevant Z : high impedance (off) (Q = D) : The four selected internal flip-flop outputs will assume the states applied to the four external data
inputs.
Q
: The level of Q before the indicated input conditions were established.
0
W
: The first bit of word 0, etc.
0 B1
G
W
G
R
0123
0
0
0
0
Q
1
0 B1
1 B1
2 B1
3 B1
0
Q = D Q Q
0
Q
0
Q
0
Q
2
W0 B
2
W1 B
2
W2 B
2
W3 B
2
Q
0
0
Q = D Q Q
0
Q
0
Q
3
W0 B
3
W1 B
3
W2 B
3
W3 B
3
Q
0
Q
0
0
Q = D Q
0
Q
4
W0 B
4
W1 B
4
W2 B
4
W3 B
4
2
Page 3
Pin Arrangement
HD74HC670
V
1
D
2
16
CC
Logic Diagram
Data
Read
select
Outputs
D
D
R
R
Q
Q
GND
D
2
3
3
4
4
B
5
A
D
D
R
R
2
D
W
W
C
1
A
B
W
3
4
B
A
15
14
13
12
Data D
1
W
A
W
B
Write
Write select
Enable
Read
6
4
7
3
Q
4
Q
3
C
Q
Q
2
8
11
R
Q
10
1
1
Outputs
Q
9
2
(Top view)
To other three bits
Data
D
G
D
G
D
G
D
G
W
A
W
B
G
W
Q
Q
Q
Q
V
CC
Q
R
A
G
R
R
B
3
Page 4
HD74HC670
DC Characteristics
Ta = –40 to
Ta = 25°C
Item Symbol V
Input voltage V
IH
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 1.5 — 1.5 V
4.5 3.15 — 3.15 —
6.0 4.2 — 4.2
V
IL
2.0 0.5 — 0.5 V
4.5 1.35 — 1.35
6.0 1.8 — 1.8
Output voltage V
OH
2.0 1.9 2.0 — 1.9 V Vin = VIH or VILIOH = –20 µA
4.5 4.4 4.5 — 4.4
6.0 5.9 6.0 — 5.9
4.5 4.18 — 4.13 — IOH = –6 mA
6.0 5.68 — 5.63 — IOH = –7.8 mA
V
OL
2.0 0.0 0.1 — 0.1 V Vin = VIH or VILIOL = 20 µA
4.5 0.0 0.1 — 0.1
6.0 0.0 0.1 — 0.1
4.5 0.26 — 0.33 IOL = 6 mA
6.0 0.26 — 0.33 IOL = 7.8 mA
Off-state output
I
OZ
6.0 ±0.5 — ±5.0 µA Vin = VIN or VIL,
current Input current Iin 6.0 ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply
I
CC
6.0 4.0 — 40 µA Vin = VCC or GND, Iout = 0 µA
current
+85°C
Vout = V
or GND
CC
4
Page 5
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = –40 to
Item Symbol V
Propagation delay t time t
Output enable t time t
Output disable t time t
Pulse width t
Setup time t
Hold time t
PLH
PHL
t
PLH
t
PHL
t
PLH
t
PHL
ZH
ZL
HZ
LZ
w
su
t
su
h
Ta = 25°C
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 160 — 200 ns Read select to Q
4.5 21 32 40
6.0 27 34
2.0 200 — 250 ns Write enable to Q
4.5 24 40 50
6.0 34 43
2.0 150 — 190 ns Data to Q
4.5 18 30 38
6.0 26 33
2.0 150 — 190 ns
4.5 18 30 38
6.0 26 33
2.0 150 — 190 ns
4.5 17 30 38
6.0 26 33
2.0 80 100 ns
4.5 16 20
6.0 14 17
2.0 60 75 ns Data to Write enable
4.5 12 4 15
6.0 10 13
2.0 60 75 ns Write select to Write enable
4.5 12 15
6.0 10 13
2.0 50 63 ns Write enable to Data
4.5 10 6 13
6.0 9 11
2.0 50 63 ns Write enable to Write select
4.5 10 13
6.0 9 11
+85°C
HD74HC670
5
Page 6
HD74HC670
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont)
Ta = –40 to
Ta = 25°C
Item Symbol V
Latch time for new t
latch
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.5 100 — 125 ns
data 4.5 20 25
6.0 17 21 — Output rise/fall t time t
TLH
THL
2.0 75 95 ns
4.5 5 15 19
6.0 13 16 Input capacitance Cin 5 10 10 pF
+85°C
6
Page 7
19.20
20.00 Max
16 9
1.3
Unit: mm
6.30
7.40 Max
81
1.11 Max
2.54 ± 0.25
0.48 ± 0.10
5.06 Max
2.54 Min
0.51 Min
Hitachi Code JEDEC EIAJ Weight
7.62
+ 0.13
0.25
– 0.05
0° – 15°
(reference value)
DP-16 Conforms Conforms
1.07 g
Page 8
16
Unit: mm
10.06
10.5 Max 9
5.5
1
0.80 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.12
0.10 ± 0.10
0.15
M
2.20 Max
7.80
0.20 ± 0.04
*0.22 ± 0.05
0.70 ± 0.20
Hitachi Code JEDEC EIAJ
(reference value)
Weight
+ 0.20 – 0.30
1.15
0° – 8°
FP-16DA — Conforms
0.24 g
Page 9
16
Unit: mm
9.9
10.3 Max 9
1
1.27
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.25
+ 0.11
– 0.04
0.14
0.15
3.95
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
0.60
Hitachi Code JEDEC EIAJ Weight
+ 0.10 – 0.30
0° – 8°
+ 0.67 – 0.20
(reference value)
FP-16DN Conforms Conforms
0.15 g
Page 10
Cautions
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4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail­safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
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7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.
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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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