Page 1
HD74HC668/HD74HC669
Synchronous UP/Down Decade Counter
Synchronous Up/Down 4-bit binary Counter
Description
This synchronous presettable decade counter features an internal carry look-ahead for cascading in highspeed counting applications. Synchronous operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each other when so instructed by the countenable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that
are normally associated with asynchronous (ripple-clock) counters.
A buffered clock input triggers the four master-slave flip-flops on the rising (positive going) edge of the
clock waveform. This counter is fully programmable; that is, the outputs may each be preset to either level.
The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is
synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree
with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are two count enable inputs and a carry
output. Both count enable inputs (P and T) must be low to count. The direction of the count is determined
by the level of the up/down input. when the input is high, the counter counts up; when low, it counts down.
Input T is fed forward to enable the carry output. The carry output thus enabled will produce a low-level
output pulse with a duration approximately equal to the high portion of the QA output when counting up
and approximately equal to the low portion of the QA output when counting down. This low level overflow
carry pulse can be used to enable successive cascaded stages. Transitions at the enable P or T inputs are
allowed regardless of the level of the clock input. All inputs are diode-clamped to minimize transissionline effects, thereby simplifying system design. This counter features a fully independent clock circuit.
Changes at control inputs (enable P, Enable T, load, up/down) that will modify the operating mode have no
effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting)
will be dictated solely by the conditions meeting the stable setup and hold times.
Features
• High Speed Operation
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
Page 2
HD74HC668/HD74HC669
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Pin Arrangement
HD74HC668
Data
inputs
U/D
CK
Enable
P
GND
1
2
A
3
B
4
16
15
14
13
V
CC
Ripple
carry
output
Q
A
Q
B
Outputs
C
5
D
6
7
8
12
11
10
9
Q
C
Q
D
Enable T
Load
(Top view)
2
Page 3
HD74HC669
HD74HC668/HD74HC669
Data
inputs
U/D
CK
Enable
P
GND
1
2
A
3
B
4
16
15
14
13
V
CC
Ripple
carry
output
Q
A
Q
B
Outputs
C
5
D
6
7
8
12
11
10
9
Q
C
Q
D
Enable
T
Load
(Top view)
3
Page 4
HD74HC668/HD74HC669
Logic Diagram
HD74HC668
U/D
D
Load
Enable P
Enable T
A
D
B
D
C
L
Q
T
QIN
CK
L
Q
T
QIN
CK
L
Q
T
QIN
CK
V
CC
L
Q
T
QIN
CK
Q
A
Q
B
Q
C
Q
D
CK
D
D
RCO
4
Page 5
HD74HC669
HD74HC668/HD74HC669
CK
Load
U/D
Enable P
Enable T
QT
QIN
D
A
QT
QIN
D
B
QT
QIN
D
C
QT
QIN
D
D
Q
A
Q
B
Q
C
Q
D
RCO
V
CC
5
Page 6
HD74HC668/HD74HC669
Timing Chart
HD74HC668
Load
A
Data
inputs
Clock
U/D
Enable P and T
Q
Q
Q
Q
Ripple
carry
output
B
C
D
A
B
C
D
78901 2210 98722
Count up Inhibit Count down
Load
6
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HD74HC669
Load
Data
inputs
Clock
U/D
P and T
HD74HC668/HD74HC669
A
B
C
D
Q
A
Q
B
Ripple
carry
output
Q
C
Q
D
13 14 15 0 1 2 2 2 1 0 15 14 13
Count up Inhibit
Load
Count down
7
Page 8
HD74HC668/HD74HC669
DC Characteristics
Ta = –40 to
Ta = 25°C
Item Symbol V
Input voltage V
IH
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 1.5 — — 1.5 — V
4.5 3.15 — — 3.15 —
6.0 4.2 — — 4.2 —
V
IL
2.0 — — 0.5 — 0.5 V
4.5 — — 1.35 — 1.35
6.0 — — 1.8 — 1.8
Output voltage V
OH
2.0 1.9 2.0 — 1.9 — V Vin = VIH or VILIOH = –20 µA
4.5 4.4 4.5 — 4.4 —
6.0 5.9 6.0 — 5.9 —
4.5 4.18 — — 4.13 — IOH = –4 mA
6.0 5.68 — — 5.63 — IOH = –5.2 mA
V
OL
2.0 — 0.0 0.1 — 0.1 V Vin = VIH or VILIOL = 20 µA
4.5 — 0.0 0.1 — 0.1
6.0 — 0.0 0.1 — 0.1
4.5 — — 0.26 — 0.33 IOL = 4 mA
6.0 — — 0.26 — 0.33 IOL = 5.2 mA
Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND
Quiescent supply
I
CC
6.0 — — 4.0 — 40 µA Vin = VCC or GND, Iout = 0 µA
current
+85°C
8
Page 9
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = –40 to
Ta = 25°C
Item Symbol V
Maximum clock f
max
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 — — 5 — 4 MHz
Frequency 4.5 — — 27 — 21
6.0 — — 32 — 25
Propagation delay t
time t
PLH
PHL
2.0 — — 200 — 250 ns Clock to Ripple carry out
4.5 — — 40 — 50
6.0 — — 34 — 43
t
PLH
t
PHL
2.0 — — 225 — 280 ns Clock to Q
4.5 — — 45 — 56
6.0 — — 38 — 48
t
PLH
t
PHL
2.0 — — 150 — 190 ns Enable T to Ripple carry out
4.5 — — 30 — 38
6.0 — — 26 — 33
t
PLH
t
PHL
2.0 — — 200 — 250 ns U/D to Ripple carry out
4.5 — — 40 — 50
6.0 — — 34 — 43
Pulse width t
w
2.0 80 — — 100 — ns
4.5 16 — — 20 —
6.0 14 — — 17 —
Setup time t
su
2.0 100 — — 125 — ns Data to Clock
4.5 20 — — 25 —
6.0 17 — — 21 —
t
su
2.0 150 — — 190 — ns Enable P, T to Clock
4.5 30 — — 38 —
6.0 26 — — 33 —
t
su
2.0 150 — — 190 — ns Loadk to Clock
4.5 30 — — 38 —
6.0 26 — — 33 —
t
su
2.0 150 — — 190 — ns U/D to Clock
4.5 30 — — 38 —
6.0 26 — — 33 —
+85°C
HD74HC668/HD74HC669
9
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HD74HC668/HD74HC669
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont)
Ta = –40 to
Ta = 25°C
Item Symbol V
Hold time t
h
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 5 — — 5 — ns
4.5 5 — — 5 —
6.0 5 — — 5 —
Output rise/fall t
time t
TLH
THL
2.0 — — 75 — 95 ns
4.5 — 5 15 — 19
6.0 — — 13 — 16
Input capacitance Cin — — 5 10 — 10 pF
+85°C
10
Page 11
19.20
20.00 Max
16 9
1.3
Unit: mm
6.30
7.40 Max
81
1.11 Max
2.54 ± 0.25
0.48 ± 0.10
5.06 Max
2.54 Min
0.51 Min
Hitachi Code
JEDEC
EIAJ
Weight
7.62
+ 0.13
0.25
– 0.05
0° – 15°
(reference value)
DP-16
Conforms
Conforms
1.07 g
Page 12
16
Unit: mm
10.06
10.5 Max
9
5.5
1
0.80 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.12
0.10 ± 0.10
0.15
M
2.20 Max
7.80
0.20 ± 0.04
*0.22 ± 0.05
0.70 ± 0.20
Hitachi Code
JEDEC
EIAJ
(reference value)
Weight
+ 0.20
– 0.30
1.15
0° – 8°
FP-16DA
—
Conforms
0.24 g
Page 13
16
Unit: mm
9.9
10.3 Max
9
1
1.27
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.25
+ 0.11
– 0.04
0.14
0.15
3.95
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
0.60
Hitachi Code
JEDEC
EIAJ
Weight
+ 0.10
– 0.30
0° – 8°
+ 0.67
– 0.20
(reference value)
FP-16DN
Conforms
Conforms
0.15 g
Page 14
Cautions
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received the latest product standards or specifications before final design, purchase or use.
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contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
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products.
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