Datasheet HD74HC595 Datasheet (HIT)

Page 1
HD74HC595
8-bit Shift Register/Latch (with 3-state outputs)
Description
This device each contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output pins for cascading.
Both the shift register and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register state will always be one clock pulse ahead of the storage register.
• High Speed Operation: tpd (RCK to Q) = 17 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads (QA to QH outputs)
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
RCK SCK SCLR G Function
XXXHQ X X L X Shift register cleared QH’ = L X H X Shift register clocked Qn = Q
X H X Contents of shift register transferred to output latches
to QH high impedance
A
, QA = SER
n – 1
Page 2
HD74HC595
Pin Arrangement
1
Q
B VCC
2
C
Q
QD
3
QE
4
QF
5
QG
6
7
QH
GND
89
16
15
14
13
12
11
10
QA
SER
G
RCK
SCK
SCLR
H'
Q
(Top view)
Absolute Maximum Ratings
Item Symbol Rating Unit
Supply voltage range V Input voltage V Output voltage V Output current I DC current drain per VCC, GND ICC, I DC input diode current I DC output diode current I Power dissipation per package P
CC
IN
OUT
OUT
GND
IK
OK
T
Storage Temperature Tstg –65 to +150 °C
–0.5 to +7.0 V –0.5 to VCC + 0.5 V –0.5 to VCC + 0.5 V
±35 mA ±75 mA ±20 mA ±20 mA
500 mW
2
Page 3
Logic Diagram
G
RCK
HD74HC595
SER
R
R
R
R
R
DDQ
DDQ
DDQ
DDQ
DDQ
QA
QB
QC
QD
QE
SCK
SCLR
R
R
R
DDQ
DDQ
DDQ
QF
QG
Q
H
H'
Q
3
Page 4
HD74HC595
DC Characteristics
Ta = –40 to
Ta = 25°C
Item Symbol V
Input voltage V
IH
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 1.5 — — 1.5 — V
4.5 3.15 — — 3.15 —
6.0 4.2 — — 4.2 —
V
IL
2.0 — — 0.5 — 0.5 V
4.5 — — 1.35 — 1.35
6.0 — — 1.8 — 1.8
Output voltage V
OH
2.0 1.9 2.0 — 1.9 — V QA to Q
4.5 4.4 4.5 — 4.4 — Vin = VIH or V
6.0 5.9 6.0 — 5.9 —
4.5 4.18 — — 4.13 — IOH = –6 mA
6.0 5.68 — — 5.63 — IOH = –7.8 mA
V
OL
2.0 — 0.0 0.1 — 0.1 V QA to Q
4.5 — 0.0 0.1 — 0.1 Vin = VIH or V
6.0 — 0.0 0.1 — 0.1
4.5 — — 0.26 — 0.33 IOL = 6 mA
6.0 — — 0.26 — 0.33 IOL = 7.8 mA
Output voltage V
OH
2.0 1.9 2.0 — 1.9 — V Q’
4.5 4.4 4.5 — 4.4 — Vin = VIH or V
6.0 5.9 6.0 — 5.9 —
4.5 4.18 — — 4.13 — IOH = –4 mA
6.0 5.68 — — 5.63 — IOH = –5.2 mA
V
OL
2.0 — 0.0 0.1 — 0.1 V Q’
4.5 — 0.0 0.1 — 0.1 Vin = VIH or V
6.0 — 0.0 0.1 — 0.1
4.5 — — 0.26 — 0.33 IOL = 4 mA
6.0 — — 0.26 — 0.33 IOL = 5.2 mA
Off-state output
I
OZ
6.0 — — ±0.5 — ±5.0 µA Vin = VIH or VIL,
current Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply
I
CC
6.0 — — 4.0 — 40 µA Vin = VCC or GND, Iout = 0 µA
current
+85°C
H
H
Vout = V
H
H
or GND
CC
IL
IL
IL
IL
IOH = –20 µA
IOL = 20 µA
IOH = –20 µA
IOL = 20 µA
4
Page 5
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = –40 to
Ta = 25°C
Item Symbol V
Maximum clock f
max
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 — — 5 — 4 MHz
frequency 4.5 — — 27 — 21
6.0 — — 31 — 24 Propagation delay t time t
PLH
PHL
2.0 — — 115 — 145 ns SCK to QH’
4.5 — 12 23 — 29
6.0 — — 20 — 25
t
PLH
t
PHL
2.0 — — 150 — 190 ns RCK to Q
4.5 — 17 30 — 38
6.0 — — 26 — 33
t
PLH
2.0 — — 175 — 220 ns SCLR to QH’
4.5 — 20 35 — 44
6.0 — — 30 — 37 Output enable t time t
ZL
ZH
2.0 — — 150 — 190 ns
4.5 — 13 30 — 38
6.0 — — 26 — 33 Output disable t time t
LZ
HZ
2.0 — — 150 — 190 ns
4.5 — 15 30 — 38
6.0 — — 26 — 33 Setup time t
su
2.0 100 — — 125 — ns SER to SCK
4.5 20 1 — 25 —
6.0 17 — — 21 —
2.0 200 — — 250 — ns SCK to RCK
4.5 40 8 — 50 —
6.0 34 — — 43 — Pulse width t
w
2.0 80 — — 100 — ns
4.5 16 8 — 20 —
6.0 14 — — 17 — Removal time t
rem
2.0 100 — — 125 — ns
4.5 20 — — 25 —
6.0 17 — — 21 —
+85°C
HD74HC595
5
Page 6
HD74HC595
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont)
Ta = –40 to
Ta = 25°C
Item Symbol V
Hold time t
h
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 5 — — 5 — ns
4.5 5 1 — 5 —
6.0 5 — — 5 — Output rise/fall t time t
TLH
THL
2.0 — — 75 — 95 ns QH’
4.5 — 5 15 — 19
6.0 — — 13 — 16
2.0 — — 60 — 75 ns Q
4.5 — 4 12 — 15
6.0 — — 10 — 13 Input capacitance Cin — — 5 10 — 5 pF
+85°C
6
Page 7
19.20
20.00 Max
16 9
1.3
Unit: mm
6.30
7.40 Max
81
1.11 Max
2.54 ± 0.25
0.48 ± 0.10
5.06 Max
2.54 Min
0.51 Min
Hitachi Code JEDEC EIAJ Weight
7.62
+ 0.13
0.25
– 0.05
0° – 15°
(reference value)
DP-16 Conforms Conforms
1.07 g
Page 8
16
Unit: mm
10.06
10.5 Max 9
5.5
1
0.80 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.12
0.10 ± 0.10
0.15
M
2.20 Max
7.80
0.20 ± 0.04
*0.22 ± 0.05
0.70 ± 0.20
Hitachi Code JEDEC EIAJ
(reference value)
Weight
+ 0.20 – 0.30
1.15
0° – 8°
FP-16DA — Conforms
0.24 g
Page 9
16
Unit: mm
9.9
10.3 Max 9
1
1.27
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.25
+ 0.11
– 0.04
0.14
0.15
3.95
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
+ 0.67
0.60
– 0.20
Hitachi Code JEDEC EIAJ Weight
+ 0.10 – 0.30
0° – 8°
(reference value)
FP-16DN Conforms Conforms
0.15 g
Page 10
Cautions
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4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail­safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.
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