Datasheet HD74HC195 Datasheet (HIT)

Page 1

HD74HC195

4-bit Parallel-Access Shift Register

Description

This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; shift from QA towards QD.

Paralle loading is accomplished by applying the four bits of data, and taking the Shift/Load control Input low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the Shift/Load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K or toggle flip-flop as shown in the function table.

Features

• High Speed Operation: tpd (Clock to Q) = 13 ns typ (CL = 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC = 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

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HD74HC195

Function Table

Inputs

Shift/ Serial Parallel Outputs

Clear Load Clock J K ABCDQAQBQCQDQ

LXXXXXXXXLLLLH HL XXabcdabcdd

HHLXXXXXXQA0Q HH LHXXXXQA0Q

HH LLXXXXLQAnQ HH HHXXXXHQAnQ HH HLXXXXQAnQ

H : high level (steady state) L : low level (steady state) X : don’t care

: transition from low to high level.

a, b, c, d : the level of steady-state input at inputs A, B, C or D respectively. QA0, QB0, QC0, QD0: the level of QA, QB, QC or QD respectively, before the indicated steady-state input

conditions were established.

, QBn, QCn, QDn: the level of QA, QB, QC or QD respectively before the most recent transition of

the clock.

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Pin Arrangement

Clear

HD74HC195

Timing Diagram

Serial Inputs Shift/Load

Parallel Data Inputs

Outputs

Serial Inputs

Parallel Inputs

Clock Clear

Q QB

QC QD

Clear

Shift/Load

GND

A

(Top view)

A B C D

Clear Load

Serial Shift Serial Shift

H L

Clock

Shift/Load

Outputs

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HD74HC195

Logic Diagram

Shift/ Load

Clock

Clear

K J

CB A

D C CQ

LCL

D C CQ

LCL

D C CQ

LCL

D C CQ

LCL

QD QD QC QB QA

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HD74HC195

DC Characteristics

Ta = –40 to

Ta = 25°C

Item Symbol V

Input voltage V

(V) Min Typ Max Min Max Unit Test Conditions

2.0 1.5 — — 1.5 — V

4.5 3.15 — — 3.15 —

6.0 4.2 — — 4.2 —

2.0 — — 0.5 — 0.5 V

4.5 — — 1.35 — 1.35

6.0 — — 1.8 — 1.8

Output voltage V

2.0 1.9 2.0 — 1.9 — V Vin = VIH or VILIOH = –20 µA

4.5 4.4 4.5 — 4.4 —

6.0 5.9 6.0 — 5.9 —

4.5 4.18 — — 4.13 — IOH = –4 mA

6.0 5.68 — — 5.63 — IOH = –5.2 mA

2.0 — 0.0 0.1 — 0.1 V Vin = VIH or VILIOL = 20 µA

4.5 — 0.0 0.1 — 0.1

6.0 — 0.0 0.1 — 0.1

4.5 — — 0.26 — 0.33 IOL = 4 mA

6.0 — — 0.26 — 0.33 IOL = 5.2 mA Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply

6.0 — — 4.0 — 40 µA Vin = VCC or GND, Iout = 0 µA current

+85°C

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HD74HC195

AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)

Ta = –40 to

Ta = 25°C

Item Symbol V

Maximum clock f

max

(V) Min Typ Max Min Max Unit Test Conditions

2.0 — — 6 — 5 MH frequency 4.5 — — 30 — 24

6.0 — — 35 — 28 Propagation delay t

PHL

2.0 — — 140 — 175 ns Clock to Q time 4.5 — 13 28 — 35

6.0 — — 24 — 30

PLH

2.0 — — 140 — 175 ns

4.5 — 13 28 — 35

6.0 — — 24 — 30

PHL

2.0 — — 150 — 190 ns Clear to Q

4.5 — 15 30 — 38

6.0 — — 26 — 33 Pulse width t

2.0 80 — — 100 — ns Clock to Clear

4.5 16 7 — 20 —

6.0 14 — — 17 — Setup time t

2.0 100 — — 125 — ns A, B, C, D, J, K to Clock

4.5 20 6 — 25 —

6.0 17 — — 21 —

2.0 100 — — 125 — ns Shift/Load to Clock

4.5 20 13 — 25 —

6.0 17 — — 21 — Hold time t

2.0 0 — — 0 — ns Any input except Shift/Load

4.5 0 –3 — 0 —

6.0 0 — — 0 — Removal time t

rem

2.0 75 — — 95 — ns Shift/Load to Clock

4.5 15 8 — 19 —

6.0 13 — — 16 —

2.0 25 — — 31 — ns Clear inactive to Clock

4.5 5 0 — 6 —

6.0 4 — — 5 —

+85°C

Page 7

AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont)

Ta = –40 to

Ta = 25°C

Item Symbol V

Output rise/fall t time t

TLH

THL

(V) Min Typ Max Min Max Unit Test Conditions

2.0 — — 75 — 95 ns

4.5 — 5 15 — 19

6.0 — — 13 — 16 Input capacitance Cin — — 5 10 — 10 pF

+85°C

HD74HC195

Page 8

19.20

20.00 Max

16 9

1.3

Unit: mm

6.30

7.40 Max

1.11 Max

2.54 ± 0.25

0.48 ± 0.10

5.06 Max

2.54 Min

0.51 Min

Hitachi Code JEDEC EIAJ Weight

7.62

+ 0.13

0.25

– 0.05

0° – 15°

(reference value)

DP-16 Conforms Conforms

1.07 g

Page 9

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

Hitachi, Ltd.

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