Datasheet HD74HC191, HD74HC190 Datasheet (HIT)

Page 1
HD74HC190/HD74HC191
Synchronous Up/Down Decade Counter (Single Clock Line)
Synchronous Up/Donw 4-bit Binary Counter (Single Clock Line)
Description
The HD74HC190 and HD74HC191 are synchronous, reverside up/down counters. The HD74HC190 is a 4-bit decade counter and the HD74HC191 is a 4-bit binary counter. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple clock) counters.
The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock input if the Enable G input is low. A high at Enable G inhibits counting. The direction of the count is determined by the level of the Down/ Up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down.
These counters feature a fully independent clock circuit. Changes at the control inputs (D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter will be dictated solely by the condition meeting the stable setup and hold times.
These counters are fully programmable; that is, the outputs may each be preset to either level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.
Two outputs have been made available to perform the cascading function. Ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately qual to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (9 or 15) counting up. The ripple clock output produces a low-level output pulse under those same conditions but only while the clock input is low. The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if paralle enabling is used. The maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.
Page 2
HD74HC190/HD74HC191
Features
• High Speed Operation: tpd (Clock to Q) = 22 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Pin Arrangement
Inputs
Outputs
Inputs
Outputs
Data B
QB
QA
Enable G
Down/Up
Q
QD
GND
1
2
3
4
5
6
C
7
8
B
QB
Q
A
G
Max/Min
Dn/Up
QC
D
Q
D
(Top view)
A
CK
Ripple Clock
Load
C
16
15
14
13
12
11
10
9
V
CC
Data A
Clock Ripple
Clock Max/Min
Load
Data C
Data D
Inputs
Outputs
Inputs
2
Page 3
Timing Chart
HD74HC190
Illustrated below is the following sequence:
1. Load (preset) to BCD seven.
2. Count up to eight, nine (maximum), zero, one and two.
3. Inhibit
4. Count down to one, zero (minimum), nine, eight and seven.
Load
A B
C D
Clock
Down/Up Enable G
HD74HC190/HD74HC191
Q QB QC QD
Max/Min
Ripple
Clock
A
7
89 012 2210987
Count Up Inhibit Count Down
Load
3
Page 4
HD74HC190/HD74HC191
HD74HC191
Illustrated below is the following sequence:
1. Load (preset) to binary thirteen.
2. Count up to fourteen, fifteen (maximum), zero, one and two.
3. Inhibit
4. Count down to one, zero (minimum), fifteen, fourteen and thirteen.
Load
A
B
Data
Inputs
Clock
Down/Up Enable G
Q QB QC QD
Max/Min
Ripple
Clock
C D
A
13
14 15 0 1 2 2 1 0 15 14 13
Count Up Inhibit Count Down
Load
4
Page 5
Logic Diagram
HD74HC190
HD74HC190/HD74HC191
Clock
Down/Up
Input A
Enable G
Input B
Input C
Input D
Load
CK PAQ
CK
INCL
CK P
B
CK
INCL
CK P
C
CK
INCL
CK P
D
CK
INCL
Ripple Clock
Max/Min Output
QA
Q
Q
Q
Q
Q
Q
Q
QB
QC
QD
5
Page 6
HD74HC190/HD74HC191
HD74HC191
Clock
Down/Up
Input A
Enable G
Input B
Input C
Input D
Load
CK PAQ
CK
INCL
CK P
B
CK
INCL
CK P
C
CK
INCL
CK P
D
CK
INCL
Ripple Clock
Max/Min Output
QA
Q
Q
Q
Q
Q
Q
Q
QB
QC
QD
6
Page 7
HD74HC190/HD74HC191
DC Characteristics
Ta = –40 to
Ta = 25°C
Item Symbol V
Input voltage V
IH
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 1.5 — — 1.5 — V
4.5 3.15 — — 3.15 —
6.0 4.2 — — 4.2 —
V
IL
2.0 — — 0.5 — 0.5 V
4.5 — — 1.35 — 1.35
6.0 — — 1.8 — 1.8
Output voltage V
OH
2.0 1.9 2.0 — 1.9 — V Vin = VIH or VILIOH = –20 µA
4.5 4.4 4.5 — 4.4 —
6.0 5.9 6.0 — 5.9 —
4.5 4.18 — — 4.13 — IOH = –4 mA
6.0 5.68 — — 5.63 — IOH = –5.2 mA
V
OL
2.0 — 0.0 0.1 — 0.1 V Vin = VIH or VILIOL = 20 µA
4.5 — 0.0 0.1 — 0.1
6.0 — 0.0 0.1 — 0.1
4.5 — — 0.26 — 0.33 IOL = 4 mA
6.0 — — 0.26 — 0.33 IOL = 5.2 mA Input current Iin 6.0 — — ±0.1 — ±1.0 µA Vin = VCC or GND Quiescent supply
I
CC
6.0 — — 4.0 — 40 µA Vin = VCC or GND, Iout = 0 µA current
+85°C
7
Page 8
HD74HC190/HD74HC191
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = –40 to
Ta = 25°C
Item Symbol V
Maximum clock f
max
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 — — 5 — 4 MHz frequency 4.5 — — 25 — 20
6.0 — — 29 — 24 Propagation delay t time t
PLH
PHL
2.0 — — 265 — 335 ns Load to Q
4.5 — 21 53 — 66
6.0 — — 45 — 56
2.0 — — 230 — 290 Data to Q
4.5 — 18 46 — 58
6.0 — — 39 — 49
2.0 — — 120 — 150 Clock to RC
4.5 — 14 24 — 30
6.0 — — 20 — 26
2.0 — — 190 — 240 Clock to Q
4.5 — 22 38 — 48
6.0 — — 32 — 41
2.0 — — 250 — 315 Clock to max/min
4.5 — 26 50 — 63
6.0 — — 43 — 54
2.0 — — 230 — 290 Down/up to RC
4.5 — 20 46 — 58
6.0 — — 39 — 49
2.0 — — 130 — 165 G to RC
4.5 — 14 26 — 33
6.0 — — 22 — 28
2.0 — — 190 — 240 Down/up to max/min
4.5 — 17 38 — 48
6.0 — — 32 — 41 Pulse width t
w
2.0 80 — — 100 — ns
4.5 16 8 — 20 —
6.0 14 – — 17 — Hold time t
h
2.0 0 — — 0 — ns
4.5 0 –6 — 0 —
6.0 0 — — 0 —
+85°C
8
Page 9
HD74HC190/HD74HC191
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns) (cont)
Ta = –40 to
Ta = 25°C
Item Symbol V
Setup time t
su
(V) Min Typ Max Min Max Unit Test Conditions
CC
2.0 100 — — 125 — ns
4.5 20 7 — 25 —
6.0 17 — — 21 — Output rise/fall t time t
TLH
THL
2.0 — — 75 — 95 ns
4.5 — 5 15 — 19
6.0 — — 13 — 16 Input capacitance Cin — — 5 10 — 10 pF
+85°C
9
Page 10
19.20
20.00 Max
16 9
1.3
Unit: mm
6.30
7.40 Max
81
1.11 Max
2.54 ± 0.25
0.48 ± 0.10
5.06 Max
2.54 Min
0.51 Min
Hitachi Code JEDEC EIAJ Weight
7.62
+ 0.13
0.25
– 0.05
0° – 15°
(reference value)
DP-16 Conforms Conforms
1.07 g
Page 11
16
Unit: mm
10.06
10.5 Max 9
5.5
1
0.80 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.12
0.10 ± 0.10
0.15
M
2.20 Max
7.80
0.20 ± 0.04
*0.22 ± 0.05
0.70 ± 0.20
Hitachi Code JEDEC EIAJ
(reference value)
Weight
+ 0.20 – 0.30
1.15
0° – 8°
FP-16DA — Conforms
0.24 g
Page 12
16
Unit: mm
9.9
10.3 Max 9
1
1.27
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.25
+ 0.11
– 0.04
0.14
0.15
3.95
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
0.60
Hitachi Code JEDEC EIAJ Weight
+ 0.10 – 0.30
0° – 8°
+ 0.67 – 0.20
(reference value)
FP-16DN Conforms Conforms
0.15 g
Page 13
Cautions
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