
HD74BC373A
Octal D Type Transparent Latches With 3 State Outputs
ADE-205-009A(Z)
Rev. 1
March 1993
Description
The HD74BC373A provides high drivability and operation equal to or better than high speed bipolar
standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5
of high speed bipolar logic IC, when the frequency is 10 MHz. The device has eight D type latches with
three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the
D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch
enable returns high again. When a high logic level is applied to the output control input, all outputs go to a
high impedance state, regardless of what signals are present at the other inputs and the state of the storage
elements.
Features
• Input/Output are at high impedance state when power supply is off.
• Built in input pull up circuit can make input pins be open, when not used.
• TTL level input
• Wide operating temperature range input pins
Ta = –40 to + 85°C
Function Table
Inputs
G LE D Output Q
HX X Z
LH L L
LH H H
L L X No change
H : High level
L : Low level
X : Immaterial
Z : High impedance

HD74BC373A
Pin Arrangement
G
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
10
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
CC
(Top view)
Absolute Maximum Ratings
Item Symbol Rating Unit
Supply voltage V
Input diode current I
Input voltage V
Output voltage V
Off state output voltage V
CC
IK
IN
OUT
OUT(off)
Storage temperature Tstg –65 to +150 °C
Note: 1. The absolute maximum ratings are values which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
–0.5 to +7.0 V
±30 mA
–0.5 to +7.5 V
–0.5 to +7.5 V
–0.5 to +5.5 V
2

HD74BC373A
Recommended Operating Conditions
Item Symbol Min Typ Max Unit
Supply voltage V
Input voltage V
Output voltage V
CC
IN
OUT
Operating temperature Topr –40 — 85 °C
Input rise/fall time*
1
tr, t
f
Note: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Logic Diagram
G
4.5 5.0 5.5 V
0—VCCV
0—VCCV
0 — 8 ns/V
1D
2D
7D
8D
LE
D Q
D Q
D Q
D Q
1Q
2Q
7Q
8Q
3

HD74BC373A
Electrical Characteristics (Ta = –40°C to +85°C)
Item Symbol VCC(V) Min Max Unit Test Conditions
Input voltage V
Output voltage V
IH
V
IL
OH
4.5 2.4 — V IOH = –3 mA
4.5 2.0 — V IOH = –15 mA
V
OL
4.5 — 0.4 V IOL = 24 mA
4.5 — 0.5 V IOL = 48 mA
Input diode voltage V
Input current I
IK
I
4.5 — –1.2 V IIN = –18 mA
5.5 — –250 µAV
5.5 — 1.0 µAV
5.5 — 100 µAV
Short circuit output current*1I
Off state output current I
Supply current I
OS
OZH
I
OZL
CCL
I
CCH
I
CCZ
2
I
*
CCT
5.5 –100 –225 mA VIN = 0 or 5.5 V
5.5 — 50 µAV
5.5 — –50 µAV
5.5 — 29.5 mA VIN = 0 or 5.5 V
5.5 — 2.5 mA VIN = 0 or 5.5 V
5.5 — 2.5 mA VIN = 0 or 5.5 V
5.5 — 1.5 mA VIN = 3.4 or 0.5 V
Notes : 1. Not more than one output should be shorted at a time and duration of the short circuit should not
exceed one second.
2. When input by the TTL level, it shows I
2.0 — V
— 0.8 V
increase at per one input pin.
CC
= 0 V
IN
= 5.5 V
IN
= 7.0 V
IN
= 2.7 V
O
= 0.5 V
O
All outputs is “L”
All outputs is “H”
All outputs is “Z”
4

Switching Test Method (CL = 50 pF)
HD74BC373A
Ta = 25°C
V
= 5.0 V
CC
Ta = –40 to 85°C
VCC = 5.0 V ±10%
Item Symbol Min Max Min Max Unit Test Conditions
Propagation D → Qt
delay time t
LE → Qt
Output enable time t
Output disable time t
PLH
PHL
PLH
t
PHL
ZH
t
ZL
HZ
t
LZ
3.0 8.0 3.0 10.0 ns See under figure
3.0 8.0 3.0 10.0
3.0 8.0 3.0 10.0 ns
3.0 8.0 3.0 10.0
3.0 9.0 3.0 11.0 ns
3.0 9.0 3.0 11.0
3.0 8.0 3.0 10.0 ns
3.0 8.0 3.0 10.0
Setup time tS(H) 2.0 — 2.0 — ns
tS(L) 2.0 — 2.0 —
Hold time th(H) 2.0 — 2.0 — ns
th(L) 2.0 — 2.0 —
Pulse width t
Input capacitanse C
Output capacitance C
w
IN
O
6.0 — 6.0 — ns
3.0(Typ) — pF VIN = VCC or GND
15.0(Typ) — pF VO = VCC or GND
Test Circuit
V
CC
Input
Pulse Generator
Z
out
Pulse Generator
Z
out
= 50
= 50
Ω
Ω
Input
See Function Table
Notes: 1. CL includes probe and jig capacitance.
2. Open: t
7 V: tZL, t
PLH
, t
PHL
LZ
, tZH, tHZ, th, tSU, t
V
G
1D to 8D
LE
w
CC
1Q to 8Q
Output
C =
L
50 pF
50 ScopeΩ
500 Ω
450 Ω
*2
OPEN
7V
5

Waveforms-3
HD74BC373A
t
r
Input
LE
Input
10% 10%
1.5 V
D
Notes: 1. tr = 2.5 ns, tf = 2.5 ns
2. Input waveform: PRR =1 MHz, duty cycle 50%
Waveforms-4
t
f
Input G
1.5 V
10%
90% 90%
1.5 V
t
t
ZL
t
f
3 V
1.5 V
w
t
s
t
h
0 V
3 V
1.5 V
0 V
t
r
90%90%
3 V
1.5 V
10%
t
LZ
0 V
3.5 V
Waveform–A
Waveform–B
Notes: 1. tr = 2.5 ns, tf = 2.5 ns
2. Input waveform: PRR = 1 MHz, duty cycle 50%
3. Waveform-A shows input conditions such that the output is “L” level when enable by the
output control.
4. Waveform-B shows input conditions such that the output is “H” level when enable by the
output control.
1.5 V
V
+ 0.3 V
OL
t
ZH
t
HZ
V
– 0.3 V
OH
V
OL
V
OH
1.5 V
0 V
7

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