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HD74ALVCH162821
3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs
ADE-205-186A (Z)
2nd. Edition
September 1997
Description
The HD74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are
edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides
true data at the Q outputs. A buffered output enable (OE) input can be used to place the ten outputs in
either a normal logic state (high or low level) or a high impedance state. In the high impedance state, the
outputs neither load nor drive the bus lines significantly. The high impedance state and increased drive
provide the capability to drive bus line without need for interface or pullup components. The output enable
(OE) input does not affect the internal operations of the flip flops. Old data can be retained or new data can
be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold
unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA,
include 26 Ω resistors to reduce overshoot and undershoot.
Features
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
• All outputs have equivalent 26 Ω series resistors, so no external resistors are required.
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HD74ALVCH162821
Function Table
Inputs Output Q
OE CLK D
L ↑ HH
L↑ LL
L H or L X Q
HXXZ
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑ : Low to high transition
Note: 1. Output level before the indicated steady state input conditions were established.
*1
0
2
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Pin Arrangement
HD74ALVCH162821
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2Q10
2OE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1CLK
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2D10
2CLK
(Top view)
3
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HD74ALVCH162821
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
V
CC
Input voltage
Output voltage
Input clamp current I
Output clamp current I
Continuous output current I
VCC, GND current / pin ICC or I
Maximum power dissipation
at Ta = 55°C (in still air)
*1
*1, 2
*3
V
I
V
O
IK
OK
O
GND
P
T
Storage temperature Tstg –65 to 150 °C
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
–0.5 to 4.6 V
–0.5 to 4.6 V
–0.5 to VCC +0.5 V
–50 mA VI < 0
±50 mA VO < 0 or VO > V
±50 mA VO = 0 to V
CC
±100 mA
1 W TSSOP
CC
Recommended Operating Conditions
Item Symbol Min Max Unit Conditions
Supply voltage V
Input voltage V
Output voltage V
High level output current I
Low level output current I
CC
I
O
OH
OL
Input transition rise or fall rate ∆t / ∆v 0 10 ns / V
Operating temperature Ta –40 85 °C
Note: Unused control inputs must be held high or low to prevent them from floating.
2.3 3.6 V
0VCCV
0VCCV
—–6mAV
—–8 V
= 2.3 V
CC
= 2.7 V
CC
— –12 VCC = 3.0 V
— 6 mA VCC = 2.3 V
—8 V
—12 V
= 2.7 V
CC
= 3.0 V
CC
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Logic Diagram
1OE
1CLK
1D1
1
56
55
1 of 10
Channels
C1
1D
To nine other channels
HD74ALVCH162821
2
1Q1
2OE
2CLK
2D1
28
29
42
1 of 10
Channels
C1
1D
To nine other channels
15
2Q1
5
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HD74ALVCH162821
Electrical Characteristics (Ta = –40 to 85°C)
Item Symbol V
Input voltage V
IH
(V) *1Min Max Unit Test Conditions
CC
2.3 to 2.7 1.7 — V
2.7 to 3.6 2.0 —
V
IL
2.3 to 2.7 — 0.7
2.7 to 3.6 — 0.8
Output voltage V
OH
Min to Max VCC–0.2 — V IOH = –100 µA
2.3 1.9 — IOH = –4 mA, VIH = 1.7 V
2.3 1.7 — IOH = –6 mA, VIH = 1.7 V
3.0 2.4 — IOH = –6 mA, VIH = 2.0 V
2.7 2.0 — IOH = –8 mA, VIH = 2.0 V
3.0 2.0 — IOH = –12 mA, VIH = 2.0 V
V
OL
Min to Max — 0.2 IOL = 100 µA
2.3 — 0.4 IOL = 4 mA, VIL = 0.7 V
2.3 — 0.55 IOL = 6 mA, VIL = 0.7 V
3.0 — 0.55 IOL = 6 mA, VIL = 0.8 V
2.7 — 0.6 IOL = 8 mA, VIL = 0.8 V
3.0 — 0.8 IOL = 12 mA, VIL = 0.8 V
Input current I
IN
I
IN (hold)
3.6 — ±5 µAVIN = VCC or GND
2.3 45 — VIN = 0.7 V
2.3 –45 — VIN = 1.7 V
3.0 75 — VIN = 0.8 V
3.0 –75 — VIN = 2.0 V
3.6 — ±500 VIN = 0 to 3.6 V
Off state output current *2I
Quiescent supply current I
OZ
CC
∆I
3.6 — ±10 µAV
= VCC or GND
OUT
3.6 — 40 µAVIN = VCC or GND
3.0 to 3.6 — 750 µAVIN = one input at (VCC–0.6)
CC
V,
other inputs at V
or GND
CC
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating
conditions.
2. For I/O ports, the parameter I
includes the input leakage current.
OZ
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HD74ALVCH162821
Switching Characteristics (Ta = –40 to 85°C)
Item Symbol VCC (V) Min Typ Max Unit FROM
(Input)TO(Output)
Maximum clock frequency f
Propagation delay time t
Output enable time t
Output disable time t
Setup time t
Hold time t
Pulse width t
Input capacitance C
Output capacitance C
max
PLH
t
PHL
ZH
t
ZL
HZ
t
LZ
su
h
w
IN
O
2.5±0.2 150 — — MHz
2.7 150 — —
3.3±0.3 150 — —
2.5±0.2 1.0 — 6.9 ns CLK Q
2.7 — — 6.0
3.3±0.3 1.0 — 5.1
2.5±0.2 1.0 — 7.6 ns OE Q
2.7 — — 6.9
3.3±0.3 1.0 — 5.7
2.5±0.2 1.4 — 6.4 ns OE Q
2.7 — — 5.5
3.3±0.3 1.0 — 5.1
2.5±0.2 4.4 — — ns
2.7 3.9 — —
3.3±0.3 3.4 — —
2.5±0.2 0 — — ns
2.7 0 — —
3.3±0.3 0 — —
2.5±0.2 3.3 — — ns
2.7 3.3 — —
3.3±0.3 3.3 — —
3.3 — 3.5 — pF Control inputs
3.3 — 6.0 — Data inputs
3.3 — 7.0 — pF
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HD74ALVCH162821
• Test Circuit
500 Ω
See under table
S1
OPEN
*1
L
500 ΩC = 50 pF
GND
Load Circuit for Outputs
Symbol
t / t
PLH PHL
t / t / t
su h w
t / t
ZH HZ
t / t
ZL LZ
Note: 1. C includes probe and jig capacitance.
L
Vcc=2.5±0.2V
OPEN
GND
4.6 V 6.0 V
Vcc=2.7V,
3.3±0.3V
OPEN
GND
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HD74ALVCH162821
• Waveforms – 1
Input
Output
• Waveforms – 2
Timing Input
Data Input
Input
10 %
90 %
tf
V
IH
V
ref
10 %
t
PHL
V
ref
GND
V
OH
V
OL
tr
90 %
V
ref
t
PLH
V
ref
tr
V
90 %
V
ref
10 %
t
su
V
ref
t
h
V
ref
IH
GND
V
IH
GND
t
w
V
IH
V
ref
V
ref
GND
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HD74ALVCH162821
• Waveforms – 3
trtf
Output
Control
Waveform - A
Waveform - B
90 %
V
ref
10 % 10 %
t
ZL
V
ref
t
ZH
V
ref
Notes: 1. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
V
90 %
ref
t
t
HZ
LZ
TEST
V
IH
V
ref
V
OH1
V
OL1
V + 0.3 V
OL
V – 0.3 V
OH
Vcc=2.5±0.2V
2.3 V 2.7 V
1.2 V 1.5 V
2.3 V 3.0 V
GND
V
GND
≈V
V
V
≈V
Vcc=2.7V,
3.3±0.3V
GND
IH
OH1
OL
OH
OL1
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Package Dimensions
14.00
+0.3
–0.1
HD74ALVCH162821
Unit : mm
2956
+0.3
–0.1
6.10
128
+0.1
0.20
–0.05
0.50
0.08
M
0.40 Max
0.10
0.05 Min
1.20 max
8.10 ± 0.3
0.15 ± 0.05
JEDEC code
Hitachi code
EIAJ code
10° Max
0.50 ± 0.1
TTP-56D
—
—
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Cautions
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copyright, trademark, or other intellectual property rights for information contained in this document.
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intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
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products.
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