Datasheet HD74ALVCH16269 Datasheet (HIT)

HD74ALVCH16269

12-bit to 24-bit Registered Bus Transceivers

with 3-state Outputs

ADE-205-136 (Z)

Preliminary 1st. Edition

May 1996

Description

The HD74ALVCH16269 is used in applications where two separate ports must be multiplexed onto, or
demultiplexed from, a single port. The device is particularly suitable as an interface between
synchronous DRAMs and high speed microprocessors. Data is stored in the internal B port registers on
the low to high transition of the clock (CLK) input when the appropriate clock enable (CLKENA)
inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a
24-bit word on the B port. For data transfer in the B to A direction, a single storage register is
provided. The select ( SEL) line selects 1B or 2B data for the A outputs. The register on the A output
permits the fastest possible data transfer, thus extending the period that the data is valid on the bus.
The control terminals are registered so that all transactions are synchronous with CLK. Data flow is
controlled by the active low output enables (OEA, OEB1, OEB2). Active bus hold circuitry is
provided to hold unused or floating data inputs at a valid logic level.

Features

• VCC = 2.3 V to 3.6 V

• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)

• High output current ±24 mA (@VCC = 3.0 V)

• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

HD74ALVCH16269

Function Table

Inputs Outputs
CLK OEA OEB A 1B, 2B

↑ HHZ Z
↑ H L Z Active
↑ L H Active Z
↑ L L Active Active

Output enable

Inputs Outputs
CLKENA1 CLKENA2 CLK A 1B 2B

HHXX1B

*1

0

LX↑LL X
LX↑HH X
XL↑LX L
XL↑HX H

A-to-B storage (OEB = L)

2B0

*1

Inputs Output A
CLK SEL 1B 2B

XHXX A
XLXX A

*1

0

*1

0

↑ HLX L
↑ HHX H
↑ LXL L
↑LXH H

B-to-A storage (OEA = L)

H : High level
L : Low level
X : Immaterial
Z : High impedance
↑ : Low to high transition
Note: 1. Output level before the indicated steady state input conditions were established.

Pin Arrangement

HD74ALVCH16269

OEA

OEB1

2B3

GND

2B2
2B1

V

CC

A1
A2

A3

GND

A4
A5

A6
A7

A8
A9

GND

A10
A11
A12
V

CC

1B1
1B2

GND

1B3

NC

SEL

10
11

12
13
14

15
16

17
18

19

20
21
22
23
24
25
26
27
28

OEB2

1
2

3
4
5

6
7

8

9

56

CLKENA2

55
54

2B4

53

GND
2B5

52
51

2B6

50

V

2B7

49

2B8

48
47

2B9

46

GND
2B10

45

2B11

44
43

2B12

42

1B12
1B11

41

1B10

40

GND

39
38

1B9
1B8

37

1B7

36
35

V

34

1B6

33

1B5

32

GND

31

1B4

30

CLKENA1

29

CLK

CC

CC

(Top view)

HD74ALVCH16269

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage V
Input voltage

Output voltage

*1, 2

*1, 2

Input clamp current I
Output clamp current I
Continuous output current I

Maximum power dissipation
at Ta = 55°C (in still air)

*3

CC

V

I

V

O

IK

OK

O

P

T

Storage temperature Tstg –65 to 150 °C
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent

damage to the device. These are stress ratings only, and functional operation of the device
at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute maximum rated conditions for extended
periods may affect device reliability.

1. The input and output negative voltage ratings may be exceeded if the input and output
clamp current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of
150°C and a board trace length of 750 mils.

–0.5 to 4.6 V
–0.5 to 4.6 V Except I/O ports
–0.5 to VCC +0.5 I/O ports
–0.5 to VCC +0.5 V
–50 mA VI < 0

±50 mA VO < 0 or VO > V
±50 mA VO = 0 to V

CC

±100
1 W TSSOP

CC

Recommended Operating Conditions

Item Symbol Min Max Unit Conditions

Supply voltage V
Input voltage V
Output voltage V
High level output current I

Low level output current I

CC

I

O

OH

OL

Input transition rise or fall rate ∆t / ∆v 0 10 ns / V
Operating temperature Ta –40 85 °C

Note: Unused control inputs must be held high or low to prevent them from floating.

2.3 3.6 V
0VCCV
0VCCV
— –12 mA VCC = 2.3 V
— –12 VCC = 2.7 V
— –24 VCC = 3.0 V
—12mAV
—12 V
—24 V

= 2.3 V

CC

= 2.7 V

CC

= 3.0 V

CC

Logic Diagram

HD74ALVCH16269

CLK

OEB1

OEB2

CLKENA1

CLKENA2

SEL

OEA

A1

29

2

56

30

55

28

1

1D

C1

8

C1

1D

C1

1D

CE

C1

1D

CE

C1

1D

1 of 12 Channels

G1

C1

1D

C1

1D

23

1

1

1B1

6

2B1

HD74ALVCH16269

Electrical Characteristics (Ta = –40 to 85°C)

Item Symbol V

Input voltage V

IH

(V) *1Min Max Unit Test Conditions

CC

2.3 to 2.7 1.7 — V

2.7 to 3.6 2.0 —

V

2.3 to 2.7 — 0.7

IL

2.7 to 3.6 — 0.8

Output voltage V

Min to Max VCC–0.2 — V IOH = –100 µA

OH

2.3 2.0 — IOH = –6 mA, VIH = 1.7 V

2.3 1.7 — IOH = –12 mA, VIH = 1.7 V

2.7 2.2 — IOH = –12 mA, VIH = 2.0 V

3.0 2.4 — IOH = –12 mA, VIH = 2.0 V

3.0 2.0 — IOH = –24 mA, VIH = 2.0 V

V

Min to Max — 0.2 IOL = 100 µA

OL

2.3 — 0.4 IOL = 6 mA, VIL = 0.7 V

2.3 — 0.7 IOL = 12 mA, VIL = 0.7 V

2.7 — 0.4 IOL = 12 mA, VIL = 0.8 V

3.0 — 0.55 IOL = 24 mA, VIL = 0.8 V

Input current I

IN

I

IN (hold)

3.6 — ±5 µAVIN = VCC or GND

2.3 45 — VIN = 0.7 V

2.3 –45 — VIN = 1.7 V

3.0 75 — VIN = 0.8 V

3.0 –75 — VIN = 2.0 V

3.6 — ±500 VIN = 0 to 3.6 V
Off state output current *2I
Quiescent supply current I

OZ

CC

∆I

3.6 — ±10 µAV

= VCC or GND

OUT

3.6 — 40 µAVIN = VCC or GND

3.0 to 3.6 — 750 µAVIN = one input at (VCC–0.6)

CC

V,
other inputs at V

or GND

CC

Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended

operating conditions.

2. For I/O ports, the parameter I

includes the input leakage current.

OZ

HD74ALVCH16269

Switching Characteristics (Ta = –40 to 85°C)

Item Symbol VCC (V) Min Typ Max Unit FROM

(Input)TO(Output)

Maximum clock frequency f

Propagation delay time t

Output enable time t

Output disable time t

Input capacitance C
Output capacitance C

max

PLH

t

PHL

ZH

t

ZL

HZ

t

LZ

IN

IN / O

2.5±0.2 135 — — MHz

2.7 135 — —

3.3±0.3 135 — —

2.5±0.2 1.0 — 8.8 ns CLK B

2.7 — — 7.3

3.3±0.3 1.0 — 6.2

2.5±0.2 1.0 — 7.0 A

2.7 — — 5.8

3.3±0.3 1.0 — 5.0

2.5±0.2 1.0 — 8.4 ns CLK B

2.7 — — 6.7

3.3±0.3 1.0 — 6.1

2.5±0.2 1.0 — 8.1 A

2.7 — — 6.2

3.3±0.3 1.0 — 5.9

2.5±0.2 1.4 — 8.3 ns CLK B

2.7 — — 6.9

3.3±0.3 1.0 — 6.1

2.5±0.2 1.5 — 7.7 A

2.7 — — 6.8

3.3±0.3 1.0 — 5.6

3.3 — 3.5 — pF Control inputs

3.3 — 9.0 — pF A or B ports

HD74ALVCH16269

Item Symbol VCC (V) Min Typ Max Unit FROM (Input)

Setup time t

Hold time t

Pulse width t

su

h

w

2.5±0.2 2.0 — — ns A data before CLK↑

2.7 2.0 — —

3.3±0.3 1.7 — —

2.5±0.2 2.2 — — B data before CLK↑

2.7 2.1 — —

3.3±0.3 1.8 — —

2.5±0.2 1.6 — — SEL before CLK↑

2.7 1.6 — —

3.3±0.3 1.3 — —

2.5±0.2 1.0 — — CLKENA1 or

2.7 1.2 — — CLKENA2 before
CLK↑

3.3±0.3 0.9 — —

2.5±0.2 1.5 — — OE before CLK↑

2.7 1.6 — —

3.3±0.3 1.3 — —

2.5±0.2 0.7 — — ns A data after CLK↑

2.7 0.6 — —

3.3±0.3 0.6 — —

2.5±0.2 0.7 — — B data after CLK↑

2.7 0.6 — —

3.3±0.3 0.6 — —

2.5±0.2 1.1 — — SEL aftrer CLK↑

2.7 0.7 — —

3.3±0.3 0.7 — —

2.5±0.2 1.0 — — CLKENA1 or

2.7 0.8 — — CLKENA2 after CLK↑

3.3±0.3 1.1 — —

2.5±0.2 0.8 — — OE after CLK↑

2.7 0.8 — —

3.3±0.3 0.8 — —

2.5±0.2 3.3 — — ns CLK “H” or “L”

2.7 3.3 — —

3.3±0.3 3.3 — —

• Test Circuit

500 Ω

HD74ALVCH16269

See under table

S1

OPEN

*1

L

500 ΩC = 50 pF

GND

Load Circuit for Outputs

Symbol

t / t

PLH PHL

t / t / t

su h w

t / t

ZH HZ

t / t

ZL LZ

Note: 1. C includes probe and jig capacitance.

L

Vcc=2.5±0.2V

OPEN

GND

4.6 V 6.0 V

Vcc=2.7V,

3.3±0.3V

OPEN

GND

HD74ALVCH16269

• Waveforms – 1

Input

Output

• Waveforms – 2

Timing Input

Data Input

Input

10 %

tr

V

90 %

ref

t

PLH

90 %

V

ref

tf

V

IH

V

ref

10 %

t

PHL

V

ref

GND

V

OH

V

OL

tr

V

90 %

V

ref

10 %

t

su

V

ref

t

h

V

ref

IH

GND

V

IH

GND

t

w

V

IH

V

ref

V

ref

GND

HD74ALVCH16269

• Waveforms – 3

trtf

Output
Control

Waveform - A

Waveform - B

90 %

V

ref

10 % 10 %

t

ZL

V

ref

t

ZH

V

ref

Notes: 1. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.

3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.

4. The output are measured one at a time with one transition per measurement.

V

90 %

ref

t

t

HZ

LZ

TEST

V

IH

V

ref

V

OH1

V

OL1

V + 0.3 V

OL

V – 0.3 V

OH

Vcc=2.5±0.2V

2.3 V 2.7 V

1.2 V 1.5 V

2.3 V 3.0 V
GND

V

GND

≈V

V
V

≈V

Vcc=2.7V,

3.3±0.3V

GND

IH

OH1

OL

OH

OL1

HD74ALVCH16269

Package Dimensions

14.00

56

128

+0.1

0.20

–0.05

+0.3
–0.1

0.50

0.08

M

29

+0.3

–0.1

6.10

Unit : mm

0.40 Max

0.10

0.05 ± 0.05

1.2 Max

8.10 ± 0.3

0.15 ± 0.05

Hitachi code

JEDEC code

0.50 ± 0.1

EIAJ code

10° Max

TTP-56D

—
—

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