Datasheet HD74ACT112, HD74AC112 Datasheet (HIT)

HD74AC112/HD74ACT112

Dual JK Negative Edge-Triggered Flip-Flop

Description

The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to
each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level
of the J and K inputs may change when the clock is High and the bistable will perform according to the
Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs
on the falling edge of the clock pulse.

Features

• Outputs Source/Sink 24 mA

• HD74ACT112 has TTL-Compatible Inputs

Pin Arrangement

CP

K

J

S

D1

Q

Q

Q

GND

1

1

2

1

3

1

4

5

1

6

1

7

2

8

(Top view)

16

15

14

13

12

11

10

V

CC

C

D1

C

D2

CP

2

K

2

J

2

S

D2

9

Q

2

HD74AC112/HD74ACT112

Logic Symbol

410

S

3

1

2

D1

J

1

CP

K

Q

1

Q

1

C

D1

15 14

1

1

V

CC

5

13

6

= Pin16

GND = Pin8

Pin Names

J1, J2, K1, K

CP1, CP
CD1, C
SD1, S

2

D2

D2

Q1, Q2, Q1, Q 2Outputs

Asynchronous Inputs:

Low input to SD sets Q to High level
Low input to CD sets Q to Low level
Clear and Set are independent of clock
Simultaneous Low on CD and SD makes both Q and Q High

Data Inputs

2

Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active Low)
Direct Set Inputs (Active Low)

11

12

J

2

CP

K

S

D2

Q

2

Q

2

C

D2

9

2

7

2

2

HD74AC112/HD74ACT112

Truth Table

Inputs Outputs
@t

n

JK Q

LL Qn
LH L
HL H
HH Qn

t

: Bit time before clock pulse.

n

t

: Bit time after clock pulse.

n + 1

H : High Voltage Level
L : Low Voltage Level

Logic Diagram

S

D

C

D

J

CP

#CP

@t

n + 1

Q

Q

K

#

CP

CP

CP

#

CP

CP

CP

CP

#

#

CP

CP

DC Characteristics (unless otherwise specified)

Item Symbol Max Unit Condition

Maximum quiescent supply current I

Maximum quiescent supply current I

Maximum additional ICC/input
(HD74ACT112)

CC

CC

I

CCT

80 µAV

8.0 µAV

1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V

= VCC or ground, VCC = 5.5 V,

IN

Ta = Worst case

= VCC or ground, VCC = 5.5 V,

IN

Ta = 25°C

Ta = Worst case

3

HD74AC112/HD74ACT112

AC Characteristics: HD74AC112

Item Symbol V

Maximum clock f

max

Ta = +25°C
C

= 50 pF

L

(V)*1Min Typ Max Min Max Unit

CC

3.3 125 — — 100 — MHz

Ta = –40°C to +85°C
CL = 50 pF

frequency 5.0 150 — — 125 —
Propagation delay t

C

to Q or Q 5.0 1.0 8.5 11.0 1.0 12.0

P

Propagation delay t

C

to Q or Q 5.0 1.0 8.5 11.0 1.0 12.0

P

Propagation delay t

C

, SD to Q or Q 5.0 1.0 7.0 9.5 1.0 10.5

D

Propagation delay t

C

, SD to Q or Q 5.0 1.0 9.0 11.0 1.0 12.5

D

PLH

PHL

PLH

PHL

3.3 1.0 11.0 14.0 1.0 15.0 ns

3.3 1.0 11.0 14.0 1.0 15.0

3.3 1.0 9.5 12.5 1.0 13.5

3.3 1.0 11.5 14.5 1.0 15.5

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements: HD74AC112

Ta = –40°C

Ta = +25°C
C

= 50 pF

L

Item Symbol V

Setup time t
J or K to C

P

Hold time t

C

to J or K 5.0 –0.5 0.0 0.0

P

Pulse width t

C

or CD or S

P

D

Recovery time t

C

or SD to C

D

P

su

h

w

rec

(V)*1Typ Guaranteed Minimum Unit

CC

3.3 3.0 5.5 6.0 ns

5.0 2.0 4.5 4.6

3.3 –1.5 0.0 0.0

3.3 2.0 5.5 7.0

5.0 2.0 4.5 5.0

3.3 –1.0 3.5 3.5

5.0 –1.0 3.0 3.0

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

to +85°C
CL = 50 pF

4

AC Characteristics: HD74ACT112

HD74AC112/HD74ACT112

Ta = +25°C
C

= 50 pF

L

Item Symbol V

Maximum clock

f

max

(V)*1Min Typ Max Min Max Unit

CC

5.0 100 — — 80 — MHz

frequency
Propagation delay

C

to Q or Q

P

Propagation delay

C

to Q or Q

P

Propagation delay

C

, SD to Q or Q

D

Propagation delay

C

, SD to Q or Q

D

t

PLH

t

PHL

t

PLH

t

PHL

5.0 1.0 10.5 13.0 1.0 14.0 ns

5.0 1.0 10.5 13.0 1.0 14.0

5.0 1.0 8.0 10.0 1.0 11.0

5.0 1.0 10.5 12.5 1.0 13.5

Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements: HD74ACT112

Ta = +25°C
C

L

Item Symbol V

Setup time
J or K to C

P

Hold time

C

to J or K

P

Pulse width

C

or CD or S

P

Recovery time

C

, SD to C

D

P

D

t

su

t

h

t

w

t

rec

Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V

(V)*1Typ Guaranteed Minimum Unit

CC

5.0 2.5 7.0 8.0 ns

5.0 0.0 1.5 1.5

5.0 4.5 7.0 8.0

5.0 –2.5 3.0 3.0

= 50 pF

Ta = –40°C to +85°C
CL = 50 pF

Ta = –40°C
to +85°C
CL = 50 pF

Capacitance

Item Symbol Typ Unit Condition

Input capacitance C
Power dissipation capacitance C

IN

PD

4.5 pF VCC = 5.5 V

35.0 pF VCC = 5.0 V

5

19.20

20.00 Max

16 9

1.3

Unit: mm

6.30

7.40 Max

81

1.11 Max

2.54 ± 0.25

0.48 ± 0.10

5.06 Max

2.54 Min

0.51 Min

Hitachi Code
JEDEC
EIAJ
Weight

7.62

+ 0.13

0.25

– 0.05

0° – 15°

(reference value)

DP-16
Conforms
Conforms

1.07 g

16

Unit: mm

10.06

10.5 Max
9

5.5

1

0.80 Max

1.27

*0.42 ± 0.08

0.40 ± 0.06

*Dimension including the plating thickness

Base material dimension

8

0.12

0.10 ± 0.10

0.15

M

2.20 Max

7.80

0.20 ± 0.04

*0.22 ± 0.05

0.70 ± 0.20

Hitachi Code
JEDEC
EIAJ

(reference value)

Weight

+ 0.20
– 0.30

1.15

0° – 8°

FP-16DA
—
Conforms

0.24 g

16

Unit: mm

9.9

10.3 Max
9

1

1.27

0.635 Max

*0.42 ± 0.08

0.40 ± 0.06

*Dimension including the plating thickness

Base material dimension

8

0.25

+ 0.11

– 0.04

0.14

0.15

3.95

1.75 Max

M

6.10

1.08

0.20 ± 0.03

*0.22 ± 0.03

+ 0.67

0.60

– 0.20

Hitachi Code
JEDEC
EIAJ
Weight

+ 0.10
– 0.30

0° – 8°

(reference value)

FP-16DN
Conforms
Conforms

0.15 g

16 9

18

+ 0.08

*0.22

– 0.07

0.20 ± 0.06

5.00

5.30 Max

0.65 Max

0.65

0.13

Unit: mm

4.40

1.0

M

6.40 ± 0.20

0.10

1.10 Max

*Dimension including the plating thickness

Base material dimension

0.15 ± 0.04

*0.17 ± 0.05

+0.03

–0.04

0.07

0° – 8°

Hitachi Code
JEDEC
EIAJ

(reference value)

Weight

0.50 ± 0.10

TTP-16DA
—
—

0.05 g

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