Datasheet HD74AC273 Datasheet (HIT)

Page 1

HD74AC273

Octal D Flip-Flop

Description

The HD74AC273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition, is transferred to the corresponding flip-flops’s Q output

All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.

Features

• Ideal Buffer for MOS Microprocessor or Memory

• Eight Edge-Triggered D Flip-Flops

• Buffered Common Clock

• Buffered, Asynchronous Master Reset

• See HD74AC373 for Transparent Latch Version

• See HD74AC374 for 3-State Version

• Outputs Source/Sink 24 mA

Page 2

HD74AC273

Pin Arrangement

Logic Symbol

10 11

Gnd

(Top view)

Pin Names

D0 – D7Data Inputs MR Master Reset CP Clock Pulse Input Q0 – Q7Data Outputs

D0 D1 D2 D3 D4 D5 D6 D7

CP MR

0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

Page 3

Logic Diagram

D0 D1 D2 D3 D4 D5 D6 D7

HD74AC273

Q7Q6Q5Q4Q3Q2Q1Q0

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Mode Select-Truth Table

Inputs Outputs

Operating Mode MR CP D

Reset (Clear) L X X L Load “1” H HH Load “0” H LL

H : High Voltage Level L : Low Voltage Level X : Immaterial

: Low-to-High Clock Transition

DC Characteristics (unless otherwise specified)

Item Symbol Max Unit Condition

Maximum quiescent supply current I

80 µAV

8.0 µAV

= VCC or ground, VCC = 5.5 V,

Ta = Worst case

= VCC or ground, VCC = 5.5 V,

Ta = 25°C

Page 4

HD74AC273

AC Characteristics: HD74AC273

Item Symbol V

Maximum clock f

max

Ta = +25°C C

= 50 pF

(V)*1Min Typ Max Min Max Unit

3.3 90 125 — 75 — MHz

Ta = –40°C to +85°C CL = 50 pF

frequency 5.0 140 175 — 125 — Propagation delay t

PLH

3.3 1.0 7.0 12.5 1.0 14.0 ns Clock to output 5.0 1.0 5.5 9.0 1.0 10.0 Propagation delay t

PHL

3.3 1.0 7.0 13.0 1.0 14.5 ns Clock to output 5.0 1.0 5.0 10.0 1.0 11.0 Propagation delay t

PHL

3.3 1.0 7.0 13.0 1.0 14.0 ns MR to output 5.0 1.0 5.0 10.0 1.0 10.5

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

AC Operating Requirements: HD74AC273

Ta = –40°C

Ta = +25°C C

= 50 pF

Item Symbol V

Setup time, HIGH or LOW t

(V)*1Typ Guaranteed Minimum Unit

3.3 3.5 5.5 6.0 ns Data to CP 5.0 2.5 4.0 4.5 Hold time, HIGH or LOW t

3.3 –2.0 0.0 0.0 ns Data to CP 5.0 –1.0 1.0 1.0 Clock pulse width t

3.3 3.5 5.5 6.0 ns HIGH or LOW 5.0 2.5 4.0 4.5 MR Pulse width t

3.3 2.0 5.5 6.0 ns HIGH or LOW 5.0 1.5 4.0 4.5 Recovery time t

rec

3.3 1.5 3.5 4.5 ns MR to CP 5.0 1.0 2.0 3.0

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

to +85°C CL = 50 pF

Page 5

HD74AC273

Capacitance

Item Symbol Typ Unit Condition

Input capacitance C Power dissipation capacitance C

4.5 pF VCC = 5.5 V

50.0 pF VCC = 5.0 V

Page 6

24.50

25.40 Max

Unit: mm

1120

6.30

0.89

1.27 Max

2.54 ± 0.25

1.30

0.48 ± 0.10

7.00 Max

0.51 Min

2.54 Min 5.08 Max

Hitachi Code JEDEC EIAJ Weight

7.62

+ 0.11

0.25

– 0.05

0° – 15°

(reference value)

DP-20N — Conforms

1.26 g

Page 7

Unit: mm

12.6

13 Max

5.5

0.80 Max

1.27

*0.42 ± 0.08

0.40 ± 0.06

*Dimension including the plating thickness

Base material dimension

0.12

0.10 ± 0.10

0.15

2.20 Max

7.80

0.20 ± 0.04

*0.22 ± 0.05

0.70 ± 0.20

Hitachi Code JEDEC EIAJ Weight

(reference value)

+ 0.20 – 0.30

1.15

0° – 8°

FP-20DA — Conforms

0.31 g

Page 8

Unit: mm

12.8

13.2 Max 11

7.50

0.935 Max

1.27

*0.42 ± 0.08

0.40 ± 0.06

*Dimension including the plating thickness

Base material dimension

0.12

0.20 ± 0.10

0.15

2.65 Max

10.40

0.25 ± 0.04

*0.27 ± 0.05

0.70

Hitachi Code JEDEC EIAJ Weight

+ 0.25 – 0.40

1.45

+ 0.57 – 0.30

(reference value)

0° – 8°

FP-20DB Conforms —

0.52 g

Page 9

20 11

110

+0.08

*0.22

–0.07

0.20 ± 0.06

6.50

6.80 Max

0.65 Max

0.65

0.13

Unit: mm

4.40

1.0

6.40 ± 0.20

0.10

1.10 Max

*Dimension including the plating thickness

Base material dimension

0.15 ± 0.04

*0.17 ± 0.05

+0.03

–0.04

0.07

0° – 8°

Hitachi Code JEDEC EIAJ

(reference value)

Weight

0.50 ± 0.10

TTP-20DA — —

0.07 g

Page 10

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

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4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

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7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

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