Page 1
HD74AC175
Quad D-Type Flip-Flop
Description
The HD74AC175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements
where clock and clear inputs are common. The information on the D inputs is stored during the Low-toHigh clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset
input resets all flip-flops, independent of the Clock or D inputs, when Low.
Features
• Edge-Triggered D-Type Inputs
• Buffered Positive Edge-Triggered Clock
• Asynchronous Common Reset
• True and Complement Output
• Outputs Source/Sink 24 mA
Page 2
HD74AC175
Pin Arrangement
Logic Symbol
MR
Q
Q0
D0
D1
Q1
Q1
GND
1
0
2
3
4
5
6
7
8
(Top view)
0
D
CP
D1 D2 D3
16
15
14
13
12
11
10
CC
V
Q3
Q3
D3
D2
Q2
Q2
9
CP
Pin Names
D0 to D3Data Inputs
CP Clock Pulse Input
MR Master Reset Input
Q0 to Q3True Outputs
Q0 to Q 3Complement Outputs
2
MR
Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
Page 3
HD74AC175
Functional Description
The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q
outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their
individual D inputs on the Low-to-High clock (CP) transition, causing individual Q and Q outputs to
follow. A Low input on the Master Reset (MR) will force all Q outputs Low and Q outputs High
independent of Clock or Data inputs. The HD74AC175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.
Truth Table
Inputs Outputs
, MR = H @ t
@ t
n
Dn Qn Qn
LL H
HH L
H : High Voltage Level
L : Low Voltage Level
t
: Bit Time before Clock Pulse
n
t
: Bit Time after Clock Pulse
n + 1
n+1
Logic Diagram
D3CPMR
D
Q
CP
Q
CD
Q3Q3
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
D2
D
CP
Q
Q
CD
Q2Q2
D1
D
CP
Q
Q
CD
Q1Q1
D0
D
CP
Q
Q
CD
Q0Q0
3
Page 4
HD74AC175
DC Characteristics (unless otherwise specified)
Item Symbol Max Unit Condition
Maximum quiescent supply current I
Maximum quiescent supply current I
AC Characteristics
CC
CC
80 µAV
8.0 µAV
= VCC or ground, VCC = 5.5 V,
IN
Ta = Worst case
= VCC or ground, VCC = 5.5 V,
IN
Ta = 25°C
Item Symbol V
Maximum clock f
max
Ta = +25°C
C
= 50 pF
L
(V)*1Min Typ Max Min Max Unit
CC
3.3 149 — — 139 — MHz
Ta = –40°C to +85°C
CL = 50 pF
frequency 5.0 187 — — 187 —
Propagation delay t
CP to Qn or Q
n
Propagation delay t
CP to Qn or Q
n
Propagation delay t
MR to Q
n
Propagation delay t
MR to Q
n
PLH
PHL
PLH
PHL
3.3 1.0 9.5 12.0 1.0 13.5 ns
5.0 1.0 7.0 9.0 1.0 9.5
3.3 1.0 8.5 13.0 1.0 14.5 ns
5.0 1.0 6.0 9.5 1.0 10.5
3.3 1.0 7.5 12.5 1.0 13.5 ns
5.0 1.0 5.5 9.0 1.0 10.0
3.3 1.0 8.5 11.0 1.0 12.5 ns
5.0 1.0 6.0 8.5 1.0 9.5
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
4
Page 5
AC Operating Requirements
Ta = –40°C
Ta = +25°C
C
= 50 pF
L
Item Symbol V
Set-up time, HIGH or LOW t
su
(V)*1Typ Guaranteed Minimum Unit
CC
3.3 2.0 4.5 4.5 ns
Dn to CP 5.0 1.0 3.0 3.0
Hold time, HIGH or LOW t
h
3.3 0 1.0 1.0 ns
Dn to CP 5.0 0 1.0 1.0
CP pulse width HIGH or LOW t
w
3.3 2.5 4.5 4.5 ns
5.0 2.0 3.5 3.5
MR pulse width, LOW t
w
3.3 2.5 4.5 5.0 ns
5.0 2.0 3.5 3.5
Recovery time MR to CP t
rec
3.3 –2.0 0.0 0.0 ns
5.0 –1.0 0.0 0.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
to +85°C
CL = 50 pF
HD74AC175
Capacitance
Item Symbol Typ Unit Condition
Input capacitance C
Power dissipation capacitance C
IN
PD
4.5 pF VCC = 5.5 V
45.0 pF VCC = 5.0 V
5
Page 6
19.20
20.00 Max
16 9
1.3
Unit: mm
6.30
7.40 Max
81
1.11 Max
2.54 ± 0.25
0.48 ± 0.10
5.06 Max
2.54 Min
0.51 Min
Hitachi Code
JEDEC
EIAJ
Weight
7.62
+ 0.13
0.25
– 0.05
0° – 15°
(reference value)
DP-16
Conforms
Conforms
1.07 g
Page 7
16
Unit: mm
10.06
10.5 Max
9
5.5
1
0.80 Max
1.27
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.12
0.10 ± 0.10
0.15
M
2.20 Max
7.80
0.20 ± 0.04
*0.22 ± 0.05
0.70 ± 0.20
Hitachi Code
JEDEC
EIAJ
(reference value)
Weight
+ 0.20
– 0.30
1.15
0° – 8°
FP-16DA
—
Conforms
0.24 g
Page 8
16
Unit: mm
9.9
10.3 Max
9
1
1.27
0.635 Max
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
8
0.25
+ 0.11
– 0.04
0.14
0.15
3.95
1.75 Max
M
6.10
1.08
0.20 ± 0.03
*0.22 ± 0.03
+ 0.67
0.60
– 0.20
Hitachi Code
JEDEC
EIAJ
Weight
+ 0.10
– 0.30
0° – 8°
(reference value)
FP-16DN
Conforms
Conforms
0.15 g
Page 9
16 9
18
+ 0.08
*0.22
– 0.07
0.20 ± 0.06
5.00
5.30 Max
0.65 Max
0.65
0.13
Unit: mm
4.40
1.0
M
6.40 ± 0.20
0.10
1.10 Max
*Dimension including the plating thickness
Base material dimension
0.15 ± 0.04
*0.17 ± 0.05
+0.03
–0.04
0.07
0° – 8°
Hitachi Code
JEDEC
EIAJ
(reference value)
Weight
0.50 ± 0.10
TTP-16DA
—
—
0.05 g
Page 10
Cautions
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intellectual property rights, in connection with use of the information contained in this document.
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received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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