Datasheet HD74ACT164, HD74AC164 Datasheet (HIT)

Page 1
HD74AC164/HD74ACT164
Serial-In, Parallel-Out Shift Register
Description
The HD74AC164/HD74ACT164 is a high-speed 8-bit serial-in/parallel-out shift register. Serial data is entered through a 2-input AND gate synchronous with the Low-to-High transition of the clock. The device features an asynchronous Master Reset which clears the register, setting all outputs Low independent of the clock.
Features
• HD74ACT164 has TTL-Compatible Inputs
Pin Arrangement
Q
Q1
Q2
Q
GND
1
A
B
2
0
3
4
5
3
6
7
(Top view)
14
13
12
11
10
VCC
Q7
Q6
Q5
Q4
MR
9
CP
8
Page 2
HD74AC164/HD74ACT164
Logic Symbol
A B CP
0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
MR Q
Pin Names
A, B Data Inputs CP Clock Pulse Input (Active Rising Edge) MR Master Reset Input (Active Low) Q0 to Q7Outputs
Functional Description
The HD74AC164/HD74ACT164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of these inputs can be used as an active High Enable for data entry through the other inputs. An unused input must be tied High.
Each Low-to-High transition on the Clock (CP) input shifts data one place to the right and enters into Q the logical AND of the two data inputs (A•B) that existed before the rising clock edge. A Low level on the Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q outputs Low.
0
2
Page 3
HD74AC164/HD74ACT164
Mode Select Table
Inputs Outputs
Q
Operating Mode MR ABQ
0
Reset (Clear) L X X L L to L Shift H L L L q0 to q
HL HLq HHLLq HHHHq
H : High Voltage Level L : Low Voltage Level X : Immaterial q
: Lower case letters indicate the state of the referenced input or output one setup time prior to the
n
Low-to-High clock transition.
Logic Diagram
to Q
1
to q
0
to q
0
to q
0
7
6
6
6
6
CP
MR
A B
QD
D
D
C
Q0
QD
C
D
Q1
QD
C
D
Q2
QD
C
D
Q3
QD
C
D
Q4
QD
C
D
Q5
QD
C
D
Q6
Q
C
D
Q7
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
DC Characteristics (unless otherwise specified)
Item Symbol Max Unit Condition
Maximum quiescent supply current I
Maximum quiescent supply current I
Maximum additional ICC/input (HD74ACT164)
CC
CC
I
CCT
80 µAV
8.0 µAV
1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V,
= VCC or ground, VCC = 5.5 V,
IN
Ta = Worst case
= VCC or ground, VCC = 5.5 V,
IN
Ta = 25°C
Ta = Worst case
3
Page 4
HD74AC164/HD74ACT164
AC Characteristics: HD74AC164
Item Symbol V
Maximum clock f
max
Ta = +25°C C
= 50 pF
L
(V)*1Min Typ Max Min Max Unit
CC
3.3 125 — — 100 — MHz
Ta = –40°C to +85°C CL = 50 pF
frequency 5.0 150 — — 125 — Propagation delay t CP to Q
n
Propagation delay t CP to Q
n
Propagation delay t MR to Q
n
PLH
PHL
PHL
3.3 1.0 8.5 13.0 1.0 13.5 ns
5.0 1.0 6.5 10.0 1.0 10.5
3.3 1.0 8.5 13.0 1.0 14.5
5.0 1.0 6.5 10.0 1.0 10.5
3.3 1.0 9.5 16.0 1.0 18.0
5.0 1.0 7.5 11.5 1.0 13.5
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74AC164
Ta = –40°C
Item Symbol V
Setup time A or B to CP t
su
3.3 3.0 5.5 6.0 ns
5.0 2.0 4.6 4.5
Hold time CP to A or B t
h
3.3 –1.5 0.0 0.0
5.0 –1.5 0.0 0.0
Pulse width CP or MR t
w
3.3 2.0 5.5 7.0
5.0 2.0 4.5 5.0
Recovery time MR or CP t
rec
3.3 –2.5 0.0 0.0
5.0 –1.5 0.0 0.0
Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = +25°C C
= 50 pF
L
(V)*1Typ Guaranteed Minimum Unit
CC
to +85°C CL = 50 pF
4
Page 5
AC Characteristics: HD74ACT164
HD74AC164/HD74ACT164
Ta = +25°C C
= 50 pF
L
Item Symbol V
Maximum clock
f
max
(V)*1Min Typ Max Min Max Unit
CC
5.0 100 — — 80 — MHz
frequency Propagation delay
CP to Q
n
Propagation delay CP to Q
n
Propagation delay MR to Q
n
t
PLH
t
PHL
t
PHL
5.0 1.0 9.0 11.5 1.0 12.5 ns
5.0 1.0 9.0 11.5 1.0 12.5
5.0 1.0 9.5 13.0 1.0 14.5
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74ACT164
Ta = +25°C C
L
Item Symbol V
Setup time A or B to CP t Hold time CP to A or B t Pulse width CP or MR t Recovery time MR or CP t
su
h
w
rec
Note: 1. Voltage Range 5.0 is 5.0 V ± 0.5 V
(V)*1Typ Guaranteed Minimum Unit
CC
5.0 2.5 7.0 8.0 ns
5.0 0.0 1.5 1.5
5.0 4.5 7.0 8.0
5.0 0.0 2.0 2.0
= 50 pF
Ta = –40°C to +85°C CL = 50 pF
Ta = –40°C to +85°C CL = 50 pF
Capacitance
Item Symbol Typ Unit Condition
Input capacitance C Power dissipation capacitance C
IN
PD
4.5 pF VCC = 5.5 V
20.0 pF VCC = 5.0 V
5
Page 6
1
19.20
20.32 Max
1.30
Unit: mm
814
6.30
7.40 Max
7
2.54 ± 0.25
2.39 Max
0.48 ± 0.10
2.54 Min 5.06 Max
0.51 Min
Hitachi Code JEDEC EIAJ Weight
7.62
+ 0.10
0.25
– 0.05
0° – 15°
(reference value)
DP-14 Conforms Conforms
0.97 g
Page 7
14
1.27
10.5 Max
1
10.06
1.42 Max
Unit: mm
8
5.5
7
+ 0.20
7.80
– 0.30
2.20 Max *0.22 ± 0.05
1.15
0.20 ± 0.04 0° – 8°
0.70 ± 0.20
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
0.12
0.10 ± 0.10
0.15
M
Hitachi Code JEDEC EIAJ
(reference value)
Weight
FP-14DA — Conforms
0.23 g
Page 8
9.05 Max
14
Unit: mm
8.65
8
*Pd plating
1
0.635 Max
1.27
*0.40 ± 0.06
7
+ 0.11
– 0.04
0.14
0.25
3.95
1.75 Max
0.15
M
6.10
1.08
*0.20 ± 0.05
0.60
Hitachi Code JEDEC EIAJ Weight
+ 0.10 – 0.30
0° – 8°
+ 0.67 – 0.20
(reference value)
FP-14DN Conforms Conforms
0.13 g
Page 9
14 8
17
+0.08
*0.22
–0.07
0.20 ± 0.06
5.00
5.30 Max
0.83 Max
0.65
0.13
Unit: mm
4.40
1.0
M
6.40 ± 0.20
0.10
1.10 Max
*Dimension including the plating thickness
Base material dimension
0.15 ± 0.04
*0.17 ± 0.05
+0.03
–0.04
0.07
0° – 8°
Hitachi Code JEDEC EIAJ
(reference value)
Weight
0.50 ± 0.10
TTP-14D — —
0.05 g
Page 10
Cautions
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4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail­safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.
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