The HD74AC164/HD74ACT164 is a high-speed 8-bit serial-in/parallel-out shift register. Serial data is
entered through a 2-input AND gate synchronous with the Low-to-High transition of the clock. The device
features an asynchronous Master Reset which clears the register, setting all outputs Low independent of the
clock.
Features
• Outputs Source/Sink 24 mA
• HD74ACT164 has TTL-Compatible Inputs
Pin Arrangement
Q
Q1
Q2
Q
GND
1
A
B
2
0
3
4
5
3
6
7
(Top view)
14
13
12
11
10
VCC
Q7
Q6
Q5
Q4
MR
9
CP
8
Page 2
HD74AC164/HD74ACT164
Logic Symbol
A
B
CP
0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
MR Q
Pin Names
A, BData Inputs
CPClock Pulse Input (Active Rising Edge)
MRMaster Reset Input (Active Low)
Q0 to Q7Outputs
Functional Description
The HD74AC164/HD74ACT164 is an edge-triggered 8-bit shift register with serial data entry and an
output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of
these inputs can be used as an active High Enable for data entry through the other inputs. An unused input
must be tied High.
Each Low-to-High transition on the Clock (CP) input shifts data one place to the right and enters into Q
the logical AND of the two data inputs (A•B) that existed before the rising clock edge. A Low level on the
Master Reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all Q
outputs Low.
0
2
Page 3
HD74AC164/HD74ACT164
Mode Select Table
InputsOutputs
Q
Operating ModeMRABQ
0
Reset (Clear)LXXLL to L
ShiftHLLLq0 to q
HL HLq
HHLLq
HHHHq
H :High Voltage Level
L :Low Voltage Level
X :Immaterial
q
:Lower case letters indicate the state of the referenced input or output one setup time prior to the
n
Low-to-High clock transition.
Logic Diagram
to Q
1
to q
0
to q
0
to q
0
7
6
6
6
6
CP
MR
A
B
QD
D
D
C
Q0
QD
C
D
Q1
QD
C
D
Q2
QD
C
D
Q3
QD
C
D
Q4
QD
C
D
Q5
QD
C
D
Q6
Q
C
D
Q7
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
DC Characteristics (unless otherwise specified)
ItemSymbol MaxUnitCondition
Maximum quiescent supply currentI
Maximum quiescent supply currentI
Maximum additional ICC/input
(HD74ACT164)
CC
CC
I
CCT
80µAV
8.0µAV
1.5mAVIN = VCC – 2.1 V, VCC = 5.5 V,
= VCC or ground, VCC = 5.5 V,
IN
Ta = Worst case
= VCC or ground, VCC = 5.5 V,
IN
Ta = 25°C
Ta = Worst case
3
Page 4
HD74AC164/HD74ACT164
AC Characteristics: HD74AC164
ItemSymbolV
Maximum clockf
max
Ta = +25°C
C
= 50 pF
L
(V)*1MinTypMaxMinMaxUnit
CC
3.3125——100—MHz
Ta = –40°C to +85°C
CL = 50 pF
frequency5.0150——125—
Propagation delayt
CP to Q
n
Propagation delayt
CP to Q
n
Propagation delayt
MR to Q
n
PLH
PHL
PHL
3.31.08.513.01.013.5ns
5.01.06.510.01.010.5
3.31.08.513.01.014.5
5.01.06.510.01.010.5
3.31.09.516.01.018.0
5.01.07.511.51.013.5
Note:1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74AC164
Ta = –40°C
ItemSymbolV
Setup time A or B to CPt
su
3.33.05.56.0ns
5.02.04.64.5
Hold time CP to A or Bt
h
3.3–1.50.00.0
5.0–1.50.00.0
Pulse width CP or MRt
w
3.32.05.57.0
5.02.04.55.0
Recovery time MR or CPt
rec
3.3–2.50.00.0
5.0–1.50.00.0
Note:1. Voltage Range 3.3 is 3.3 V ± 0.3 V
Voltage Range 5.0 is 5.0 V ± 0.5 V
Ta = +25°C
C
= 50 pF
L
(V)*1TypGuaranteed MinimumUnit
CC
to +85°C
CL = 50 pF
4
Page 5
AC Characteristics: HD74ACT164
HD74AC164/HD74ACT164
Ta = +25°C
C
= 50 pF
L
ItemSymbolV
Maximum clock
f
max
(V)*1MinTypMaxMinMaxUnit
CC
5.0100——80—MHz
frequency
Propagation delay
CP to Q
n
Propagation delay
CP to Q
n
Propagation delay
MR to Q
n
t
PLH
t
PHL
t
PHL
5.01.09.011.51.012.5ns
5.01.09.011.51.012.5
5.01.09.513.01.014.5
Note:1. Voltage Range 5.0 is 5.0 V ± 0.5 V
AC Operating Requirements: HD74ACT164
Ta = +25°C
C
L
ItemSymbolV
Setup time A or B to CPt
Hold time CP to A or Bt
Pulse width CP or MRt
Recovery time MR or CPt
su
h
w
rec
Note:1. Voltage Range 5.0 is 5.0 V ± 0.5 V
(V)*1TypGuaranteed MinimumUnit
CC
5.02.57.08.0ns
5.00.01.51.5
5.04.57.08.0
5.00.02.02.0
= 50 pF
Ta = –40°C to +85°C
CL = 50 pF
Ta = –40°C
to +85°C
CL = 50 pF
Capacitance
ItemSymbolTypUnitCondition
Input capacitanceC
Power dissipation capacitanceC
IN
PD
4.5pFVCC = 5.5 V
20.0pFVCC = 5.0 V
5
Page 6
1
19.20
20.32 Max
1.30
Unit: mm
814
6.30
7.40 Max
7
2.54 ± 0.25
2.39 Max
0.48 ± 0.10
2.54 Min 5.06 Max
0.51 Min
Hitachi Code
JEDEC
EIAJ
Weight
7.62
+ 0.10
0.25
– 0.05
0° – 15°
(reference value)
DP-14
Conforms
Conforms
0.97 g
Page 7
14
1.27
10.5 Max
1
10.06
1.42 Max
Unit: mm
8
5.5
7
+ 0.20
7.80
– 0.30
2.20 Max
*0.22 ± 0.05
1.15
0.20 ± 0.04
0° – 8°
0.70 ± 0.20
*0.42 ± 0.08
0.40 ± 0.06
*Dimension including the plating thickness
Base material dimension
0.12
0.10 ± 0.10
0.15
M
Hitachi Code
JEDEC
EIAJ
(reference value)
Weight
FP-14DA
—
Conforms
0.23 g
Page 8
9.05 Max
14
Unit: mm
8.65
8
*Pd plating
1
0.635 Max
1.27
*0.40 ± 0.06
7
+ 0.11
– 0.04
0.14
0.25
3.95
1.75 Max
0.15
M
6.10
1.08
*0.20 ± 0.05
0.60
Hitachi Code
JEDEC
EIAJ
Weight
+ 0.10
– 0.30
0° – 8°
+ 0.67
– 0.20
(reference value)
FP-14DN
Conforms
Conforms
0.13 g
Page 9
148
17
+0.08
*0.22
–0.07
0.20 ± 0.06
5.00
5.30 Max
0.83 Max
0.65
0.13
Unit: mm
4.40
1.0
M
6.40 ± 0.20
0.10
1.10 Max
*Dimension including the plating thickness
Base material dimension
0.15 ± 0.04
*0.17 ± 0.05
+0.03
–0.04
0.07
0° – 8°
Hitachi Code
JEDEC
EIAJ
(reference value)
Weight
0.50 ± 0.10
TTP-14D
—
—
0.05 g
Page 10
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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For further information write to:
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Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.
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