Datasheet HD-6409 Datasheet (Intersil Corporation)

HD-6409

March 1997

Features

• Converter or Repeater Mode

• Independent Manchester Encoder and Decoder
Operation

• Static to One Megabit/sec Data Rate Guaranteed

• Low Bit Error Rate

• Digital PLL Clock Recovery

• On Chip Oscillator

• Low Operating Power: 50mW Typical at +5V

• Available in 20 Lead Dual-In-Line and 20 Pad LCC
Package

Ordering Information

TEMPERATURE

PACKAGE

PDIP -40oC to +85oC HD3-6409-9 E20.3
SOIC -40oC to +85oC HD9P6409-9 M20.3
CERDIP -40oC to +85oC HD1-6409-9 F20.3

DESC -55oC to 125oC 5962-9088801MRA F20.3

CLCC -40oC to +85oC HD4-6409-9 J20.A

DESC -55oC to 125oC 5962-9088801M2A J20.A

RANGE 1 MEGABIT/SEC

PKG.

NO.

CMOS Manchester Encoder-Decoder

Description

The HD-6409 Manchester Encoder-Decoder (MED) is a high
speed, low power device man uf actured using self-aligned sil­icon gate technology. The device is intended for use in serial
data communication, and can be operated in either of two
modes. In the converter mode, the MED converts Non
return-to-Zero code (NRZ) into Manchester code and
decodes Manchester code into Nonreturn-to-Zero code. For
serial data communication, Manchester code does not have
some of the deficiencies inherent in Nonreturn-to-Zero code.
For instance, use of the MED on a serial line eliminates DC
components, provides clock recovery, and gives a relatively
high degree of noise immunity. Because the MED converts
the most commonly used code (NRZ) to Manchester code,
the advantages of using Manchester code are easily realized
in a serial data link.

In the Repeater mode, the MED accepts Manchester code
input and reconstructs it with a recovered clock. This mini­mizes the effects of noise on a serial data link. A digital
phase lock loop generates the recovered clock. A maximum
data rate of 1MHz requires only 50mW of power.

Manchester code is used in magnetic tape recording and in
fiber optic communication, and generally is used where data
accuracy is imperative. Because it frames blocks of data, the
HD-6409 easily interfaces to protocol controllers.

Pinouts

HD-6409 (CERDIP, PDIP, SOIC)

TOP VIEW

1

BZI

BOI

2

UDI

3

SD/CDS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

SDO

SRST

NVM

DCLK

RST

GND

4
5
6
7
8
9

10

| Copyright © Intersil Corporation 1999

V

20

CC

BOO

19

BZO

18

SS

17

ECLK

16

CTS

15

MS

14

OX

13
12

IX

11

CO

SD/CDS

SDO

SRST

NVM

DCLK

5-1

HD-6409 (CLCC)

TOP VIEW

UDI

BOI

BZI

3212019

4

5

6

7

8

10 11 12 139

GND

CO

RST

VCCBOO

BZO

18

SS

17

ECLK

16

CTS

15

MS

14

IX

OX

File Number 2951.1

Block Diagram

HD-6409

SDO
NVM

BOI

BZI

UDI

RST

SD/CDS

CO

RESET

IX

OX

SS

Logic Symbol

DAT A

INPUT

LOGIC

OSCILLATOR

EDGE

DETECTOR

SD

5-BIT SHIFT

REGISTER

AND DECODER

INPUT/
OUTPUT
SELECT

COUNTER

CIRCUITS

COMMAND

SYNC

GENERATOR

MANCHESTER

ENCODER

OUTPUT
SELECT

LOGIC

BOO

BZO

CTS

SRST

MS

ECLK
DCLK

SS

CO

SD/CDS

ECLK

MS

RST

SDO

DCLK

NVM

SRST

17
11

4

16

14

9

5
8
7

6

CLOCK

GENERATOR

ENCODER

CONTROL

DECODER

13

OX

12

IX

19

BOO

18

BZO

15

CTS

2

BOI

1

BZI

3

UDI

5-2

HD-6409

Pin Description

PIN

NUMBER TYPE SYMBOL NAME DESCRIPTION

1 I BZl Bipolar Zero Input Used in conjunction with pin 2, Bipolar One Input (BOl), to input Manchester II

encoded data to the decoder, BZI and BOl are logical complements. When using
pin 3, Unipolar Data Input (UDI) for data input, BZI must be held high.

2 I BOl Bipolar One Input Used in conjunction with pin 1, Bipolar Zero Input (BZI), to input Manchester II

encoded data to the decoder, BOI and BZI are logical complements. When using
pin 3, Unipolar Data Input (UDI) for data input, BOl must be held low.

3 I UDI Unipolar Data Input An alternate to bipolar input (BZl, BOl), Unipolar Data Input (UDl) is used to input

Manchester II encoded data to the decoder. When using pin 1 (BZl) and pin 2
(BOl) for data input, UDI must be held low.

4 I/O SD/CDS Serial Data/Com-

mand Data Sync

5 O SDO Serial Data Out The decoded serial NRZ data is transmitted out synchronously with the decoder

6OSRST Serial Reset In the converter mode,SRST followsRST. In the repeater mode, when RST goes

7ONVM Nonvalid Manchester A low on NVM indicates that the decoder has received invalid Manchester data

8 O DCLK Decoder Clock The decoder clock is a 1X clock recovered from BZl and BOl, or UDI to synchro-

9IRST Reset In the converter mode, a low on RST forces SDO, DCLK, NVM, and SRST low.

10 I GND Ground Ground
11 O C
12 I I

13 O O

14 I MS Mode Select MS must be held low for operation in the converter mode, and high for operation

15 I CTS Clear to Send In the converter mode, a high disables the encoder, forcing outputsBOO,BZO high

16 O ECLK Encoder Clock In the converter mode, ECLK is a 1X clock output used to receive serial NRZ data

Clock Output Buffered output of clock input IX. May be used as clock signal for other peripherals.

O

Clock Input IX is the input for an external clock or, if the internal oscillator is used, IX and O

X

Clock Drive If the internal oscillator is used, OX and IX are used for the connection of the crys-

X

In the converter mode, SD/CDS is an input used to receive serial NRZ data. NRZ
data is accepted synchronously on the falling edge of encoder clock output
(ECLK). In the repeater mode, SD/CDS is an output indicating the status of last
valid sync pattern received. A high indicates a command sync and a low indicates
a data sync pattern.

clock (DCLK). SDO is forced low when RST is low.

low, SRST goes low and remains low afterRST goes high.SRST goes high only
when RST is high, the reset bit is zero, and a valid synchronization sequence is
received.

and present data on Serial Data Out (SDO) is invalid. A high indicates that the
sync pulse and data were valid and SDO is valid.NVM is set low by a low onRST,
and remains low after RST goes high until valid sync pulse followed by two valid
Manchester bits is received.

nously output received NRZ data (SDO).

A high on RST enables SDO and DCLK, and forces SRST high. NVM remains
low after RST goes high until a valid sync pulse followed by two Manchester bits
is received, after which it goes high. In the repeater mode, RST has the same ef­fect on SDO, DCLK and NVM as in the converter mode. When RST goes low,
SRST goes low and remains low after RST goes high. SRST goes high only
when RST is high, the reset bit is zero and a valid synchronization sequence is
received.

are used for the connection of the crystal.

tal.

in the repeater mode.

and ECLK low. A high to low transition ofCTS initiates transmission of a Command
sync pulse. A low on CTS enables BOO, BZO, and ECLK. In the repeater mode,
the function ofCTS is identical to that of the converter mode with the exception that
a transition of CTS does not initiate a synchronization sequence.

to SD/CDS. In the repeater mode, ECLK is a 2X clock which is recovered from
BZl and BOl data by the digital phase locked loop.

X

5-3

HD-6409

Pin Description

PIN

NUMBER TYPE SYMBOL NAME DESCRIPTION

17 I SS Speed Select A logic high on SS sets the data rate at 1/32 times the clock frequency while a

low sets the data rate at 1/16 times the clock frequency.

18 O BZO BipolarZero Output BZO and its logical complement BOO are the Manchester data outputs of the en-

coder. The inactive state for these outputs is in the high state.
19 O BOO Bipolar One Out See pin 18.
20 I V

NOTE: (I) Input (O) Output

CC

V

CC

VCC is the +5V power supply pin. A 0.1µF decoupling capacitor from VCC (pin-

20) to GND (pin-10) is recommended.

Encoder Operation

The encoder uses free running clocks at 1X and 2X the data
rate derived from the system clock l
is used to control the encoder outputs, ECLK,

for internal timing. CTS

X

BOO and
BZO. A free running 1X ECLK is transmitted out of the
encoder to drive the external circuits which supply the NRZ
data to the MED at pin SD/CDS.

A low on

CTS enables encoder outputs ECLK, BOO and
BZO, while a high on CTS forces BZO, BOO high and holds
ECLK low. When

CTS goes from high to low , a synchro-

nization sequence is transmitted out on

1

BOO and BZO. A

synchronization sequence consists of eight Manchester “0”

CTS

1

ECLK

SD/CDS

‘1’ ‘0’ ‘1’

BZO

2

‘1’ ‘0’ ‘1’

BOO

0000 0000

bits followed by a command sync pulse. A command

2

sync pulse is a 3-bit wide pulse with the first 1 1/2 bits high
followed b y 1 1/2 bits low. Serial NRZ data is clocked into

3

the encoder at SD/CDS on the high to low transition of ECLK
during the command sync pulse. The NRZ data received is
encoded into Manchester II data and transmitted out on
BOO and BZO following the command sync pulse. Fol-

4

lowing the synchronization sequence, input data is encoded
and transmitted out continuously without parity check or
word framing. The length of the data block encoded is
defined by

DON’T CARE

EIGHT “0’s”

CTS. Manchester data out is inverted.

3

COMMAND

SYNC

4

t

CE6

FIGURE 1. ENCODER OPERATION

Decoder Operation

The decoder requires a single clock with a frequency 16X or
32X the desired data rate. The rate is selected on the speed
select with SS low producing a 16X clock and high a 32X
clock. For long data links the 32X mode should be used as
this permits a wider timing jitter margin. The internal opera­tion of the decoder utilizes a free running clock synchronized
with incoming data for its clocking.

The Manchester II encoded data can be presented to the
decoder in either of two ways. The Bipolar One and Bipolar

SYNCHRONIZATION SEQUENCE

t

CE5

Zero inputs will accept data from differential inputs such as a
comparator sensed transformer coupled bus. The Unipolar
Data input can only accept noninverted Manchester II
encoded data i.e.

Bipolar One Out through an inverter to
Unipolar Data Input. The decoder continuously monitors this
data input for valid sync pattern. Note that while the MED
encoder section can generate only a command sync pattern,
the decoder can recognize either a command or data sync
pattern. A data sync is a logically inverted command sync.

5-4

HD-6409

There is a three bit delay between UDI, BOl, or BZI input and
the decoded NRZ data transmitted out of SDO.

Control of the decoder outputs is provided by the
When

RST is low, SDO, DCLK and NVM are forced low.

When

RST is high, SDO is transmitted out synchronously
with the recovered clock DCLK. The
low after a low to high transition on

NVM output remains

RST until a valid sync

RST pin.

pattern is received.

DCLK

UDI

COMMAND

SYNC

SDO

RST

NVM

1001010101010

FIGURE 2. DECODER OPERATION

Repeater Operation

The decoded data at SDO is in NRZ format. DCLK is pro­vided so that the decoded bits can be shifted into an external
register on every high to low transition of this clock. Three bit
periods after an invalid Manchester bit is received on UDI, or
BOl,

NVM goes low synchronously with the questionable
data output on SDO. FURTHER, THE DECODER DOES
NOT REESTABLISH PROPER DATA DECODING UNTIL
ANOTHER SYNC PATTERN IS RECOGNIZED.

Manchester Il data can be presented to the repeater in either
of two ways. The inputs Bipolar One In and Bipolar Zero In
will accept data from differential inputs such as a comparator
or sensed transformer coupled bus. The input Unipolar Data
In accepts only noninverted Manchester II coded data. The
decoder requires a single clock with a frequency 16X or 32X
the desired data rate. This clock is selected to 16X with
Speed Select low and 32X with Speed Select high. For long
data links the 32X mode should be used as this permits a
wider timing jitter margin.

The inputs UDl, or BOl, BZl are delayed approximately 1/2
bit period and repeated as outputs

BOO and BZO. The 2X
ECLK is transmitted out of the repeater synchronously with
BOO and BZO.

INPUT

COUNT

ECLK

UDI

BZO

BOO

1 234567

SYNC PULSE

A low on

CTS enables ECLK, BOO, and BZO. In contrast to
the converter mode, a transition on CTS does not initiate a
synchronization sequence of eight 0’s and a command sync.
The repeater mode does recognize a command or data sync
pulse. SD/CDS is an output which reflects the state of the
most recent sync pulse received, with high indicating a com­mand sync and low indicating a data sync.

When

RST is low, the outputs SDO, DCLK, and NVM are

low , and

SRST is set low .SRST remains low after RST goes
high and is not reset until a sync pulse and two valid
manchester bits are received with the reset bit low. The reset
bit is the first data bit after the sync pulse. With RST high,
NRZ Data is transmitted out of Serial Data Out synchro­nously with the 1X DCLK.

RST

SRST

FIGURE 3. REPEATER OPERATION

5-5

Manchester Code

HD-6409

Nonreturn-to-Zero (NRZ) code represents the binary values
logic-O and Iogic-1 with a static level maintained throughout
the data cell. In contrast, Manchester code represents data
with a level transition in the middle of the data cell. Manches­ter has bandwidth, error detection, and synchronization
advantages over NRZ code.

The Manchester II code Bipolar One and Bipolar Zero shown
below are logical complements. The direction of the transi­tion indicates the binary value of data. A logic-0 in Bipolar
One is defined as a Low to high transition in the middle of
the data cell, and a logic-1 as a high to low mid bit transition,
Manchester Il is also known as Biphase-L code.

The bandwidth of NRZ is from DC to the clock frequency fc/2,
while that of Manchester is from fc/2 to fc. Thus, Manchester
can be AC or transformer coupled, which has considerable
advantages over DC coupling. Also, the ratio of maximum to
minimum frequency of Manchester extends one octave, while
the ratio for NRZ is the range of 5-10 octaves. It is much eas­ier to design a narrow band than a wideband amp.

Secondly, the mid bit transition in each data cell provides the
code with an effective error detection scheme. If noise pro­duces a logic inversion in the data cell such that there is no
transition, an error indiction is given, and synchronization
must be re-established. This places relatively stringent
requirements on the incoming data.

The synchronization advantages of using the HD-6409 and
Manchester code are several fold. One is that Manchester is
a self clocking code. The clock in serial data communication
defines the position of each data cell. Non self clocking
codes, as NRZ, often require an extra clock wire or clock
track (in magnetic recording). Further, there can be a phase
variation between the clock and data track. Crosstalk
between the two may be a problem. In Manchester, the
serial data stream contains both the clock and the data, with
the position of the mid bit transition representing the clock,
and the direction of the transition representing data. There is
no phase variation between the clock and the data.

A second synchronization advantage is a result of the num­ber of transitions in the data. The decoder resynchronizes on
each transition, or at least once every data cell. In contrast,
receivers using NRZ, which does not necessarily have tran­sitions, must resynchronize on frame bit transitions, which
occur far less often, usually on a character basis. This more
frequent resynchronization eliminates the cumulative effect
of errors over successive data cells. A final synchronization
advantage concerns the HD-6409’s sync pulse used to ini­tiate synchronization. This three bit wide pattern is suffi­ciently distinct from Manchester data that a false start by the
receiver is unlikely.

Crystal Oscillator Mode

C1

16MHz

X1R1C0

C1

BIT PERIOD

BINARY CODE

NONRETURN

TO ZERO

BIPOLAR ONE

BIPOLAR ZERO

FIGURE 4. MANCHESTER CODE

I

X

C1 = 32pF
C0 = CRYSTAL + STRAY
X1 = AT CUT PARALLEL

RESONANCE
FUNDAMENTAL
MODE

(TYP) = 30Ω

R

S

R1 = 15MΩ

O

X

C

O

12345
01100

LC Oscillator Mode

C1

C1

I

X

C1 = 20pF
C0 = 5pF

L

O

X

C

f

≈

E

≈

O

C1 2C0–

------------------------- ­2

1

-----------------------

2π LC

e

FIGURE 5. CRYSTAL OSCILLATOR MODE

FIGURE 6. LC OSCILLATOR MODE

5-6

HD-6409

Using the 6409 as a Manchester Encoded UART

BIPOLAR IN

BIPOLAR IN

RESET

CP

BQHA

CK

‘164

DATA IN

‘273

PARALLEL DATA OUT

BCKA

‘164

DATA IN

‘273

BZI

BOI

UDI
SD/CDS
SDO
SRST
NVM

DCLK
RST

GND

V

CC

BOO

BZO

SS

ECLK

CTS

MS
OX

CO

BIPOLAR OUT
BIPOLAR OUT

CTS

IX

LOAD

LOAD QHCK

‘165

PARALLEL DATA IN

LOAD QHCKSI

‘165

FIGURE 7. MANCHESTER ENCODER UART

5-7

HD-6409

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC+0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Thermal Information

Thermal Resistance (Typical) θ

CERDIP. . . . . . . . . . . . . . . . . . . . . . . . . . 83oC/W 23oC/W

CLCC Package . . . . . . . . . . . . . . . . . . . . 95oC/W 26oC/W

JA

θ

JC

PDIP Package. . . . . . . . . . . . . . . . . . . . . 75oC/W N/A

SOIC Package. . . . . . . . . . . . . . . . . . . . . 100oC/W N/A

Storage Temperature Range. . . . . . . . . . . . . . . . . .-65oC to +150oC

Maximum Junction Temperature

Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC

Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . .+300oC

( Lead Tips Only for Surface Mount Packages)

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 Gates

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Operating Conditions

Operating Temperature Range. . . . . . . . . . . . . . . . . -40oC to +85oC

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . .50ns Max

NOTES:

1. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles.

2. The input conditions specified are nominal values, the actual input waveforms transition spans may vary by ±2 IX clock cycles (16X mode)
or ±6 IX clock cycles (32X mode).

3. The maximum zero crossing tolerance is ±2 IX clock cycles (16X mode) or ±6 IX clock cycles (32 mode) from the nominal.

Sync. Transition Span (t2). . . . . . . . . . 1.5 DBP Typical, (Notes 1, 2)

Short Data Transition Span (t4). . . . . . .0.5DBP Typical, (Notes 1, 2)

Long Data Transition Span (t5) . . . . . . .1.0DBP Typical, (Notes 1, 2)

Zero Crossing Tolerance (tCD5) . . . . . . . . . . . . . . . . . . . . . .(Note 3)

DC Electrical Specifications V

= 5.0V ± 10%, TA = -40oC to +85o (HD-6409-9)

CC

SYMBOL PARAMETER MIN MAX UNITS (NOTE 1) TEST CONDITIONS

V
V

V

IHR

V

ILR

V

IHC

V

ILC

I
I

I

O

V

OH

V

OL

I

CCSB

IH
IL

I
I

Logical “1” Input Voltage 70% V

CC

Logical “0” Input Voltage - 20% V

-VV

CC

VVCC = 4.5V

CC

= 4.5V

Logic “1” Input Voltage (Reset) VCC -0.5 - V VCC = 5.5V
Logic “0” Input Voltage (Reset) - GND +0.5 V VCC = 4.5V
Logical “1” Input Voltage (Clock) VCC -0.5 - V VCC = 5.5V
Logical “0” Input Voltage (Clock) - GND +0.5 V VCC = 4.5V
Input Leakage Current (Except IX) -1.0 +1.0 µAVIN = VCC or GND, VCC = 5.5V
Input Leakage Current (IX) -20 +20 µAVIN = VCC or GND, VCC = 5.5V
I/O Leakage Current -10 +10 µAV

= VCC or GND, VCC = 5.5V

OUT

Output HIGH Voltage (All Except OX)VCC -0.4 - V IOH = -2.0mA, VCC = 4.5V (Note 2)
Output LOW Voltage (All Except OX) - 0.4 V IOL = +2.0mA, VCC = 4.5V (Note 2)
Standby Power Supply Current - 100 µAVIN = VCCor GND, VCC= 5.5V,

Outputs Open

I

CCOP

Operating Power Supply Current - 18.0 mA f = 16.0MHz, VIN = VCC or GND

VCC = 5.5V, CL = 50pF

F

T

Functional Test - - - (Note 1)

NOTES:

1. Tested as follows: f = 16MHz, VIH = 70% VCC, VIL = 20% VCC, VOH≥ VCC/2, and VOL ≤ VCC/2, VCC = 4.5V and 5.5V.

2. Interchanging of force and sense conditions is permitted

Capacitance T

= +25oC, Frequency = 1MHz

A

SYMBOL PARAMETER TYP UNITS TEST CONDITIONS

Input Capacitance 10 pF All measurements are referenced to device GND
Output Capacitance 12 pF

C

C

OUT

IN

5-8

HD-6409

AC Electrical Specifications V

= 5.0V ±10%, TA = -40oC to +85oC (HD-6409-9)

CC

SYMBOL PARAMETER MIN MAX UNITS (NOTE 1) TEST CONDITIONS

f
t

t

CH

t

t

CE1

t

CE2

t

CD2

t

t

CE3

t

CE4

t

CE5

t

CE6

t

CE7

t

CD1

t

CD3

t

CD4

t
t

t
t

CL

R2

t

t

t

t

R1
R3

C
C
1
3

r
f
r
f

Clock Frequency - 16 MHz ­Clock Period 1/f

C

- sec ­Bipolar Pulse Width tC+10 - ns ­One-Zero Overlap - tC-10 ns ­Clock High Time 20 - ns f = 16.0MHz
Clock Low Time 20 - ns f = 16.0MHz
Serial Data Setup Time 120 - ns ­Serial Data Hold Time 0 - ns ­DCLK to SDO, NVM - 40 ns ­ECLK to BZO - 40 ns ­Output Rise Time (All except Clock) - 50 ns From 1.0V to 3.5V, CL = 50pF, Note 2
Output Fall Time (All except Clock) - 50 ns From 3.5V to 1.0V, CL = 50pF, Note 2
Clock Output Rise Time - 11 ns From 1.0V to 3.5V, CL = 20pF, Note 2
Clock Output Fall Time - 11 ns From 3.5V to 1.0V, CL = 20pF, Note 2
ECLK to BZO, BOO 0.5 1.0 DBP Notes 2, 3
CTS Low to BZO, BOO Enabled 0.5 1.5 DBP Notes 2, 3
CTS Low to ECLK Enabled 10.5 11.5 DBP Notes 2, 3
CTS High to ECLK Disabled - 1.0 DBP Notes 2, 3
CTS High to BZO, BOO Disabled 1.5 2.5 DBP Notes 2, 3
UDI to SDO, NVM 2.5 3.0 DBP Notes 2, 3
RST Low to CDLK, SDO, NVM Low 0.5 1.5 DBP Notes 2, 3
RST High to DCLK, Enabled 0.5 1.5 DBP Notes 2, 3
UDI to BZO, BOO 0.5 1.0 DBP Notes 2, 3
UDI to SDO, NVM 2.5 3.0 DBP Notes 2, 3

NOTES:

1. AC testing as follows: f = 4.0MHz, VIH = 70% VCC, VIL = 20% VCC, Speed Select = 16X, VOH≥ VCC/2, VOL ≤ VCC/2, VCC = 4.5V and

5.5V. Input rise and fall times driven at 1ns/V, Output load = 50pF.

2. Guaranteed via characteristics at initial device design and after major process and/or design changes, not tested.

3. DBP-Data Bit Period, Clock Rate = 16X, one DBP = 16 Clock Cycles; Clock Rate = 32X, one DBP = 32 Clock Cycles.

5-9

Timing Waveforms

BIT PERIOD BIT PERIOD BIT PERIOD

BOI

BZI

BOI

BZI

T

1

COMMAND SYNC

T

1

T

2

T

2

DATA SYNC

HD-6409

NOTE: UDI = 0, FOR NEXT DIAGRAMS

T

3

T

1

T

1

T

3

T

3

T

2

T

3

T

2

BOI

BZI

UDI

UDI

UDI

10%

T

1

T

3

T

4

T

3

T

5

T

1

T

3

T

5

T

3

T

1

T

4

ONEONE ZERO

NOTE: BOI = 0, BZI = 1 FOR NEXT DIAGRAMS

T

2

T

2

COMMAND SYNC

T

2

T

2

DATA SYNC

T

4

T

5

T

5

T

4

ZERO ONE ONEONE

FIGURE 8.

t

90%

C

t

r

t

CH

t

CL

t

f

t

r

1.0V

3.5V

t

f

FIGURE 9. CLOCK TIMING FIGURE 10. OUTPUT WAVEFORM

T

3

T

4

5-10

HD-6409

Timing Waveforms

CTS

BZO

t

BOO

ECLK

CE4

FIGURE 12. ENCODER TIMING FIGURE 13. ENCODER TIMING

(Continued)

ECLK

SD/CDS

t

CE5

BZO

BOO

t

CE2

t

CE1

t

CE3

FIGURE 11. ENCODER TIMING

CTS

ECLK

BZO

BOO

t

CE6

t

CE7

DCLK

UDI

SDO

NVM

MANCHESTER

LOGIC-1

MANCHESTER

LOGIC-0

t

CD1

NOTE: Manchester Data-In is not synchronous with Decoder Clock.

Decoder Clock is synchronous with decoded NRZ out of SDO.

FIGURE 14. DECODER TIMING

RST

DCLK, SDO,

NVM

50%
t

CD3

50%

MANCHESTER

LOGIC-0

MANCHESTER

LOGIC-1

t

CD2

t

CD2

RST

DCLK

50%

t

CD5

NRZ

LOGIC-1

t

CD4

FIGURE 15. DECODER TIMING FIGURE 16. DECODER TIMING

5-11

HD-6409

Timing Waveforms

UDI

MANCHESTER ‘1’

ECLK

t

R2

t

BZO

SDO

NVM

R1

Test Load Circuit

(Continued)

MANCHESTER ‘0’ MANCHESTER ‘0’ MANCHESTER ‘1’

t

R2

MANCHESTER ‘1’ MANCHESTER ‘0’ MANCHESTER ‘0’

t

R3

t

R3

FIGURE 17. REPEATER TIMING

DUT

C

L

(NOTE)

NOTE: INCLUDES STRAY AND JIG

CAPACITANCE

FIGURE 18. TEST LOAD CIRCUIT

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Intersil products are sold by description only. Intersil Corporation reser ves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for an y infringements of patents or other rights of third parties which
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5-12