Datasheets HD404829R Datasheet

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Customer Support Dept.
April 1, 2003

Cautions

Keep safety first in your circuit designs!

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Remember to give due consideration to safety when making your circuit designs, with appropriate measu res such as (i)
placement of substitutive, auxiliar y circuits, (ii) use of nonflammable material or (iii) preve n tion ag ain st any malf u nc tio n or
mishap.

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HD404829R Series

AS Microcomputer Incorporating a LCD controller/Driver Circuit

ADE-202-057C

Rev.4

Sept. 1999

Description

The HD404829R series incorporates an 8-bit A/D converter (four channels), a Liquid Crystal Display
(LCD) and a serial interface, and has large-current Input/Output (I/O) pins. The series is a 4-bit single-chip
microcomputer best used in the AV equipment such as CD radio cassette tape recorders which require the
LCD display control.

The HD404829R Series, with a 32.768kHz sub-oscillator for clocks, counts up the system clock and a
variety of power modes can reduce power consumption.

The HD4074829 is a ZTATTM microcomputer which incorporates a PROM. System development period
has been dramatically reduced so that the process from debugging to mass production is smooth. (The
PROM programming specifications are the same as those for Type 27256.)

ZTATTM: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.

Features

• 1,876-digit × 4-bit RAM

• 44 I/O pins, including 10 high-current pins (15 mA, max.) and 20 pins multiplexed with LCD segment

pins

• Four timer/counters

• 8-bit input capture circuit

• Three timer outputs (including two PWM out-puts)

• Two event counter inputs (including one double-edge function)

• Clock-synchronous 8-bit serial interface

• A/D converter (4 channels × 8 bits)

• LCD controller/driver (52 segments × 4 commons)

• Built-in oscillators
 Main clock: 4.2-MHz ceramic (an external clock is also possible)
 Subclock: 32.768-kHz crystal

• Eleven interrupt sources
 Five by external sources, including three double-edge functions

HD404829R Series

 Six by internal sources

• Subroutine stack up to 16 levels, including interrupts

• Four low-power dissipation modes
 Subactive mode
 Standby mode
 Watch mode
 Stop mode

• One external input for transition from stop mode to active mode

• Instruction cycle time (min.): 0.95 µs (f

• Operation voltage

VCC = 2.7 V to 6.0 V (HD404829R)
VCC = 2.7 V to 5.5 V (HD4074829)

• Two operating modes
 MCU mode
 MCU/PROM mode (HD4074829 only)

= 4.2 MHz)

OSC

2

HD404829R Series

Ordering Information

Type Product Name Model Name ROM (Words) Package

Mask ROM HD404828R HD404828RH 8,192 100-pin plastic QFP

(FP-100B)

HD404828RFS 100-pin plastic QFP

(FP-100A)

HD404828RTF 100-pin plastic TQFP

(TFP-100B)

HD4048212R HD4048212RH 12,288 100-pin plastic QFP

(FP-100B)

HD4048212RFS 100-pin plastic QFP

(FP-100A)

HD4048212RTF 100-pin plastic TQFP

(TFP-100B)

HD404829R HD404829RH 16,384 100-pin plastic QFP

(FP-100B)

HD404829RFS 100-pin plastic QFP

(FP-100A)

HD404829RTF 100-pin plastic TQFP

(TFP-100B)

TM

ZTAT

HD4074829 HD4074829H 16,384 100-pin plastic QFP

(FP-100B)

HD4074829FS 100-pin plastic QFP

(FP-100A)

HD4074829TF 100-pin plastic TQFP

(TFP-100B)

Caution about operation!

It has been confirmed that the HD404829R Series, same as the ZTATTM version HD4074829 and the
conventional HD404829 Series, satisfies the electrical properties given on the data sheets, etc. However,
effective values of the electrical properties, the operating margin, and the noise margin may differ with the
manufacturing processes, on-chip ROM, and layout patterns. Therefore, conduct an evaluation test of your
system using the ZTATTM version and the mask ROM version. Also conduct a similar evaluation test for
checkup before replacing your conventional product with the HD404829R Series.

3

HD404829R Series

List of Functions

Product name HD404828R HD4048212R HD404829R HD4074829

ROM (Words) 8,192 12,288 16,384 16,384PROM
RAM (Digits) 1,876
I/O 44 (max)

Large-current I/O pins 10 (Sink 15 mA max)
LCD segment multiplexed pins 20

Timer / Counter 4

Input capture 8 bit × 1
Timer output 3 (PWM output possible for 2)

Event input 2 (edge selection possible for 1)
Serial interface 1 (8-bit syncronous)
A/D converter 8 bit × 4 channels
LCD controller / driver circuit Max. 52 seg × 4 com
Interrupts External 5 (edge selection possible for 3)

Internal 6

Low-Power Dissipation Mode 4

Stop mode O

Watch mode O

Standby mode O

Subactive mode O
Main Oscillator Ceramic oscillation O (0.4–4.2MHz)

Crystal oscillation O (0.4–4.2MHz) —
Sub oscillator Crystal oscillation O (32.768 kHz)
Minimum instruction execution time 0.95 µs (f
Operating voltage (V) 2.7 to 6.0 2.7 to 5.5
Package 100-pin plastic QFP (FP-100B)

100-pin plastic QFP (FP-100A)

100-pin plastic TQFP (TFP-100B)

Guaranteed operation temperature
(˚C)

= 4.2 MHz)

OSC

–20 to +75

4

Pin Arrangement

NUMG

NUMO

CC32

NUMOVVVV

1

COM4

COM3

COM2

COM1

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

HD404829R Series

SEG42

SEG41

SEG40

SEG39

AV

CC

AN
AN
AN
AN

AV

TEST
OSC
OSC

RESET

X1
X2

GND

D
D
D
D
D
D
D
D
D
D

D /STOPC

10

D /INT

11 0

999897

100

1
2

0

3

1

4

2

5

3

6

SS

7
8

1

9

2

10
11
12
13
14

0

15

1

16

2

17

3

18

4

19

5

20

6

21

7

22

8

23

9

24
25

26

27

123

012

R0 /INT

R0 /INT

95949392919089888786858483828180797877

96

FP-100B

TFP-100B

28

29

30

31

32

33

34 3536

37

38

39

40

41

42

4

3

012

R0 /INT

R0 /INT

R1 /TOB

R1 /TOC

R1 /TOD

1

R2 /SI

3

0

R2 /SCK

R1 /EVNB

R2 /EVND

2

3

012301230

R2 /SO

R3 /SEG1

R3 /SEG2

R3 /SEG3

R3 /SEG4

R4 /SEG5

43

44 4546

R4 /SEG6

R4 /SEG7

R4 /SEG8

R5 /SEG9

76

47

48

49

50

123

R5 /SEG10

R5 /SEG11

R5 /SEG12

R6 /SEG13

SEG38

75

SEG37

74

SEG36

73

SEG35

72

SEG34

71

SEG33

70

SEG32

69

SEG31

68

SEG30

67

SEG29

66

SEG28

65

SEG27

64

SEG26

63

SEG25

62

SEG24

61

SEG23

60

SEG22

59

SEG21

58

R7 /SEG20

57
56
55
54
53
52
51

0

3

R7 /SEG19

2

R7 /SEG18

1

R7 /SEG17

0

R6 /SEG16

3

R6 /SEG15

2

R6 /SEG14

1

Top view

5

HD404829R Series

Pin Arrangement

NUMO
NUMG

AV

CC

AN

0

AN

1

AN

2

AN

3

AV

SS

TEST

OSC

1

OSC

2

RESET

X1
X2

GND

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

10

D /INT

11

R0 /INT

0

R0 /INT

1

R0 /INT

2

9

0
1
2
3

D /STOPC

CC32

NUMOVVVV

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31323334353637383940414243444546474849

1

COM4

COM3

COM2

COM1

SEG52

SEG51

SEG50

SEG49

99989796959493929190898887868584838281

FP-100A

SEG48

SEG47

SEG46

SEG45

SEG44

SEG43

SEG42

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
R7 /SEG20

3

R7 /SEG19

2

R7 /SEG18

1

R7 /SEG17

0

R6 /SEG16

3

R6 /SEG15

2

R6 /SEG14

1

R6 /SEG13

0

R5 /SEG12

3

43

012

R1 /TOB

R1 /TOC

R0 /INT

R1 /TOD

1

R2 /SI

0

3

R2 /SCK

R1 /EVNB

R2 /EVND

2

3

012301230

R2 /SO

R3 /SEG1

R3 /SEG2

R3 /SEG3

R3 /SEG4

R4 /SEG5

R4 /SEG6

R4 /SEG7

R4 /SEG8

1

2

R5 /SEG9

R5 /SEG10

R5 /SEG11

Top view

6

HD404829R Series

Pin Description

Pin Number

FP-100B

Item Symbol

Power V
supply

CC

GND 13 15 Connected to ground
Test TEST 7 9 I Used for factory testing only: Connect this pin to V
Reset RESET 10 12 I Resets the MCU
Oscillator OSC

OSC

1

2

X1 11 13 I Used for a 32.768-kHz crystal for clock purposes.

X2 12 14 O If not to be used, fix the X1 pin to VCC and leave

Port D0–D

9

D10, D

R00–R7

11

3

Interrupt INT0, INT1,

INT2–INT

4

Stop clear STOPC 24 26 I Input pin for transition from stop mode to active

Serial SCK 35 37 I/O Serial interface clock input/output pin
interface

SI 36 38 I Serial interface receive data input pin

SO 37 39 O Serial interface transmit data output pin
Timer TOB, TOC,

TOD

EVNB, EVND 33, 34 35, 36 I Event count input pins
LCD V1, V2, V

3

COM1–COM4 90–93 92–95 O Common signal pins for LCD

SEG1–SEG52 38–89 40–91 O Segment signal pins for LCD

TFP-100B FP-100A I/O Function

97 99 Applies power voltage

8 10 I Input/output pins for the internal oscillator circuit:
9 11 O Connect them to a ceramic oscillator ,crystal

oscillator or connect OSC1 to an external oscillator
curcuit

the X2 pin open.

14–23 16–25 I/O Input/output pins addressed by individual bits; pins

D0–D9 are high-current pins that can each supply up

to 15 mA
24, 25 26, 27 I Input pins addressable by individual bits
26–57 28–59 I/O Input/output pins addressable in 4-bit units
25–29 27–31 I Input pins for external interrupts

mode

30–32 32–34 O Timer output pins

94–96 96–98 Power pins for LCD controller/driver; may be left

open during operation since they are connected by

internal voltage division resistors.

Voltage conditions are: VCC ≥ V1 ≥ V2 ≥ V3 ≥ GND

CC

7

HD404829R Series

Pin Number

FP-100B

Item Symbol

A/D

AV

CC

converter

AV

SS

AN0–AN
NUMG NUMG 100 2 These are not pins for user applications. Connect
NUMO NUMO 98,99 100,1 NUMG to the same potential as GND. Leave NUMO

TFP-100B FP-100A I/O Function

1 3 Power pin for A/D converter: Connect it to the same

potential as VCC, as physically close to the VCC pin as
possible

6 8 Ground for AVCC: Connect it to the same potential

as GND, as physically close to the GND pin as
possible

2–5 4–7 I Analog input pins for A/D converter

3

.

open

8

Block Diagram

RESET

TEST

STOPCOSC1OSC2X1X2VCCGND

HD404829R Series

INT

0

INT

1

INT

2

INT

3

INT

4

EVNB

TOB

TOC

EVND
TOD

SCK

SI
SO

AV

cc

AV

ss

AN

0

AN

1

AN

2

AN

3

V

1

V

2

V

3

COM1
COM2
COM3
COM4
SEG1
SEG2
SEG3

~

SEG52

HMCS400 CPU

ROM

External interrupt

control circuit

Timer A

8-bit free-running timer

8-bit free-running / reload timer

8-bit free-running / reload timer

Timer B

Timer C

Timer D

8-bit free-running / reload timer

Clock-synchronous

8-bit serial interface

A/D converter

4 channels x 8 bits

LCD controller / driver

52 segments x 4 commons

RAM

circuit

D Port

R0 Port

R1 Port

R2 Port

R4 Port R3 Port

R5 Port

R6 Port

R7 Port

D

0

D

1

D

2

D

3

D

4

D

5

D

6

D

7

D

8

D

9

D

10

D

11

R0

0

R0

1

R0

2

R0

3

R1

0

R1

1

R1

2

R1

3

R2

0

R2

1

R2

2

R2

3

R3

0

R3

1

R3

2

R3

3

R4

0

R4

1

R4

2

R4

3

R5

0

R5

1

R5

2

R5

3

R6

0

R6

1

R6

2

R6

3

R7

0

R7

1

R7

2

R7

3

~

: High current pins

9

HD404829R Series

Memory Map

ROM Memory Map

The ROM memory map is shown in figure 1 and described below.

ROM address ROM address

$0000

$000F
$0010

$003F
$0040

$0FFF
$1000

$1FFF
$2000

$2FFF
$3000

$3FFF

Vector address

Zero-page subroutine

(64 words)

Pattern

(4096 words)

HD404828R

Program

(8,192 words)

HD4048212R

Program

(12,288 words)

HD404829R, HD4074829

Program

(16,384 words)

$0000
$0001

$0002
$0003

$0004
$0005

$0006
$0007
$0008
$0009

$000A
$000B

$000C
$000D

$000E
$000F

(jump to RESET, STOPC routine)

JMPL instruction

JMPL instruction

(jump to INT routine)

JMPL instruction

(jump to INT routine)

JMPL instruction

(jump to timer A routine)

JMPL instruction

(jump to timer B, INT routine)

JMPL instruction

(jump to timer C, INT routine)

JMPL instruction

(jump to timer D, INT routine)

JMPL instruction

(jump to A/D, serial routine)

0

1

2

3

4

Figure 1 ROM Memory Map

Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses

of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.

Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.

Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.
Program Area ($0000–$1FFF: HD404828R; $0000–$2FFF: HD4048212R; $0000–$3FFF;

HD404829R, HD4074829): Used for program coding.

10

HD404829R Series

RAM Memory Map

The MCU contains a 1,876-digit × 4-bit RAM area consisting of a memory register area, an LCD data area,
a data area, and a stack area. In addition, an interrupt control bits area, special register area, and register
flag area are mapped onto the same RAM memory space as a RAM-mapped register area outside the above
areas. The RAM memory map is shown in figure 2 and described below.

RAM-Mapped Register Area ($000–$03F):

• Interrupt Control Bits Area ($000–$003)
This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit

manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.

• Special Function Register Area ($004–$01F, $024–$03F)
This area is used as mode registers and data registers for external interrupts, serial interface,

timer/counters, LCD, A/D converter, and as data control registers for I/O ports. The structure is shown
in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and
read/write (R/W). The SEM, SEMD, REM, and REMD instructions can be used for the LCD control
register (LCR: $01B), but RAM bit manipulation instructions cannot be used for other registers.

• Register Flag Area ($020–$023)

This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).
These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and
TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using
the instructions are shown in figure 4.

11

HD404829R Series

RAM address RAM address

$000

$040

Memory registers (16 digits)

$050

LCD display area (52 digits)

$084
$090

$260

$3C0

$3FF

$090

Data

(464 digits)

V = 0

(bank = 0)

$25F

Notes: 1.

The data area has three banks:
bank 0 (V = 0) to bank 2 (V = 2).

2.

Two registers are mapped
on the same area.

R:
W:
R/W:

RAM-mapped registers

Not used

Data
V = 1

(bank = 1)

×

Data (464 digits 3)
V = 0 (bank 0)
V = 1 (bank 1)
V = 2 (bank 2)

Data (352 digits)

Stack (64 digits)

(464 digits)

Read only
Write only
Read/write

*1

Data

(464 digits)

V = 2

(bank = 2)

$000
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$010
$011
$012
$013
$014
$015
$016
$017
$018

$01B
$01C
$01D
$01E
$01F
$020
$023
$024
$025
$026
$027
$028
$029
$02A

$02B
$02C
$02D

$02E
$02F
$030
$031
$032
$033
$034
$035
$036
$037
$038
$03E
$03F

Interrupt control bits area

Port mode register A (PMRA)
Serial mode register A (SMRA)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A (TMA)
Timer mode register B1 (TMB1)

Timer B (TRBL/TWBL)

(TRBU/TWBU)
Miscellaneous register (MIS)
Timer mode register C1 (TMC1)
Timer C (TRCL/TWCL)

(TRCU/TWCU)
Timer mode register D1 (TMD1)
Timer D (TRDL/TWDL)

(TRDU/TWDU)
Timer mode register B2 (TMB2)
Timer mode register C2 (TMC2)

Timer mode register D2 (TMD2)
A/D mode register (AMR)
A/D data register lower (ADRL)
A/D data register upper (ADRU)

Not used

LCD control register (LCR)
LCD mode register (LMR)
LCD output register 1 (LOR1)
LCD output register 2 (LOR2)
LCD output register 3 (LOR3)

Register flag area

Port mode register B (PMRB)
Port mode register C (PMRC)

Detection edge select register 1 (ESR1)
Detection edge select register 2 (ESR2)

Serial mode register B (SMRB)
System clock select register (SSR)

Not used

Port D
Port D
Port D

Port R0 DCR (DCR0)
Port R1 DCR (DCR1)
Port R2 DCR (DCR2)
Port R3 DCR (DCR3)
Port R4 DCR (DCR4)
Port R5 DCR (DCR5)
Port R6 DCR (DCR6)
Port R7 DCR (DCR7)

V register (V)

DCR (DCD0)

0–D3

DCR (DCD1)

4–D7

and D9 DCR (DCD2)

8

Not used

Not used

W

W
R/W
R/W

W

W
R/W
R/W

W

W
R/W
R/W

W
R/W
R/W
R/W
R/W
R/W

W

R

R

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

R/W

*2

12

Timer read register B lower (TRBL)

10

Timer read register B upper (TRBU)

11
14

Timer read register C lower (TRCL)

15

Timer read register C upper (TRCU)

Timer read register D lower (TRDL)

17
18

Timer read register D upper (TRDU)

Figure 2 RAM Memory Map

Timer write register B lower (TWBL)

R
R

Timer write register B upper (TWBU)

R

Timer write register C lower (TWCL)

R

Timer write register C upper (TWCU)

R

Timer write register D lower (TWDL)

Timer write register D upper (TWDU)

R

$00A

W

$00B

W

$00E

W

$00F

W

$011

W
W

$012

HD404829R Series

RAM address

$000

$001

$002

$003

$020

$021

$022

$023

Bit 3

IM0

(IM of INT

(IM of timer A)

(IM of timer C)

(IM of A/D)

(Direct transfer

(RAM enable

(IM of

(IM of serial

interface)

IMTA

IMTC

IMAD

Bit 3

DTON

on flag)

RAME

flag)

IM3

INT

IMS

0

3

)

)

Bit 2 Bit 1

IF0

(IF of INT

(IF of timer A)

(IF of timer C)

(IF of A/D)

(A/D start flag)

Not used

(IF of INT

(IF of serial

interface)

)

0

IFTA

IFTC

IFAD

Interrupt control bits area

Bit 2 Bit 1

ADSF

IF3

)

3

IFS

Register flag area

RSP

(Reset SP bit)

IM1

(IM of INT

(IM of timer B)

(IM of timer D)

(Watchdog

(Input capture

(IM of INT2)

(IM of

IMTB

IMTD

WDON
on flag)

ICEF

error flag)

IM2

IM4

INT

1

4

)

)

Bit 0

IE

(Interrupt

enable flag)

IF1

(IF of INT1)

IFTB

(IF of timer B)

IFTD

(IF of timer D)

Bit 0

LSON

(Low speed

on flag)

ICSF

(Input capture

status flag)

IF2

(IF of INT2)

IF4

(IF of INT4)

Interrupt request flag

IF:

Interrupt mask

IM:

Interrupt enable flag

IE:

Stack pointer

SP:

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

SEM/SEMD REM/REMD TM/TMD

IE
IM

Allowed Allowed Allowed

LSON

IF
ICSF
ICEF

Not executed Allowed Allowed

RAME

RSP

WDON

ADSF

DTON

Not used

Not executed Allowed Inhibited

Allowed Not executed Inhibited
Allowed Inhibited Allowed

Not executed in active mode

Used in subactive mode

Allowed Allowed

Not executed Not executed Inhibited

Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.

The REM or REMD instuction must not be executed for ADSF during A/D conversion.
DTON is always reset in active mode.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

13

HD404829R Series

$000

$003
PMRA $004
SMRA $005

SRL $006
SRU $007
TMA $008

TMB1 $009

TRBL/TWBL $00A

TRBU/TWBU $00B

MIS $00C

TMC1 $00D

TRCL/TWCL $00E

TRCU/TWCU $00F

TMD1 $010

TRDL/TWDL $011

TRDU/TWDU $012

TMB2 $013
TMC2 $014
TMD2 $015

AMR $016

ADRL $017

ADRU $018

LCR $01B

LMR $01C
LOR1 $01D
LOR2 $01E

LOR3 $01F

$020

$023
PMRB $024
PMRC $025

ESR1 $026
ESR2 $027

SMRB $028

SSR $029

DCD0 $02C
DCD1 $02D

DCD2 $02E

DCR0 $030
DCR1 $031
DCR2 $032
DCR3 $033
DCR4 $034
DCR5 $035
DCR6 $036
DCR7 $037

V $03F

Bit 3 Bit 2 Bit 1

Bit 0

Interrupt control bits area

Not used Not used R2

R21/SCK

Serial transmit clock speed selection

/SI R23/SO

2

Serial data register (lower digit)

Serial data register (upper digit)

*

1

*

2

Clock source setting (timer A)
Clock source setting (timer B)

Timer B register (lower digit)

Timer B register (upper digit)

*

3

*

2

R23/SO PMOS control

Interrupt frame period selection

Clock source setting (timer C)

Timer C register (lower digit)

Timer C register (upper digit)

*

2

Clock source setting (timer D)

Timer D register (lower digit)

Timer D register (upper digit)

Not used Not used Timer-B output mode selection

Not used

*

4

Analog channel selection

Timer-C output mode setting
Timer-D output mode setting

Not used
A/D data register (lower digit)
A/D data register (upper digit)

Not used

Not used

*

6

*

7

*

LCD duty cycle selectionLCD input clock source selection

R3

/SEG4

3

/SEG8

R4

3

Not used

R3

/SEG3

2

/SEG7

R4

2

R7/SEG17–20

R31/SEG2
R4

/SEG6

1

R6/SEG13–16

R30/SEG1
R4

/SEG5

0

R5/SEG9–12

Register flag area

R0

4

0

/INT

2

D10/STOPC

R03/INT

D11/INT

detection edge selection

INT

3

EVND detection edge selection

Not used Not used

*

11

*

12

R0

/INT

1

3

R20/EVND

INT

detection edge selection

2

INT

detection edge selection

4

*

9

*

13

2

R00/INT

R13/EVNB

*

Not used

Not used

DCR

3

DCR

7

DCR

3

DCR

3

DCR

3

DCR

3

DCR

3

DCR

3

DCR

3

DCR

3

Port D
Port D

Not used

Port R0
Port R1
Port R2
Port R3
Port R4
Port R5
Port R6
Port R7

2

DCR

6

DCR

2

DCR

2

DCR

2

DCR

2

DCR

2

DCR

2

DCR

2

DCR

2

Port D
Port D
Port D

Not used

Port R0
Port R1
Port R2
Port R3
Port R4
Port R5
Port R6
Port R7

DCR

1

DCR

5

DCR

9

DCR

1

DCR

1

DCR

1

DCR

1

DCR

1

DCR

1

DCR

1

DCR

1

Port D
Port D
Port D

Port R0
Port R1
Port R2
Port R3
Port R4
Port R5
Port R6
Port R7

Port D
Port D

Not used

Port R0
Port R1
Port R2
Port R3
Port R4
Port R5
Port R6
Port R7

DCR

Not used

Not used Not used Bank 0 to bank 2 selection

*

5

8

10

DCR

0

DCR

4

DCR

8

0
0
0
0
0
0
0
0

1

DCR
DCR
DCR
DCR
DCR
DCR
DCR
DCR

Notes:

Timer-A/time-base

1.
Auto-reload on/off

2.
Pull-up MOS control

3.
Input capture selection

4.
A/D conversion time

5.
Display on/off in watch mode

6.
LCD power switch

7.
LCD display on/off

8.
SO idle H/L setting

9.
Transmit clock source selection

10.
32-kHz oscillation stop setting

11.
32-kHz oscillation division ratio

12.
System clock selection

13.

14

Figure 5 Special Function Register Area

HD404829R Series

Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be

accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.

Memory registers
$040
$041

$042
$043
$044
$045
$046
$047
$048
$049

$04A
$04B
$04C
$04D
$04E
$04F

MR(0)
MR(1)
MR(2)
MR(3)

MR(4)
MR(5)

MR(6)
MR(7)

MR(8)
MR(9)
MR(10)
MR(11)
MR(12)
MR(13)
MR(14)
MR(15)

PC –PC :

13

ST: Status flag

Program counter

0

CA: Carry flag

Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position

Stack area

960 $3C0

Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2

1023

Level 1

$3FF

$3FC
$3FD
$3FE
$3FF

Bit 3 Bit 2 Bit 1 Bit 0

ST
PC
CA
PC

PC
PC

10

PC
PC

3

PC

13

PC

9

PC

6

PC

2

PC

12

PC

8

PC

5

PC

1

11

7

4

0

15

HD404829R Series

LCD Data Area ($050–$083): Used for storing 52-digit LCD data which is automatically output to LCD

segments as display data. Data 1 lights the corresponding LCD segment; data 0 extinguishes it. Refer to
the LCD description for details.

Data Area ($090–$3BF): 464 digits from $090 to $25F have three banks, which can be selected by setting
the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure

7). The area from $260 to $3BF is accessed without setting the bank register.

Bank register (V: $03F)

Bit
Initial value
Read/Write
Bit name

V1

0

1

Note: After reset, the value in the bank register is 0, and therefore bank 0 is

selected. If V1 = 1 and V0 = 1, no bank is selected, and the operation is not
guaranteed.

3
—
—

Not used

V0

0
1
0
1

2
—
—

Not used

Bank area selection

Bank 0 is selected
Bank 1 is selected
Bank 2 is selected
Not used

1
0

R/W

V1

0
0

R/W

V0

Figure 7 Bank Register (V)

Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and

carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.

The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.

16

HD404829R Series

Functional Description

Registers and Flags

The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described
below.

30

Accumulator

B register

W register

X register

Y register

SPX register

Initial value: Undefined, R/W

Initial value: Undefined, R/W

Initial value: Undefined, R/W

Initial value: Undefined, R/W

Initial value: Undefined, R/W

Initial value: Undefined, R/W

(A)

30

(B)

0

1

(W)

30

(X)

30

(Y)

30

(SPX)

30

SPY register

Carry

Status

Program counter
Initial value: $0000,
R/W not possible

Stack pointer
Initial value: $3FF, R/W not possible

Initial value: Undefined, R/W

Initial value: Undefined, R/W

Initial value: 1, R/W not possible

13

95

1111

(SPY)

0

(CA)

0

(ST)

0

(PC)

0

(SP)

Figure 8 Registers and Flags

Accumulator (A) and B Register (B)

A and B are 4-bit registers, and are used to hold the results of ALU(arithmetic and logical unit) operations
and to transfer data between memory, I/O ports, and other registers.

W Register (W), X Register (X), Y Register (Y)

W is a 2-bit register and X and Y are 4-bit registers. These registers are used in RAM register indirect
addressing. The Y register is also used in D port addressing.

17

HD404829R Series

SPX Register (SPX) and SPY Register (SPY)

The SPX and SPY registers are 4-bit registers used to supplement the X and Y registers.

Carry Flag (CA)

CA is a 1-bit flag that stores ALU overflow generated by an arithmetic operation. CA is set to 1 when an
overflow is generated, and is cleared to 0 after operations in which no overflow occurred. CA is also
affected by the carry set/carry clear instructions (SEC and REC), and by the rotate with carry instructions
(ROTL and ROTR.)

During interrupt handling, CA is saved on the stack, and is restored from the stack by the RTNI instruction.

Status Flag (ST)

ST is a 1-bit flag that stores the results of arithmetic instructions, compare instructions, and bit test
instructions, and is used as the branch condition for the BR, BRL, CAL, and CALL conditional branch
instructions.

The contents of the ST flag are held until the next arithmetic, compare, bit test, or conditional branch
instruction is executed. After the execution of a conditional branch instruction, the value of ST is set to 1
without regard to the condition.

During interrupt handling, ST is saved on the stack, and is restored from the stack by the RTNI instruction.

Program Counter (PC)

The PC is a 14-bit counter that indicates the ROM address of the next instruction the CPU will execute.

Stack Pointer (SP)

The SP is a 10-bit register that indicates the RAM address of the next stack frame in the stack area.
The SP is initialized to $3FF by a reset. The SP is decremented by 4 by a subroutine call or by interrupt

handling, and is incremented by 4 when the saved data has been restored by a return instruction.
The upper 4 bits of the SP are fixed at 1111; the maximum number of stack levels is thus 16.
In addition to the reset method described above, the SP can also be initialized to $3FF by clearing the reset

stack pointer (RSP) in the interrupt control bits area with a RAM bit manipulation instruction, i.e., REM or
REMD.

Reset

The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is
cancelled, RESET must be high for at least one t
RESET must be high for at least two instruction cycles.

to enable the oscillator to stabilize. During operation,

R C

Initial values after MCU reset are listed in table 1.

18

HD404829R Series

Table 1 Initial Values After MCU Reset

Initial

Item Abbr.

Program
counter

Status flag (ST) 1 Enables conditional branching
Stack pointer (SP) $3FF Stack level 0
Interrupt Interrupt enable flag (IE) 0 Inhibits all interrupts

flags/mask

I/O Port data register (PDR) All bits 1 Enables output at level 1

Timer/ Timer mode register A (TMA) 0000 Refer to description of timer mode register A
counters, Timer mode register B1 (TMB1) 0000 Refer to description of timer mode register B1
serial Timer mode register B2 (TMB2) - - 00 Refer to description of timer mode register B2
interface Timer mode register C1 (TMC1) 0000 Refer to description of timer mode register C1

Interrupt request flag (IF) 0 Indicates there is no interrupt request
Interrupt mask (IM) 1 Prevents (masks) interrupt requests

Data control register (DCD0,

Port mode register A (PMRA) - - 00 Refer to description of port mode register A
Port mode register B (PMRB) 0000 Refer to description of port mode register B
Port mode register C

bits 3, 1, 0

Detection edge select
register 1

Detection edge select
register 2

Timer mode register C2 (TMC2) - 000 Refer to description of timer mode register C2
Timer mode register D1 (TMD1) 0000 Refer to description of timer mode register D1
Timer mode register D2 (TMD2) 0000 Refer to description of timer mode register D2
Serial mode register A (SMRA) 0000 Refer to description of serial mode register A
Serial mode register B (SMRB) - - x0 Refer to description of serial mode register B
Prescaler S (PSS) $000 —
Prescaler W (PSW) $00 —
Timer counter A (TCA) $00 —
Timer counter B (TCB) $00 —
Timer counter C (TCC) $00 —
Timer counter D (TCD) $00 —

(PC) $0000 Indicates program execution point from start

DCD1)
(DCD2) - - 00
(DCR0,

–DCR7)

(PMRC3,
PMRC1,
PMRC0)

(ESR1) 0000 Disables edge detection

(ESR2) 0000 Disables edge detection

Value Contents

address of ROM area

All bits 0 Turns output buffer off (to high impedance)

All bits 0

000 Refer to description of port mode register C

19

HD404829R Series

Table 1 Initial Values After MCU Reset (cont)

Initial

Item Abbr.

Timer/
counters,

serial
interface

A/D A/D mode register (AMR) 00 - 0 Refer to description of A/D mode register

LCD LCD control register (LCR) - 000 Refer to description of LCD control register

Bit registers Low speed on flag (LSON) 0 Refer to description of operating modes

Others Miscellaneous register (MIS) 0000 Refer to description of operating modes, I/O, and

Timer write register B (TWBU,

TWBL)

Timer write register C (TWCU,

TWCL)

Timer write register D (TWDU,

TWDL)

Octal counter (OC) 000 —

A/D data register (ADRL,

ADRU)

LCD mode register (LMR) 0000 Refer to description of LCD duty-cycle/clock

LCD output register 1 (LOR1) 0000 Sets R-port/LCD segment pins to R port mode
LCD output register 2 (LOR2) 0000
LCD output register 3 (LOR3) - 000

Watchdog timer on flag (WDON) 0 Refer to description of timer C
A/D start flag (ADSF) 0 Refer to description of A/D converter
Direct transfer on flag (DTON) 0 Refer to description of operating modes
Input capture status flag (ICSF) 0 Refer to description of timer D
Input capture error flag (ICEF) 0 Refer to description of timer D

System clock select
register bits 2,1

Bank register (V) - - 00 Refer to description of RAM memory map

(SSR2,
SSR1)

Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.

2. X indicates invalid value. – indicates that the bit does not exist.

Value Contents

$X0 —

$X0 —

$X0 —

$80 Refer to description of A/D data register

control register

serial interface

000 Refer to description of operating modes and

oscillation circuits

20

HD404829R Series

Status After Cancel­lation of Stop Mode by

Item Abbr.

Carry flag (CA) Pre-stop-mode values are not guaranteed; Pre-MCU-reset values
Accumulator (A) values must be initialized by program are not guaranteed; val­B register (B) ues must be initialized by
W register (W) program
X/SPX register (X/SPX)
Y/SPY register (Y/SPY)
Serial data register (SRL, SRU)
RAM Pre-stop-mode values are retained
RAM enable flag (RAME) 1 0 0
Port mode

register C bit 2
System clock

select register bit 3

(PMRC2) Pre-stop-mode

(SSR3)

STOPC Input

values are retained

Status After Cancel­lation of Stop Mode by
RESET Input

00

Status After all Other Types
of Reset

Interrupts

The MCU has 11 interrupt sources: five external signals (INT0, INT1, INT2–INT4), four timer/ counters
(timers A, B, C, and D), serial interface, and A/D converter.

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.

Some vector addresses are shared by two different interrupts. They are timer B and INT2, timer C and
INT3, timer D and INT4, and A/D converter and serial interface interrupts. So the type of request that has
occurred must be checked at the beginning of interrupt processing.

Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are
reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag
(IE) and the IF to 0 and the interrupt mask (IM) to 1.

A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 11 interrupt sources are listed in
table 3.

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.

The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in
figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack

21

HD404829R Series

during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.

Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.

Table 2 Vector Addresses and Interrupt Priorities

Reset/Interrupt Priority Vector Address

RESET, STOPC* — $0000

INT

0

INT

1

Timer A 3 $0006
Timer B, INT2 4 $0008
Timer C, INT3 5 $000A
Timer D, INT4 6 $000C
A/D, Serial 7 $000E

Note: * The STOPC interrupt request is valid only in

stop mode.

1 $0002
2 $0004

22

INT0 interrupt

interrupt

INT

1

Timer A interrupt

Timer B interrupt

Timer C interrupt

Timer D interrupt

A/D interrupt

$ 000,0

IE

$ 000,2

IFO

$ 000,3

IMO

$ 001,0

IF1

$ 001,1

IM1

$ 001,2

IFTA

$ 001,3

IMTA

$ 002,0

IFTB

$ 002,1

IMTB

$ 002,2

IFTC

$ 002,3

IMTC

$ 003,0

IFTD

$ 003,1

IMTD

$ 003,2

IFAD

$ 003,3

IMAD

Priority controller

HD404829R Series

Interrupt
request

Vector
address

$ 022,0

IF2

INT

interrupt

2

$ 022,1

IM2

$ 022,2

IF3

INT

interrupt

3

$ 022,3

IM3

$ 023,0

IF4

INT

interrupt

4

$ 023,1

IM4

$ 023,2

Serial interrupt

IFS

$ 023,3

IMS

Note: $m,n is RAM address $m, bit number n.

Figure 9 Interrupt Control Circuit

23

HD404829R Series

Table 3 Interrupt Processing and Activation Conditions

Interrupt Source

Interrupt
Cuntrol Bit INT

Timer B or

0

INT

1

Timer A

INT

2

Timer C or
INT

3

IE 1111 1 1 1
IF0 . IM0 1000 0 0 0
IF1 . IM1 * 100 0 0 0
IFTA . IMTA **10000
IFTB . IMTB

.

IM2

+ IF2
IFTC . IMTC

.

IM3

+ IF3
IFTD . IMTD

.

IM4

+ IF4
IFAD . IMAD

.

IMS

+ IFS

***1000

**** 100

**** * 10

**** * * 1

Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.

Timer D or
INT

4

A/D or
Serial

Instruction cycles

123456

Instruction

execution

Interrupt

acceptance

Note: *

*

Stacking

IE reset

The stack is accessed and the IE reset after the instruction
is executed, even if it is a 2-cycle instruction.

Vector address

generation

Execution of JMPL

instruction at vector address

Figure 10 Interrupt Processing Sequence

Execution of
instruction at

start address

of interrupt

routine

24

Power on

HD404829R Series

RESET = 1?

Yes

Reset MCU

No

Interrupt

request?

No

Execute instruction

←

PC (PC) + 1

←

PC $0002

←

PC $0004

Yes

No

IE = 1?

Accept the interrupt

IE 0
Stack (PC)
Stack (CA)

Stack (ST)

Yes

interrupt?

Yes

interrupt?

INT

INT

Yes

←

←
←
←

0

No

1

←

PC $0006

←

PC $0008

←

PC $000A

←

PC $000C

←

PC $000E

Yes

Yes

Yes

Yes

(A/D, serial interrupt)

Figure 11 Interrupt Processing Flowchart

No

Timer-A

interrupt?

No

Timer-B/INT

interrupt?

No

Timer-C/INT

interrupt?

No

Timer-D/INT

interrupt?

No

2

3

4

25

HD404829R Series

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt

processing and set by the RTNI instruction, as listed in table 4.

Table 4 Interrupt Enable Flag (IE: $000, Bit 0)

Interrupt

IE

0 Disabled
1 Enabled

External Interrupts (INT0, INT1, INT2–INT4): Five external interrupt signals.
External Interrupt Request Flags (IF0–IF4: $000, $001, $022, $023): IF0 and IF1 are set at the falling

edge of signals input to INT0 and INT1, and IF2–IF4 are set at the rising or falling edge of signals input to
INT2–INT4, as listed in table 5. The INT2–INT4 interrupt edges are selected by the detection edge select
registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13.

Table 5 External Interrupt Request Flags (IF0–IF4: $000, $001, $022, $023)

IF0–IF4 Interrupt Request

0No
1 Yes

Enabled/Disabled

Detection edge selection register 1 (ESR1: $026)

Bit
Initial value
Read/Write
Bit name

ESR13

0

1

Note: Both falling and rising edges are detected.

*

ESR13

ESR12

0
1
0
1

3
0

W

2
0

W

ESR12

INT

detection edge

3

No detection
Falling-edge detection
Rising-edge detection
Double-edge detection

1
0

W

ESR11

0
0

W

ESR10

**

Figure 12 Detection Edge Selection Register 1 (ESR1)

ESR11

0

1

ESR10

0
1
0
1

INT

detection edge

2

No detection
Falling-edge detection
Rising-edge detection
Double-edge detection

26

Detection edge selection register 2 (ESR2: $027)

HD404829R Series

Bit
Initial value
Read/Write
Bit name

ESR23

0

1

Note: Both falling and rising edges are detected.

*

ESR23

ESR22

0
1
0
1

3
0

W

2
0

W

ESR22

EVND detection edge

No detection
Falling-edge detection
Rising-edge detection
Double-edge detection

1
0

W

ESR21

0
0

W

ESR20

ESR21

**

ESR20

0

1

0
1
0
1

INT

detection edge

4

No detection
Falling-edge detection
Rising-edge detection
Double-edge detection

Figure 13 Detection Edge Selection Register 2 (ESR2)

External Interrupt Masks (IM0–IM4: $000, $001, $022, $023): Prevent (mask) interrupt requests

caused by the corresponding external interrupt request flags, as listed in table 6.

Table 6 External Interrupt Masks (IM0–IM4: $000, $001, $022, $023)

IM0–IM4 Interrupt Request

0 Enabled
1 Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.

Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)

IFTA–IFTD Interrupt Request

0No
1 Yes

27

HD404829R Series

Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the

timer A interrupt request flag, as listed in table 8.

Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)

IMTA–IMTD Interrupt Request

0 Enabled
1 Disabled (masked)

Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in
table 7.

Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the
timer B interrupt request flag, as listed in table 8.

Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 7.

Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the
timer C interrupt request flag, as listed in table 8.

Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the
rising or falling of signals input to EVND when the input capture function is used, as listed in table 7.

Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the
timer D interrupt request flag, as listed in table 8.

Serial Interrupt Request Flag (IFS: $023, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 9.

Table 9 Serial Interrupt Request Flag (IFS: $023, Bit 2)

IFS Interrupt Request

0No
1 Yes

28

HD404829R Series

Serial Interrupt Mask (IMS: $023, Bit 3): Prevents (masks) an interrupt request caused by the serial

interrupt request flag, as listed in table 10.

Table 10 Serial Interrupt Mask (IMS: $023, Bit 3)

IMS Interrupt Request

0 Enabled
1 Disabled (masked)

A/D Interrupt Request Flag (IFAD: $003, Bit 2): Set at the completion of A/D conversion, as listed in
table 11.

Table 11 A/D Interrupt Request Flag (IFAD: $003, Bit 2)

IFAD Interrupt Request

0No
1 Yes

A/D Interrupt Mask (IMAD: $003, Bit 3): Prevents (masks) an interrupt request caused by the A/D
interrupt request flag, as listed in table 12.

Table 12 A/D Interrupt Mask (IMAD: $003, Bit 3)

IMAD Interrupt Request

0 Enabled
1 Disabled (masked)

29

HD404829R Series

Operating Modes

The MCU has five operating modes as shown in table 13. The operations in each mode are listed in tables
14 and 15. Transitions between operating modes are shown in figure 14.

Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC
and OSC2.

Table 13 Operating Modes and Clock Status

Mode Name

Active Standby Stop Watch Subactive

Activation
method

Status System

oscillator

Subsystem
oscillator

Cancellation
method

RESET
cancellation,
interrupt
request,

STOPC

cancellation
in stop mode,
STOP/SBY
instruction in
subactive mode
(when direct
transfer is
selected)

Operating Operating Stopped Stopped Stopped

Operating *1 Operating *1 Operating *1 Operating *1 Operating *1

RESET input,
STOP/SBY
instruction

SBY
instruction
from active
mode

RESET input,
interrupt
request

STOP
instruction
when
TMA3 = 0

RESET input,
STOPC input
in stop mode

STOP
instruction
when
TMA3 = 1
or SBY
instruction from
subactive mode
(when LSON = 1,
or LSON and
DTON are
both 0)

RESET input,

INT0 or timer A

interrupt
request

AN interrupt
request from
timer A or

INT0 in watch

mode when
LSON = 1

RESET input,
STOP/SBY
instruction

Notes: 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select

register (SSR: $029).

2. Subactive mode is an optional function; specify it on the function option list.

*2

1

30

Table 14 Operations in Low-Power Dissipation Modes

HD404829R Series

Function Stop Mode Watch Mode Standby Mode Subactive Mode

CPU Reset Retained Retained Operating
RAM Retained Retained Retained Operating
Timer A Reset Operating Operating Operating
Timer B Reset Stopped Operating Operating
Timer C Reset Stopped Operating Operating
Timer D Reset Stopped Operating Operating
Serial interface Reset Stopped

*3

Operating Operating
A/D Reset Stopped Operating Stopped
LCD Reset Operating
I/O Reset

*1

Retained Retained Operating

*4

Operating Operating

Notes: 1. Output pins are at high impedance.

2. Subactive mode is an optional function specified on the function option list.

3. Transmission/Reception is activated if a clock is input in external clock mode. However,
interrupts stop.

4. When a 32-kHz clock source is used.

Table 15 I/O Status in Low-Power Dissipation Modes

*2

Standby Mode,
Watch Mode Stop Mode

D0–D
D10–D

9

11

Retained High impedance Input enabled
— — Input enabled

R0–R7 Retained or output

of peripheral functions

Output Input

Active Mode,
Subactive Mode

High impedance Input enabled

31

HD404829R Series

Standby mode

:

CPU
CLK
PER

:

:

:

:

Oscillate
Oscillate
Stop
f

cyc

f

cyc

f

OSC

f

X

ø
ø
ø

SBY

Interrupt

Reset by

RESET input or

by watchdog timer

RAME = 0 RAME = 1

RESET1 RESET2

Active
mode

OSC

:

X

CPU
CLK
PER

:

:
:
:

Oscillate
Oscillate
f

cyc

f

cyc

f

cyc

(TMA3 = 0)

f
f

ø
ø
ø

STOPC

STOPC

STOP

STOP

Stop mode

(TMA3 = 0, SSR3 = 0)

:

CPU
CLK
PER

:

CPU
CLK
PER

:

:

:

:

:

:

:

:

Stop
Oscillate
Stop
Stop
Stop

Stop
Stop
Stop
Stop
Stop

f

OSC

f

X

ø
ø
ø

(TMA3 = 0, SSR3 = 1)

f

OSC

f

X

ø
ø
ø

Watch mode

f

:

OSC

f

:

X

f

:

cyc

f

:

SUB

f

:

W

ø

CPU

ø

CLK

ø

PER

LSON:
DTON:

:

CPU
CLK
PER

:

:

:

:

Oscillate
Oscillate
Stop
f

W

f

cyc

f

OSC

f

X

ø
ø
ø

Main oscillation frequency
Suboscillation frequency
for time-base
f

/4

OSC

f

/8 or fX/4

X

(software selectable)
f

/8

X

CPU operating clock

:

Timer A operating clock

:

Clock for peripheral functions

:

(except timer A)
Low speed on flag
Direct transfer on flag

(TMA3 = 1) (TMA3 = 1, LSON = 0)

SBY

Interrupt

f
f

ø
ø
ø

OSC

:

X

CPU
CLK
PER

:

:
:
:

Oscillate
Oscillate
f

cyc

f

W

f

cyc

*2

Subactive
mode

f
f

ø
ø
ø

Notes:

Stop

:

OSC

Oscillate

:

X

f

:

CPU
CLK
PER

SUB

:

f

W

:

f

SUB

1. Interrupt source

2. STOP/SBY (DTON = 1, LSON = 0)

3. STOP/SBY (DTON = 0, LSON = 0)

4. STOP/SBY (DTON = Don’t care, LSON = 1)

Figure 14 MCU Status Transitions

STOP

INT

,

0

timer A

*4

INT

,

0

timer A

*

1

*3

STOP

*1

f

OSC

f

X

ø
ø
ø

(TMA3 = 1, LSON = 1)

f

OSC

f

X

ø
ø
ø

:

CPU
CLK
PER

:

CPU
CLK
PER

:

:

:

:

:

:

:

:

Stop
Oscillate
Stop
f

W

Stop

Stop
Oscillate
Stop
f

W

Stop

32

HD404829R Series

Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction

execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.

The MCU enters standby mode when the SBY instruction is executed in active mode.
Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input,

the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of
operation in standby mode is shown in figure 15.

Standby mode

RESET = 1?

Yes

RAME = 0

System clock

oscillator started

System reset

No

IF0 • IM0 = 1?

Yes

No

STOPC = 0?

RAME = 1

Stop mode

No

Yes

RESET = 1?

Yes

Notes: 1. Only when clearing from standby mode

2. IFAD • IMAD + IFS • IMS = 1

Watch mode

No

IF1 • IM1 = 1?

No

*1

Yes

IFTA • IMTA

Next instruction

execution

= 1?

Yes

No

IFTB •

IMTB + IF2 •

IM2 = 1?

No

No

*1

IFTC •

Yes

IMTC + IF3 •

IM3 = 1?

Next instruction

execution

IF = 1,
IM = 0,
IE = 1?

Yes

Interrupts

enabled

Yes

*1

No

IFTD •

IMTD + IF4 •

IM4 = 1?

*1

Yes

System clock

oscillator started

No

No

*2

*1

Yes

Figure 15 MCU Operation Flowchart

33

HD404829R Series

Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power

dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops. For the X1 and X2
oscillator to operate or stop can be selected by setting bit 3 of the system clock select register (SSR: $029;
operating: SSR3 = 0, stop: SSR3 = 1) (figure 27). The MCU enters stop mode if the STOP instruction is
executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure

44).
Stop mode is terminated by a RESET input or a STOPC input as shown in figure 16. RESET or STOPC

must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When
the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,
but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.

Stop mode

Oscillator
Internal

clock

RESET
STOPC

t

res

STOP instruction execution

(at least equal to oscillator stabilization time t

RC

)

Figure 16 Timing of Stop Mode Cancellation

Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator and the LCD

function operate, but other function operations stop. Therefore, the power dissipation in this mode is the
second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the
OSC1 and OSC2 oscillator stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if
the STOP instruction is executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is
executed in subactive mode.

Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET
input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU
enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated,
the time required to enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T +
tRC) for an INT0 interrupt, as shown in figures 17 and 18.

Operation during mode transition is the same as that at standby mode cancellation (figure 15).

34

HD404829R Series

Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by

the X1 and X2 oscillator. In this mode, functions except the A/D conversion operate. However, because
the operating clock is slow, the power dissipation becomes low, next to watch mode.

The CPU instruction execution speed can be selected as 244 µs or 122 µs by setting bit 2 (SSR2) of the
system clock select register (SSR: $029). Note that the SSR2 value must be changed in active mode. If the
value is changed in subactive mode, the MCU may malfunction.

When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active
mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on
flag (DTON: $020, bit 3).

Subactive mode is an optional function that the user must specify on the function option list.
Interrupt Frame: In watch and subactive modes, φ

is applied to timer A and the INT

CLK

Icircuit.

0

Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame.
Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure

18).
In watch and subactive modes, the timer-A/ INT0 interrupt is generated synchronously with the interrupt

frame. The interrupt request is generated synchronously with the interrupt strobe timing except during
transition to active mode. The falling edge of the INT0 signal is input asynchronously with the interrupt
frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the
falling edge. An overflow and interrupt request in timer A is generated synchronously with the interrupt
strobe timing.

Oscillation
stabilization period

Active mode Watch mode Active mode

Interrupt strobe

INT

0

Interrupt request
generation

t

(During the transition
from watch mode to
active mode only)

T:

Interrupt frame length

t :

Oscillation stabilization period

RC

If the time from the fall of the INT

Note:

and active mode is entered and is designated Tx, then Tx will be in the
following range:
T + t

≤ Tx ≤ 2T + tRC

RC

signal until the interrrupt is accepted

0

TT

T

X

RC

Figure 17 Interrupt Frame

35

HD404829R Series

Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on

flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described
below:

• Set LSON to 0 and DTON to 1 in subactive mode.

• Execute the STOP or SBY instruction.

• The MCU automatically enters active mode from subactive mode after waiting for the MCU internal

processing time and oscillation stabilization time (figure 19).

Notes: 1. The DTON flag can be set only in subactive mode. It is always reset in active mode.

2. The transition time (TD) from subactive mode to active mode:
tRC < TD < T + t

Miscellaneous register (MIS: $00C)

RC

Bit
Initial value
Read/Write
Bit name

MIS3 MIS2

Buffer control.
Refer to figure 41.

Notes: 1.

Values of T and t

2.

The value is applied only when direct transfer operation is used.

(Set LSON = 0, DTON = 1)

Interrupt strobe

3
0

W

MIS3

2
0

W

MIS2

MIS10MIS0 T

0
1
1

RC

MIS1

0 0.24414 ms

1
0
1

when a 32.768-kHz crystal oscillator is used to pins ×1 and ×2.

Figure 18 Miscellaneous Register (MIS)

STOP/SBY instruction execution

Subactive mode

1
0

W

MIS0

15.625 ms

62.5 ms
Not used

MCU internal
processing time

0
0

W

*

1 * 1

0.12207 ms

0.24414 ms

7.8125 ms

31.25 ms
Not used

t

RC

*2

Oscillation
stabilization
time

Oscillation circuit conditions

External clock input

Ceramic oscillator
Crystal oscillator
—

Active mode

36

Direct transfer
completion timing

T

Interrupt frame length

T:

Oscillation stabilization period

t :

RC

Direct transition time

T :

D

T

D

t

RC

Figure 19 Direct Transition Timing

HD404829R Series

Stop Mode Cancellation by STOPC : The MCU enters active mode from stop mode by inputting

STOPC as well as by RESET. In either case, the MCU starts instruction execution from the starting
address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3)
differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME
= 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in
stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that
stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode
is used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at
the beginning of the program.

MCU Operation Sequence: The MCU operates in the sequence shown in figures 20 to 22. It is reset by
an asynchronous RESET input, regardless of its status.

The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.

Power on

RESET = 1 ?

Yes

RAME = 0

Reset MCU

No

Figure 20 MCU Operating Sequence (Power On)

MCU

operation

cycle

37

HD404829R Series

MCU operation

cycle

IF:

Interrupt request flag

IM:

Interrupt mask

IE:

Interrupt enable flag

PC:

Program counter

CA:

Carry flag

ST:

Status flag

Low-power mode

operation cycle

Yes

IF = 1?

No

Instruction
execution

SBY/STOP
instruction?

No

←

PC Next

location

Yes

No

IM = 0 and

IE = 1?

Yes

←

IE 0
Stack (PC),

←

(CA),
(ST)

←

PC Vector

address

38

Figure 21 MCU Operating Sequence (MCU Operation Cycle)

STOP/SBY

Instruction

HD404829R Series

Interrupt

service

routine

No

IF = 1 and

IM = 0?

Yes

IE = 0

Yes

Hardware NOP

execution

PC ← (PC)+1

No

No

Standby/watch

mode

*

IF = 1 and

IM = 0?

Yes

Hardware NOP

execution

PC ← (PC)+1

Instruction

execution

No

Stop mode

STOPC = 0?

Yes

RAME = 1

Reset MCU

MCU operation

cycle

*Refer to figure 15, Flowchart for Exiting Low Power Modes, for IF and IM operation.

Note:

Figure 22 MCU Operating Sequence (Low-Power Mode Operation)

39

HD404829R Series

Notes: 1. When watch mode or subactive mode on HD404829R Series/HD4074829 is used and the LCD

function is off in that mode, the watch mode or subactive mode current is larger, and
consequently the following settings should be made.

Perform the following writes in the order shown before the transition to watch mode (before
execution of the STOP instruction):

Write $0 to LCR
Write $3 to LMR

Also, when returning to active mode from watch mode or subactive mode, perform the following
writes in the order shown:

Write a value appropriate to the conditions of use to LMR
Write a value appropriate to the conditions of use to LCR

A sample programming flowchart for the above procedures is shown in figure 23.

.

.

.

LMR

LCR

.

.

.

Set
appropriate
values for
active mode

Initialization routine

.

.

.

LCR = $0

LMR = $3

.

.

.

STOP instruction

After the MCU enters active mode again

.

.

.

LMR

LCR

.

.

.

Include these
operations

Watch mode

Set
appropriate
values for
active mode

Main routine

Or transition to
subactive mode

INT or timer A

0

interrupt processing
routine

Figure 23 Programming Flowchart (LCD Display Off in Watch or Subactive Mode)

40

HD404829R Series

Notes: 2. When the MCU is in watch mode or subactive mode, if the high level period before the falling

edge of I NT 0 is shorter than the interrupt frame, I NT 0 is not detected. Also, if the low level period
after the falling edge of I NT 0 is shorter than the interrupt frame, I NT 0 is not detected.

Edge detection is shown in figure 24. The level of the INT0 signal is sampled by a sampling
clock. When this sampled value changes to low from high, a falling edge is detected.
In figure 25, the level of the I NT 0 signal is sampled by an interrupt frame. In (a) the sampled
value is low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b),
the sampled value is high at point A, and also high at point B. A falling edge is not detected in
this case either.

When the MCU is in watch mode or subactive mode, keep the high level and low level period of

INT0 longer than interrupt frame.

INT

0

Sampling

INT

0

Interrupt
frame

High Low

Low

Figure 24 Edge Detection

INT

0

Interrupt

A: Low B: Low

(a) High level period (b) Low level period

frame

A: High B: High

Figure 25 Sampling Example

41

HD404829R Series

Internal Oscillator Circuit

A block diagram of the clock generation circuit is shown in figure 26. As shown in table 16, a ceramic
oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and
X2. The system oscillator can also be operated by an external clock. Bit 1 (SSR1) of the system clock
select register (SSR: $029) must be set according to the frequency of the oscillator connected to OSC1 and
OSC2 (figure 27).

Note: If the system clock select register (SSR: $029) setting does not match the oscillator frequency,

DTMF generator and subsystems using the 32.768-kHz oscillation will malfunction.

LSON

OSC

OSC

X1

X2

f

2

1

System

clock

oscillator

Sub-

system

clock

oscillator

OSC

f

X

division

circuit

1/8 or 1/4

division

circuit

division

circuit

1/4

1/8

f

cyc

t

cyc

f

SUB

t

subcyc

f

W

t

Wcyc

Timing

generation

circuit

Timing

generation

circuit

Timing

generation

circuit

System

clock

selection

circuit

ø

ø

CPU

PER

TMA3 bit

Clock

Time-base

selection

circuit

Note: **1/8 or 1/4 division ratio can be selected by setting bit 2 of the system

clock select register (SSR: $029).

Figure 26 Clock Generation Circuit

clock

CPU with ROM,
RAM, registers,

flags, and I/O

peripheral

(other than timer A)

ø

CLK

interrupt

Internal
module

interrupt

Time A

42

System clock select register (SSR: $029)

HD404829R Series

SSR3

0
1

Bit
Initial value
Read/Write
Bit name

32-kHz oscillation stop

Oscillation operates in stop mode
Oscillation stops in stop mode

3
0

W

SSR3

2
0

W

SSR2

—
—
—

1

0
—
—
—

SSR1

0
1

32-kHz oscillation division

SSR2

0
1

Note:

ratio selection

f

= fX/8

SUB

f

= fX/4

SUB

SSR3 is cleared only by a RESET input. SSR3 will not be cleared
by a STOPC input duringstop mode, and will retain its value.
SSR3 will also not be cleared upon entering stop mode.

Figure 27 System Clock Select Register (SSR)

System clock selection

f

= 400 kHz to 1 MHz

OSC

f

= 1.6 to 4.2 MHz

OSC

D

0

GND

X2

X1

RESET

OSC

2

OSC

1

TEST

GND

AV

SS

Figure 28 Typical Layouts of Crystal and Ceramic Oscillator

43

HD404829R Series

Table 16 Oscillator Circuit Examples

Circuit Configuration Circuit Constants

External clock
operation

External
oscillator

OSC

—

1

Ceramic oscillator

, OSC2)

(OSC

1

Crystal oscillator

, OSC2)

(OSC

1

Open

GND

GND

C

Ceramic
oscillator

C

C

1

Crystal
oscillator

C

2

OSC

2

Ceramic oscillator: CSB400P22 (Murata)

CSB400P (Murata)

R

= 1 MΩ ± 20%

f

C1 = C2 = 220 pF ± 5%

1

OSC

1

R

f

OSC

2

2

Ceramic oscillator: CSB800J122 (Murata)

CSB800J (Murata)

R

= 1 MΩ ± 20%

f

C

= C2 = 220 pF ± 5%

1

Ceramic oscillator: CSA2.00MG (Murata)
Rf = 1 MΩ ± 20%
C

= C2 = 30 pF ± 20%

1

Ceramic oscillator: CSA4.00MG (Murata)
Rf = 1 MΩ ± 20%
C

= C2 = 30 pF ± 20%

1

Rf = 1 MΩ ± 20%

OSC

OSC

1

2

R

f

C

= C2 = 10 to 22pF ± 20%

1

Crystal : Equivalent circuit at left
C

=7pF max

0

R

= 100Ω max

s

Crystal oscillator
(X1, X2)

44

OSC

1

C

LSC

1

R

S

C

0

X1

Crystal
oscillator

X2

C

2

GND

LSC

R

S

X1 X2

C

0

OSC

2

Crystal oscillator: 32.768 kHz: MX38T
(Nippon Denpa)
C

= C2 = 20 pF ± 20%

1

R

: 14 kΩ

S

C

: 1.5 pF

0

HD404829R Series

Notes: 1. Circuit constants differ by the different types of crystal oscillators, ceramic oscillators, and with the

stray capacitance of the board, so consult the manufacturer of the oscillator to determine the
circuit parameters.

2. The wiring between the OSC
as possible, and must not cross other wiring. Refer to figure 28.

3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to V

, OSC2 (X1 and X2 pins), and the other elements should be as short

1

and leave the X2 pin open.

CC

45

HD404829R Series

Input/Output

The MCU has 42 input/output pins (D0–D9, R00–R73) and 2 input pins (D10, D11). The features are
described below.

• Ten pins (D0–D9) are high-current input/output pins.

• The D10 and D11, and R00–R73 input/output pins are multiplexed with peripheral function pins such as

for the timers or serial interface. For these pins, the peripheral function setting is done prior to the D or
R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and
input/output selection are automatically switched according to the setting.

• Input or output selection for input/output pins and port or peripheral function selection for multiplexed

pins are set by software.

• Peripheral function output pins are CMOS output pins. Only the R23/SO pin can be set to NMOS open-

drain output by software.

• In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output

pins are in high-impedance state.

• Each input/output pin has a built-in pull-up MOS, which can be individually turned on or off by

software.

I/O buffer configuration is shown in figure 29, programmable I/O circuits are listed in table 17, and I/O pin
circuit types are shown in table 18.

Table 17 Programmable I/O Circuits

MIS3 (bit 3 of MIS) 0 1
DCD, DCR 0 1 0 1
PDR 01010101

CMOS buffer PMOS — — — On — — — On

NMOS — — On — — — On —

Pull-up MOS — — — — — On — On
Note: — indicates off status.

46

HD404829R Series

HLT

MIS3

DCD, DCR

PDR

Pull-up
MOS

V

CC

V

CC

Input control signal

Pull-up control signal

Buffer control signal

Output data

Input data

Figure 29 I/O Buffer Configuration

Table 18 Circuit Configurations of I/O Pins

I/O Pin Type Circuit Pins

Input/output pins

V

CC

V

CC

Input control signal

V

CC

V

CC

Pull-up control signal
Buffer control

signal

Output data

Input data

Pull-up control signal
Buffer control

signal

Output data

Input data

HLT

MIS3

DCD, DCR

PDR

HLT

MIS3

DCR
MIS2
PDR

D0 – D
R00–R0
R10–R1
R20–R2
R30–R3
R40–R4
R50–R5
R60–R6
R70–R7

R2

9

3
3
2
3
3
3
3
3

3

Input pins

Input control signal

Input control signal

Input data

D10, D

11

47

HD404829R Series

Table 18 Circuit Configurations of I/O Pins (cont)

I/O Pin Type Circuit Pins

Peripheral
function
pins

Input/output
pins

V

CC

V

CC

Pull-up control signal

HLT

MIS3

SCK

Output pins

Input pins

Output data

Input data

V

CC

V

CC

V

CC

V

CC

V

CC

Pull-up control signal

Pull-up control signal

Output data

Input data

Input data

SCK

PMOS control
signal

Output data

SCK

HLT

MIS3

MIS2

SO

HLT

MIS3

TOB, TOC, TOD

HLT

MIS3

PDR

SI, INT1, etc

INT0, STOPC

SO

TOB, TOC, TOD

SI, INT1, INT2,
INT

, INT4,

3

EVNB, EVND

INT

, STOPC

0

Notes: 1. The MCU is reset in stop mode, and peripheral function selection is cancelled. The HLT signal

becomes low, and input/output pins enter high-impedance state.

2. The HLT signal is 1 in watch and subactive modes.

48

HD404829R Series

D Port (D0–D11): Consist of 10 input/output pins and 2 input pins addressed by one bit. D0–D9 are high-

current I/O pins, and D10 and D11 are input-only pins.
Pins D0–D9 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.

Output data is stored in the port data register (PDR) for each pin. All pins D0–D11 are tested by the TD and
TDD instructions.

The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0–DCD2:
$02C–$02E) that are mapped to memory addresses (figure 30).

Pins D10 and D11 are multiplexed with peripheral function pins STOPC and I NT 0, respectively. The
peripheral function modes of these pins are selected by bits 2 and 3 (PMRC2, PMRC3) of port mode
register C (PMRC: $025) (figure 31).

R Ports (R00–R73): 32 input/output pins addressed in 4-bit units. Data is input to these ports by the LAR
and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored in the
port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are controlled
by R-port data control registers (DCR0–DCR7: $030–$037) that are mapped to memory addresses (figure

30).
Pins R00–R03 are multiplexed with peripheral pins INT1–INT4, respectively. The peripheral function

modes of these pins are selected by bits 0–3 (PMRB0–PMRB3) of port mode register B (PMRB: $024)
(figure 32).

Pins R10–R12 are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral
function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2
(TMB2: $013), bits 0–2 (TMC20–TMC22) of timer mode register C2 (TMC2: $014), and bits 0–3
(TMD20–TMD23) of timer mode register D2 (TMD2: $015) (figures 33, 34, and 35).

Pins R13 and R20 are multiplexed with peripheral pins EVNB and EVND, respectively. The peripheral
function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C
(PMRC: $025) (figure 31).

Pins R21–R23 are multiplexed with peripheral pins SCK, SI, and SO, respectively. The peripheral function
modes of these pins are selected by bit 3 (SMRA3) of serial mode register A (SMRA: $005), and bits 0 and
1 (PMRA0, PMRA1) of port mode register A (PMRA: $004), as shown in figures 36 and 37.

Ports R3 and R4 are multiplexed with segment pins SEG1–SEG8, respectively. The function modes of
these pins can be selected by individual pins, by setting LCD output registers 1 and 2 (LOR1, LOR2: $01D,
$01F) (figures 38 and 39).

Ports R5–R7 are multiplexed with segment pins SEG9–SEG20, respectively. The function modes of these
pins can be selected in 4-pin units by setting LCD output register 3 (LOR3: $01F) (figure 40).

49

HD404829R Series

Data control register (DCD0 to 2: $02C to $02E)

(DCR0 to 7: $030 to $037)

DCD0, DCD1

Bit
Initial value
Read/Write
Bit name

3
0

W

DCD03,

2
0

W

DCD02,

1
0

W

DCD01,

0
0

W

DCD00,

DCD13 DCD12 DCD10DCD11

DCD2

Bit
Initial value
Read/Write
Bit name

3
—
—

Not used

2
—
—

Not used

1
0

W

DCD21

0
0

W

DCD20

DCR0 to DCR7

Bit
Initial value
Read/Write
Bit name

3
0

W

DCR03–

2

0
W

DCR02–

1
0

W

DCR01–

0
0

W

DCR00–

DCR73 DCR72 DCR70DCR71

All Bits CMOS Buffer On/Off Selection

0 Off (high-impedance)
1On

Correspondence between ports and DCD/DCR bits

Register Name Bit 3 Bit 2 Bit 1 Bit 0

DCD0 D
DCD1 D

3
7

D

2

D

6

DCD2 — — D
DCR0 R0
DCR1 R1
DCR2 R2
DCR3 R3
DCR4 R4
DCR5 R5
DCR6 R6
DCR7 R7

3
3
3
3
3
3
3
3

R0
R1
R2
R3
R4
R5
R6
R7

2
2
2
2
2
2
2
2

D
D

R0
R1
R2
R3
R4
R5
R6
R7

1
5
9

1
1
1
1
1
1
1
1

D
D
D
R0
R1
R2
R3
R4
R5
R6
R7

0
4
8

0
0
0
0
0
0
0
0

Figure 30 Data Control Registers (DCD, DCR)

50

Port mode register C (PMRC: $025)

HD404829R Series

Bit
Initial value
Read/Write
Bit name

PMRC3

0
1

PMRC2

0
1

*

Note: PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop

3
0

W

PMRC3

PMRC2

D11/INT0 mode selection

D

11

INT

0

D10/STOPC mode selection

D

10

STOPC

mode, PMRC2 is not reset but retains its value.

Figure 31 Port Mode Register C (PMRC)

Port mode register B (PMRB: $024)

Bit
Initial value
Read/Write
Bit name

3
0

W

PMRB3

2
0

W

PMRB2

PMRB1

W

W

2
0

1
0

W

*

PMRC1

1
0

0
0

0
0

W

PMRC0

PMRC0

0
1

PMRC1

0
1

R13/EVNB mode selection
R1

3

EVNB

R20/EVND mode selection

R2

0

EVND

W

PMRB0

PMRB3

0
1

PMRB2

0
1

R0

/INT4 mode selection

3

R0

3

INT

4

R0

/INT3 mode selection

2

R0

2

INT

3

Figure 32 Port Mode Register B (PMRB)

PMRB0

0
1

PMRB1

0
1

R00/INT1 mode selection

R0

0

INT

1

R0

/INT2 mode selection

1

R0

1

INT

2

51

HD404829R Series

Timer mode register B2 (TMB2: $013)

Bit
Initial value
Read/Write
Bit name

TMB21

0

1

Not used

TMB20

0
1
0
1

3
—
—

2
—
—

Not used

R1

/TOB mode selection

0

R1

0

TOB
TOB
TOB

R/W

TMB21

R1

port

0

Toggle output
0 output
1 output

Figure 33 Timer Mode Register B2 (TMB2)

Timer mode register C2 (TMC2: $014)

Bit
Initial value
Read/Write
Bit name

3
—
—

Not used

2
0

R/W

TMC22

1
0

R/W

TMC21

1
0

0
0

R/W

TMB20

0
0

R/W

TMC20

TMC22 TMC20

TMC21

0

0

0
1

1

0
1

1

0

0

R1

/TOC mode selection

1

1

R1
Toggle output
0 output
1 output
Not used

R1
TOC
TOC
TOC
—

1

1

0
1

TOC

PWM output

Figure 34 Timer Mode Register C2 (TMC2)

port

1

52

Timer mode register D2 (TMD2: $015)

HD404829R Series

Bit
Initial value
Read/Write
Bit name

TMD23

TMD22 TMD20

0

1

✕: Don’t care

3
0

R/W

TMD23

0

1

TMD22

TMD21

0

1

0

2
0

R/W

R/W

TMD21

0
1
0
1
0

1
0

0
0

R/W

TMD20

R1

/TOD mode selection

2

R1

2

R12 port
TOD
TOD
TOD
—

Toggle output
0 output
1 output
Not used

1

1

✕✕✕

0
1

TOD
R1

PWM output
Input capture (R1

2

Figure 35 Timer Mode Register D2 (TMD2)

port)

2

Serial mode register A (SMRA: $005)

Bit
Initial value
Read/Write
Bit name

SMRA3

0
1

3
0

W

SMRA3

R21/SCK
mode selection

R2

1

SCK

SMRA2

2
0

W

SMRA1

SMRA2 SMRA0SMRA1 Clock source

0

1

Figure 36 Serial Mode Register A (SMRA)

1
0

W

0
0

W

SMRA0

0

1

0

1

Prescaler

SCK

Output

0

Output

1

Output

0

Output

1

Output

0

Output

1

Output

0

Input

1

Prescaler
Prescaler
Prescaler
Prescaler
Prescaler
Prescaler
System clock
External clock

division
ratio

÷2048
÷512
÷128
÷32
÷8
÷2

—
—

53

HD404829R Series

Port mode register A (PMRA: $004)

Bit
Initial value
Read/Write
Bit name

PMRA1

0
1

3
—
—

Not used

2
—
—

Not used

R22/SI mode selection

R2

2

SI

Figure 37 Port Mode Register A (PMRA)

LCD output register 1 (LOR1: $01D)

Bit
Initial value
Read/Write
Bit name

LOR13

0
1

3
0

W

LOR13

R33/SEG4 mode selection

R3

3

SEG4

PMRA1

2
0

W

LOR12

1
0

W

PMRA0

1
0

W

LOR11

0
0

W

PMRA0

0
1

LOR10

LOR11

0
1

R23/SO mode selection

R2

3

SO

0
0

W

R31/SEG2 mode selection

R3

1

SEG2

LOR12

0
1

R32/SEG3 mode selection

R3

2

SEG3

LOR10

0
1

Figure 38 LCD Output Register 1 (LOR1)

R30/SEG1 mode selection

R3

0

SEG1

54

LCD output register 2 (LOR2: $01E)

HD404829R Series

Bit
Initial value
Read/Write
Bit name

LOR23

0
1

LOR22

0
1

3
0

W

LOR23

R43/SEG8 mode selection

R4

3

SEG8

R42/SEG7 mode selection

R4

2

SEG7

Figure 39 LCD Output Register 2 (LAOR2)

LCD output register 3 (LOR3: $01F)

Bit
Initial value
Read/Write
Bit name

3
—
—

Not used

2
0

W

LOR32

W

LOR22

1
0

W

LOR31

2
0

W

LOR21

0
0

W

LOR30

1
0

LOR20

LOR21

0
1

LOR20

0
1

0
0

W

R41/SEG6 mode selection

R4

1

SEG6

R40/SEG5 mode selection

R4

0

SEG5

LOR32

0
1

R70/SEG17–R73/SEG20 mode selection

R7

–R7

0

3

SEG17–SEG20

Figure 40 LCD Output Register 3 (LOR3)

LOR31

0
1

LOR30

0
1

R60/SEG13–R63/SEG16 mode selection

R6

–R6

0

3

SEG13–SEG16

R50/SEG9–R53/SEG12 mode selection

R5

–R5

0

3

SEG9–SEG12

55

HD404829R Series

Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each

input/output pin other than input-only pins D10 and D11. The on/off status of all these transistors is
controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual
transistor can also be controlled by the port data register (PDR) of the corresponding pin—enabling on/off
control of that pin alone (table 17 and figure 41).

The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be

connected to VCC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by
their pull-up MOS transistors or by resistors of about 100 kΩ.

Miscellaneous register (MIS: $00C)

Bit
Initial value
Read/Write
Bit name

MIS3

0
1

3
0

W

MIS3

Pull-up MOS
on/off selection

Off
On

MIS2

W

2
0

1
0

W

MIS1

MIS2

0
1

0
0

W

MIS0

CMOS buffer
on/off selection
for pin R23/SO

On
Off

Figure 41 Miscellaneous Register (MIS)

MIS1 MIS0

t

selection.

RC

Refer to figure 18 in the
operation modes section.

56

HD404829R Series

Prescalers

The MCU has the following two prescalers, S and W.
The prescalers operating conditions are listed in table 19, and the prescalers output supply is shown in

figure 42. The timers A–D input clocks except external events, the serial transmit clock except the external
clock, and the LCD circuit operating clock are selected from the prescaler outputs, depending on
corresponding mode registers.

Prescaler Operation

Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset,

prescaler S divides the system clock. Prescaler S keeps counting, except in watch and subactive modes and
at MCU reset.

Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by
eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be
reset by software.

Table 19 Prescaler Operating Conditions

Prescaler Input Clock Reset Conditions Stop Conditions

Prescaler S System clock (in active and

standby mode),
Subsystem clock (in subactive
mode)

Prescaler W 32-kHz crystal oscillation MCU reset,

MCU reset MCU reset,

stop mode,
watch mode

MCU reset,

software

stop mode

Subsystem

clock

System

clock

Clock

selector

Prescaler W

Prescaler S

Figure 42 Prescaler Output Supply

LCD

Timer A

Timer B

Timer C

Timer D

Serial

57

HD404829R Series

Timers

The MCU has four timer/counters (A to D).

• Timer A: Free-running timer

• Timer B: Multifunction timer

• Timer C: Multifunction timer

• Timer D: Multifunction timer

Timer A is an 8-bit free-running timer. Timers B–D are 8-bit multifunction timers, whose functions are
listed in table 20. The operating modes are selected by software.

Table 20 Timer Functions

Functions Timer A Timer B Timer C Timer D

Clock Prescaler S Available Available Available Available source Prescaler W Available — — —

External event — Available — Available
Timer Free-running Available Available Available Available
functions Time-base Available — — —

Event counter — Available — Available

Reload — Available Available Available

Watchdog — — Available —

Input capture — — — Available
Timer Toggle — Available Available Available
outputs 0 output — Available Available Available

1 output — Available Available Available

PWM — — Available Available
Note: — implies not available.

Timer A
Timer A Functions: Timer A has the following functions.

• Free-running timer

• Clock time-base

The block diagram of timer A is shown in figure 43.

58

HD404829R Series

32.768-kHz
oscillator

System
clock

Data bus
Clock line
Signal line

1/4 1/2

2 f

1/2 tw

ø

PER

f

Prescaler W

W

tw

cyc

W

cyc

24832128

ччччччч

Prescaler S (PSS)

(PSW)

2816

÷÷÷

Selector

Selector

512

32

÷

1024

2048

÷

Clock

Selector

3

Figure 43 Block Diagram of Timer A

Timer A interrupt

request flag

(IFTA)

Timer

counter A

(TCA)

Timer mode

register A

(TMA)

Overflow

Internal data bus

Timer A Operations:

• Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:

$008).

• Timer A is reset to $00 by MCU reset and

incremented at each input clock. If an input clock is applied to timer A after it has reached

• $FF, an overflow is generated, and timer A is reset to $00. The overflow sets the timer A interrupt

request flag (IFTA: $001, bit 2). Timer A continues to be incremented after reset to $00, and therefore
it generates regular interrupts every 256 clocks.

• Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer

mode register A (TMA: $008) to 1. The prescaler W output is applied to timer A, and timer A
generates interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case,
prescaler W and timer A can be reset to $00 by software.

Registers for Timer A Operation: Timer A operating modes are set by the following registers.

• Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode

and input clock source as shown in figure 44.

59

HD404829R Series

Timer mode register A (TMA: $008)

Bit
Initial value
Read/Write
Bit name

3
0

W

TMA3

TMA3 TMA1TMA2 TMA0

0

00

0
1
0

1

1
0

0

1

1
0

1

1
0

1

00

1
0

1

1

1

0

0

1

1

✕

2
0

W

TMA2

Source
prescaler

PSS
PSS
PSS
PSS
PSS
PSS
PSS
PSS
PSW
PSW
PSW
PSW

—
—
—

1
0

W

TMA1

0
0

W

TMA0

Input clock
frequency

2048t

cyc

1024t

cyc

512t

cyc

128t

cyc

32t

cyc

8t

cyc

4t

cyc

2t

cyc

32t

Wcyc

16t

Wcyc

8t

Wcyc

2t

Wcyc

1/2t

Wcyc

Not used
Reset PSW and TCA

Operating mode

Timer A mode

Time-base mode

✕ : Don’t care
Note: 1.

t

Wcyc

2.

Timer counter overflow output period (seconds) = input clock period (seconds) × 256.

3.

If PSW of TCA reset is selected while the LCD is operating, LCD operation halts (power switch
goes off and all SEG and COM pins are grounded).
When an LCD is connected for display, the PSW and TCA reset periods must be set in the
program to the minimum.
The division ratio must not be modified during time-base mode operation, otherwise an overflow

4.
cycle error will occur.

60

= 244.14 µs (when a 32.768-kHz crystal oscillator is used)

Figure 44 Timer Mode Register A (TMA)

Timer B

Timer B Functions: Timer B has the following functions.

• Free-running/reload timer

• External event counter

• Timer output operation (toggle, 0, and 1 outputs)

The block diagram of timer B is shown in figure 45.

TOB

EVNB

System

clock

Timer output

control logic

φ

PER

÷2
÷4
÷8
÷32

(PSS)

÷128

Prescaler S

÷512
÷2048

Selector

3

Free-runnning/Reload control

Timer mode

register B1

(TMB1)

Timer read
register BU

Timer read

register BL

(TRBL)

4

Timer counter B

(TCBL) (TCBU)

4 4

Timer counter B

(TWBL) (TWBU)

(TRBU)

HD404829R Series

Timer B ineterrupt

request flag

(IFTB)

Overflow

Internal data bus

2

Edge detection
control

Data bus
Clock line

Signal line

Timer mode

register B2

(TMB2)

Figure 45 Block Diagram of Timer B

61

HD404829R Series

Timer B Operations:

• Free-running/reload timer operation: The free-running/reload operation, input clock source, and

prescaler division ratio are selected by timer mode register B1 (TMB1: $009).

Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by

software and incremented by one at each clock input. If an input clock is applied to timer B after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is
initialized to its initial value set in timer write register B; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or

MCU reset. Refer to figure 3 and table 1 for details.

• External event counter operation: Timer B is used as an external event counter by selecting external

event input as input clock source. In this case, pin R13/EVNB must be set to EVNB by port mode
register C (PMRC: $025).

Timer B is incremented by one at each falling edge of signals input to pin EVNB. The other operation

is basically the same as the free-running/reload timer operation.

• Timer output operation: The following three output modes can be selected for timer B by setting timer

mode register B2 (TMB2: $013).

Toggle
0 output
1 output

By selecting the timer output mode, pin R10/TOB is set to TOB. The output from TOB is reset low by
MCU reset.

 Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input

after timer B has reached $FF. By using this function and reload timer function, clock signals can
be output at a required frequency for the buzzer. The output waveform is shown in figure 46.

 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after

timer B has reached $FF. Note that this function must be used only when the output level is high.

 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer

B has reached $FF. Note that this function must be used only when the output level is low.

62

Toggle output waveform (timers B, C, and D)

Free-running timer

256 clock cycles 256 clock cycles

Reload timer

(256 – N) clock cycles (256 – N) clock cycles

PWM output waveform (timers C and D)

×

T (N + 1)

TMC13 = 0
TMD13 = 0

×

T 256

T

HD404829R Series

TMC13 = 1
TMD13 = 1

Note:

×

T (256 – N)

The waveform is always fixed low when N = $FF.

Input clock period to counter (figures 52 and 60)

T:

The value of the timer write register

N:

Figure 46 Timer Output Waveform

63

HD404829R Series

Registers for Timer B Operation: By using the following registers, timer B operation modes are selected

and the timer B count is read and written.

Timer mode register B1 (TMB1: $009)
Timer mode register B2 (TMB2: $013)
Timer write register B (TWBL: $00A, TWBU: $00B)
Timer read register B (TRBL: $00A, TRBU: $00B)
Port mode register C (PMRC: $025)

• Timer mode register B1 (TMB1: $009):

Four-bit write-only register that selects the free-running/reload timer function, input clock source, and
the prescaler division ratio as shown in figure 47. It is reset to $0 by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register B1 write instruction. Setting timer B’s initialization by writing to timer
write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.

Timer mode register B1 (TMB1: $009)

Bit
Initial value
Read/Write
Bit name

TMB13

0
1

3
0

W

TMB13

Free-running/reload
timer selection

Free-running timer
Reload timer

2
0

W

TMB12

Figure 47 Timer Mode Register B1 (TMB1)

Timer mode register B2 (TMB2: $013)

Bit
Initial value
Read/Write
Bit name

3
—
—

Not used

2
—
—

Not used

R/W

TMB21

1
0

W

TMB11

1
0

TMB10

TMB12 TMB10TMB11

0

1

0
0

R/W

TMB20

0
0

W

Input clock period and input
clock source

2048t

TMB21

0

1

0
1
0
1
0
1
0
1

cyc

512t

cyc

128t

cyc

32t

cyc

8t

cyc

4t

cyc

2t

cyc

R1

/EVNB (external event input)

3

TMB20

R1

/TOB mode selection

0

0

R1

0

1

TOB

0

TOB

1

TOB

R1

port

0

Toggle output
0 output
1 output

0

1

0

1

64

Figure 48 Timer Mode Register B2 (TMB2)

HD404829R Series

• Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output

mode as shown in figure 48. It is reset to $0 by MCU reset.

• Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit

(TWBL) and the upper digit (TWBU) as shown in figures 49 and 50. The lower digit is reset to $0 by
MCU reset, but the upper digit value is invalid.

Timer B is initialized by writing to timer write register B. In this case, the lower digit (TWBL) must be

written to first, but writing only to the lower digit does not change the timer B value. Timer B is
initialized to the value in timer write register B at the same time the upper digit (TWBU) is written to.
When timer write register B is written to again and if the lower digit value needs no change, writing
only to the upper digit initializes timer B.

Timer write register B (lower digit) (TWBL: $00A)

Bit
Initial value
Read/Write
Bit name

3
0

W

TWBL3

2
0

W

TWBL2

1
0

W

TWBL1

0
0

W

TWBL0

Figure 49 Timer Write Register B Lower Digit (TWBL)

Timer write register B (upper digit) (TWBU: $00B)

Bit
Initial value
Read/Write
Bit name

3

Undefined

W

TWBU3

2

Undefined

W

TWBU2

1

Undefined

W

TWBU1

0

Undefined

W

TWBU0

Figure 50 Timer Write Register B Upper Digit (TWBU)

• Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit

(TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 51 and 52).

The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is

obtained, and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by
reading TRBL, the count of timer B when TRBU is read can be obtained.

65

HD404829R Series

Timer read register B (lower digit) (TRBL: $00A)

Bit
Initial value
Read/Write
Bit name

3

Undefined

R

TRBL3

2

Undefined

R

TRBL2

1

Undefined

R

TRBL1

0

Undefined

R

TRBL0

Figure 51 Timer Read Register B Lower Digit (TRBL)

Timer read register B (upper digit) (TRBU: $00B)

Bit
Initial value
Read/Write
Bit name

3

Undefined

R

TRBU3

2

Undefined

R

TRBU2

1

Undefined

R

TRBU1

0

Undefined

R

TRBU0

Figure 52 Timer Read Register B Upper Digit (TRBU)

• Port mode register C (PMRC: $025): Write-only register that selects R13/EVNB pin function as shown

in figure 53. It is reset to $0 by MCU reset.

Port mode register C (PMRC: $025)

Bit
Initial value
Read/Write
Bit name

PMRC3

0
1

PMRC2

0
1

3
0

W

PMRC3

2
0

W

PMRC2

1
0

W

PMRC1

D11/INT0 mode selection

D

11

INT

0

D10/STOPC mode selection

D

10

STOPC

Figure 53 Port Mode Register C (PMRC)

0
0

W

PMRC0

PMRC1

0
1

PMRC0

0
1

R20/EVND mode selection

R2

0

EVND

R13/EVNB mode selection

R1

3

EVNB

66

Timer C

Timer C Functions: Timer C has the following functions.

• Free-running/reload timer

• Watchdog timer

• Timer output operation (toggle, 0, 1, and PWM outputs)

The block diagram of timer C is shown in figure 54.

HD404829R Series

67

HD404829R Series

System reset signal

TOC

System

clock

Timer output

control logic

ø

PER

Prescalers

(PSS)

Watchdog on

flag

(WDON)

÷2
÷ 4

÷ 8
÷ 32
÷ 128
÷ 512

÷ 1024
÷ 2048

Selector

Watchdog timer

control logic

3

Timer read

register CL

(TRCL)

4

Timer counter C

(TCCL) (TCCU)

4 4

Timer write register C

(TWCL) (TWCU)

Timer C

interrupt request

flag

(IFTC)

Timer read

register CU

(TRCU)

Internal data bus

3

Data bus
Clock line

Signal line

Free-running/reload control

Timer output

control

Timer mode

register C1

(TMC1)

Timer mode

register C2

(TMC2)

Figure 54 Block Diagram of Timer C

68

HD404829R Series

Timer C Operations:

• Free-running/reload timer operation: The free-running/reload operation, input clock source, and

prescaler division ratio are selected by timer mode register C1 (TMC1: $00D).

Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by

software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or

MCU reset. Refer to figure 3 and table 1 for details.

• Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program

routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing
timer C by software before it reaches $FF.

• Timer output operation: The following four output modes can be selected for timer C by setting timer

mode register C2 (TMC2: $014).

Toggle
0 output
1 output
PWM output

By selecting the timer output mode, pin R11/TOC is set to TOC. The output from TOC is reset low by
MCU reset.

 Toggle output: The operation is basically the same as that of timer-B’s toggle output.
 0 output: The operation is basically the same as that of timer-B’s 0 output.
 1 output: The operation is basically the same as that of timer-B’s 1 output.
 PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output

function. The output waveform differs depending on the contents of timer mode register C1
(TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is
shown in figure 46.

69

HD404829R Series

Registers for Timer C Operation: By using the following registers, timer C operation modes are selected

and the timer C count is read and written.

Timer mode register C1 (TMC1: $00D)
Timer mode register C2 (TMC2: $014)
Timer write register C (TWCL: $00E, TWCU: $00F)
Timer read register C (TRCL: $00E, TRCU: $00F)

• Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/reload

timer function, input clock source, and the prescaler division ratio as shown in
figure 55. It is reset to $0 by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C1 write instruction. Setting timer C’s initialization by writing to timer
write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.

Timer mode register C1 (TMC1: $00D)

Bit
Initial value
Read/Write
Bit name

TMC13

0
1

3
0

W

TMC13

Free-running/reload timer selection

Free-running timer
Reload timer

2
0

W

TMC12

1
0

W

TMC11

Figure 55 Timer Mode Register C1 (TMC1)

0
0

W

TMC10

TMC12 TMC10TMC11

0

1

Input clock period

0

1

0

1

0
1
0
1
0
1
0
1

2048t
1024t
512t
128t
32t

cyc

8t

cyc

4t

cyc

2t

cyc

cyc

cyc

cyc

cyc

70

HD404829R Series

• Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output

mode as shown in figure 56. It is reset to $0 by MCU reset.

• Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of the lower digit

(TWCL) and the upper digit (TWCU). The operation of timer write register C is basically the same as
that of timer write register B (TWBL: $00A, TWBU: $00B).

• Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of the lower digit

(TRCL) and the upper digit (TRCU) that holds the count of the timer C upper digit. The operation of
timer read register C is basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B).

Timer mode register C2 (TMC2: $014)

Bit
Initial value
Read/Write
Bit name

3
—
—

Not used

2
0

R/W

TMC22

TMC220TMC21 R11/TOC mode selection

10

1
0

R/W

TMC21

0

1

1

0
0

R/W

TMC20

TMC20

0
1
0
1
0
1
0
1

Figure 56 Timer Mode Register C2 (TMC2)

R1
TOC
TOC
TOC
—

TOC

1

R1

port

1

Toggle output
0 output
1 output
Not used

PWM output

71

HD404829R Series

Timer write register C (lower digit) (TWCL: $00E)

Bit
Initial value
Read/Write
Bit name

3
0

W

TWCL3

2
0

W

TWCL2

1
0

W

TWCL1

0
0

W

TWCL0

Figure 57 Timer Write Register C Lower Digit (TWCL)

Timer write register C (upper digit) (TWCU: $00F)

Bit
Initial value
Read/Write
Bit name

3

Undefined

W

TWCU3

2

Undefined

W

TWCU2

1

Undefined

W

TWCU1

0

Undefined

W

TWCU0

Figure 58 Timer Write Register C Upper Digit (TWCU)

Timer read register C (lower digit) (TRCL: $00E)

Bit
Initial value
Read/Write
Bit name

3

Undefined

R

TRCL3

2

Undefined

R

TRCL2

1

Undefined

R

TRCL1

0

Undefined

R

TRCL0

72

Figure 59 Timer Read Register C Lower Digit (TRCL)

Timer read register C (upper digit) (TRCU: $00F)

Bit
Initial value
Read/Write
Bit name

3

Undefined

R

TRCU3

2

Undefined

R

TRCU2

1

Undefined

R

TRCU1

0

Undefined

R

TRCU0

Figure 60 Timer Read Register C Upper Digit (TRCU)

HD404829R Series

Timer D
Timer D Functions: Timer D has the following functions.

• Free-running/reload timer

• External event counter

• Timer output operation (toggle, 0, 1, and PWM outputs)

• Input capture timer

The block diagram for each operation mode of timer D is shown in figures 61 and 62.

Timer D Operations:

• Free-running/reload timer operation: The free-running/reload operation, input clock source, and

prescaler division ratio are selected by timer mode register D1 (TMD1: $010).

Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by

software and incremented by one at each clock input. If an input clock is applied to timer D after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is
initialized to its initial value set in timer write register D; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.

The overflow sets the timer D interrupt request flag (IFTD: $003, bit 0). IFTD is reset by software or

MCU reset. Refer to figure 3 and table 1 for details.

• External event counter operation: Timer D is used as an external event counter by selecting the

external event input as an input clock source. In this case, pin R20/EVND must be set to EVND by port
mode register C (PMRC: $025).

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the

external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and
falling edges detection is selected, the time between the falling edge and rising edge of input signals
must be 2t

Timer D is incremented by one at each detection edge selected by detection edge select register 2

(ESR2: $027). The other operation is basically the same as the free-running/reload timer operation.

• Timer output operation: The following four output modes can be selected for timer D by setting timer

mode register D2 (TMD2: $015).

Toggle
0 output
1 output
PWM output

By selecting the timer output mode, pin R12/TOD is set to TOD. The output from TOD is reset low by
MCU reset.

 Toggle output: The operation is basically the same as that of timer-B’s toggle output.
 0 output: The operation is basically the same as that of timer-B’s 0 output.
 1 output: The operation is basically the same as that of timer-B’s 1 output.
 PWM output: The operation is basically the same as that of timer-C’s PWM output.

or longer.

cyc

73

HD404829R Series

• Input capture timer operation: The input capture timer counts the clock cycles between trigger edges

input to pin EVND.
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the

trigger input edge by detection edge select register 2 (ESR2: $027).
When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL:

$011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While
ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input
capture error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing

0.
By selecting the input capture operation, pin R12/TOD is set to R12 and timer D is reset to $00.

74

EVND

System

clock

Edge detection

logic

øPER

HD404829R Series

Timer D interrupt

request flag

(IFTD)

Timer read register
DU (TRDU)

Timer read

register DL

(TRDL)

Data bus
Clock line
Signal line

÷ 2
÷ 4

÷ 8
÷ 32
÷ 128
÷ 512

Prescaler S (PSS)

÷ 2048

2

Edge detection
control

TOD

Selector

3

Timer mode

register D1

(TMD1)

Edge detection

selection register

2 (ESR2)

Timer output

control logic

4

Timer counter D

(TCDL) (TCDU)

4 4

Timer write register D

(TWDL) (TWDU)

Free-running/reload control

Timer mode

register D2

(TMD2)

3

Internal data bus

Figure 61 Block Diagram of Timer D (Free-Running/Reload Timer)

75

HD404829R Series

EVND

System

clock

Edge detection

logic

øPER

Input capture

status flag

(ICSF)

Read signal

÷2
÷4
÷8
÷32
÷128
÷512

Prescaler S (PSS)

÷2048

Error control

logic

Selector

Input capture

error flag

(ICEF)

Timer read register D

(TRDL) (TRDU)

4 4

Timer counter D

(TCDL) (TCDU)

Input capture
timer control

Timer D interrupt

request flag

(IFTD)

Overflow

Internal data bus

2

Edge
detection
control

3

Time mode

register D1

(TMD1)

Edge detection

selection register

2 (ESR2)

Timer mode

register D2

(TMD2)

Data bus
Clock line
Signal line

Figure 62 Block Diagram of Timer D (Input Capture Timer)

76

HD404829R Series

Registers for Timer D Operation: By using the following registers, timer D operation modes are selected

and the timer D count is read and written.

Timer mode register D1 (TMD1: $010)
Timer mode register D2 (TMD2: $015)
Timer write register D (TWDL: $011, TWDU: $012)
Timer read register D (TRDL: $011, TRDU: $012)
Port mode register C (PMRC: $025)
Detection edge select register 2 (ESR2: $027)

• Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload

timer function, input clock source, and the prescaler division ratio as shown in figure 63. It is reset to
$0 by MCU reset.

Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D’s initialization by
writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change
becomes valid.

When selecting the input capture timer operation, select the internal clock as the input clock source.

Timer mode register D1 (TMD1: $010)

Bit
Initial value
Read/Write
Bit name

TMD13

0
1

3
0

W

TMD13

Free-running/reload timer selection

Free-running timer
Reload timer

2
0

W

TMD12

TMD11

Figure 63 Timer Mode Register D1 (TMD1)

W

1
0

0
0

W

TMD10

TMD12 TMD10TMD11

0

1

Input clock period and
input clock source

0

1

0

1

0
1
0
1
0
1
0
1

2048t

cyc

512t

cyc

128t

cyc

32t

cyc

8t

cyc

4t

cyc

2t

cyc

R2

/EVND

0

(external event input)

77

HD404829R Series

• Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output

mode and input capture operation as shown in figure 64. It is reset to $0 by MCU reset.

• Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of the lower digit

(TWDL) and the upper digit (TWDU). The operation of timer write register D is basically the same as
that of timer write register B (TWBL: $00A, TWBU: $00B).

• Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of the lower digit

(TRDL) and the upper digit (TRDU). The operation of timer read register D is basically the same as
that of timer read register B (TRBL: $00A, TRBU: $00B).

When the input capture timer operation is selected and if the count of timer D is read after a trigger is

input, either the lower or upper digit can be read first.

• Port mode register C (PMRC: $025): Write-only register that selects R20/EVND pin function as shown

in figure 53. It is reset to $0 by MCU reset.

• Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of

signals input to pin EVND as shown in figure 69. It is reset to $0 by MCU reset.

Timer mode register D2 (TMD2: $015)

Bit
Initial value
Read/Write
Bit name

3
0

R/W

TMD23

2
0

R/W

TMD22

1
0

R/W

TMD21

0
0

R/W

TMD20

TMD23

✕: Don’t care

TMD22 TMD20

0

1

TMD21

0

1

✕✕✕

0

1

0

1

0
1
0
1
0
1
0
1

Figure 64 Timer Mode Register D2 (TMD2)

R1

/TOD mode selection

2

R1
TOD
TOD
TOD
—

TOD
R1

R12 port

2

Toggle output
0 output
1 output
Not used

PWM output
Input capture (R1

2

port)

2

78

Timer write register D (lower digit) (TWDL: $011)

HD404829R Series

Bit
Initial value
Read/Write
Bit name

3
0

W

TWDL3

2
0

W

TWDL2

1
0

W

TWDL1

0
0

W

TWDL0

Figure 65 Timer Write Register D Lower Digit (TWDL)

Timer write register D (upper digit) (TWDU: $012)

Bit
Initial value
Read/Write
Bit name

3

Undefined

W

TWDU3

2

Undefined

W

TWDU2

1

Undefined

W

TWDU1

0

Undefined

W

TWDU0

Figure 66 Timer Write Register D Upper Digit (TWDU)

Timer read register D (lower digit) (TRDL: $011)

Bit
Initial value
Read/Write
Bit name

3

Undefined

R

TRDL3

2

Undefined

R

TRDL2

1

Undefined

R

TRDL1

0

Undefined

R

TRDL0

Figure 67 Timer Read Register D Lower Digit (TRDL)

Timer read register D (upper digit) (TRDU: $012)

Bit
Initial value
Read/Write
Bit name

3

Undefined

R

TRDU3

2

Undefined

R

TRDU2

1

Undefined

R

TRDU1

0

Undefined

R

TRDU0

Figure 68 Timer Read Register D Upper Digit (TRDU)

79

HD404829R Series

Detection edge register 2 (ESR2: $027)

Bit
Initial value
Read/Write
Bit name

ESR23

Note: Both falling and rising edges are detected.

ESR22

0

1

*

ESR23

0
1
0
1

3
0

W

2
0

W

ESR22

EVND detection edge

No detection
Falling-edge detection
Rising-edge detection
Double-edge detection

1
0

W

ESR21

ESR20

**

Figure 69 Detection Edge Select Register 2 (ESR2)

W

0
0

ESR21

0

1

ESR20

0
1
0
1

INT

detection edge

4

No detection
Falling-edge detection
Rising-edge detection
Double-edge detection

80

HD404829R Series

Note on Use

When using the timer output as PWM output, note the following point. From the update of the timer write
register untill the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 21. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.

Table 21 PWM Output Following Update of Timer Write Register

PWM Output

Mode

Free
running

Timer Write Register is Updated
during High PWM Output

Timer write
register
rewrite
(set value
is N)

Interrupt
request
generated

Timer Write Register is Updated
during Low PWM Output

Timer write
register
rewrite
(set value
is N)

Interrupt
request
generated

Reload

T × (255 – N) T × (N + 1)

Timer write
register
rewrite
(set value
is N)

Interrupt
request
generated

T × (N' + 1)

T × (255 – N) T × (N + 1)

Timer write
register
rewrite
(set value
is N)

TT × (255 – N)T

T

Interrupt
request
generated

TT × (255 – N)

81

HD404829R Series

Serial Interface

The serial interface serially transfers and receives 8-bit data, and includes the following features.

• Multiple transmit clock sources
 External clock
 Internal prescaler output clock
 System clock

• Output level control in idle states

Five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows.

Serial data register (SRL: $006, SRU: $007)
Serial mode register A (SMRA: $005)
Serial mode register B (SMRB: $028)
Miscellaneous register (MIS: $00C)
Octal counter (OC)
Selector

The block diagram of the serial interface is shown in figure 70.

82

HD404829R Series

SO

SCK

SI

System
clock

Octal

counter (OC)

Idle controll

logic

Selector

Clock

1/2

1/2

Selector

I/O controll

logic

ø

PER

÷2
÷8
÷32
÷128
÷512
÷2048

Prescaler S (PSS)

Data bus
Clock line
Signal line

Serial interrupt

request flag

(IFS)

Serial data

register (SRL/U)

Transfer
control

Serial mode

register A

(SMRA)

Serial mode

register B

(SMRB)

Internal data bus

Figure 70 Block Diagram of Serial Interface

Serial Interface Operation
Selecting and Changing the Operating Mode: table 22 lists the serial interface’s operating modes. To

select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and serial
mode register A (SMRA: $005) settings; to change the operating mode, always initialize the serial interface
internally by writing data to serial mode register A. Note that the serial interface is initialized by writing
data to serial mode register A. Refer to the following Serial Mode Register A section for details.

Pin Setting: The R21/SCK pin is controlled by writing data to serial mode register A (SMRA: $005). The
R22/SI and R23/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the
following Registers for Serial Interface section for details.

Transmit Clock Source Setting: The transmit clock source is set by writing data to serial mode register A
(SMRA: $005) and serial mode register B (SMRB: $028). Refer to the following Registers for Serial
Interface section for details.

Data Setting: Transmit data is set by writing data to the serial data register (SRL: $006, SRU: $007).
Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the
transmit clock and is input from or output to an external system.

The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output
level control in idle states is performed.

83

HD404829R Series

Table 22 Serial Interface Operating Modes

SMRA PMRA
Bit 3 Bit 1 Bit 0 Operating Mode

1 0 0 Continuous clock output mode

1 Transmit mode

1 0 Receive mode

1 Transmit/receive mode

Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to
000 by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit
clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000,
the serial interrupt request flag (IFS: $023, bit 2) is set, and the transfer stops.

When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t
to 8192t

by setting bits 2 to 0 (SMRA2– SMRA0) of serial mode register A (SMRA: $005) and bit 0

cyc

cyc

(SMRB0) of serial mode register B (SMRB: $028) as listed in table 23.

Table 23 Serial Transmit Clock (Prescaler Output)

SMRB SMRA
Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Transmit Clock Frequency

0000÷ 2048 4096t

1 ÷ 512 1024t

10÷ 128 256t

1 ÷ 32 64t

100÷ 8 16t

1 ÷ 24t

1000÷ 4096 8192t

1 ÷ 1024 2048t

10÷ 256 512t

1 ÷ 64 128t

100÷ 16 32t

1 ÷ 48t

cyc
cyc

cyc
cyc
cyc

cyc

cyc

cyc
cyc
cyc

cyc

cyc

Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 71.

STS wait state
Transmit clock wait state
Transfer state
Continuous clock output state (only in internal clock mode)

84

HD404829R Series

• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 71). In STS

wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is
then executed (01, 11), the serial interface enters transmit clock wait state.

• Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge

of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments
the octal counter, shifts the serial data register, and enters the serial interface in transfer state. However,
note that if continuous clock output mode is selected in internal clock mode, the serial interface does not
enter transfer state but enters continuous clock output state (17).

The serial interface enters STS wait state by writing data to serial mode register A (SMRA: $005) (04,

14) in transmit clock wait state.

• Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the

eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the
octal counter to 000, and the serial interface enters another state. When the STS instruction is executed
(05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is
entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.

In transfer state, writing data to serial mode register A (SMRA: $005) (06, 16) initializes the serial

interface, and STS wait state is entered.

If the state changes from transfer to another state, the serial interrupt request flag (IFS: $023, bit 2) is set

by the octal counter that is reset to 000.

• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered

only in internal clock mode. In this state, the serial interface does not transmit/
receive data but only outputs the transmit clock from the SCK pin.

When bits 1 and 0 (PMRA1, PMRA0) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If serial mode register A (SMRA: $005) is written to in continuous clock output mode (18), STS wait
state is entered.

85

HD404829R Series

External clock mode

SMRA write

Transmit clock wait state

(Octal counter = 000)

Internal clock mode

Continuous clock output state

(PMRA 0, 1 = 00)

Transmit clock 17

(Octal counter = 000,

transmit clock disabled)

04

01

03

8 transmit clocks

SMRA write

18

SMRA write

Transmit clock wait state

(Octal counter = 000)

STS wait state

STS instruction

Transmit clock

02

STS instruction (IFS 1)

(Octal counter = 000,

transmit clock disabled)

14

11

Transmit clock

12

STS instruction (IFS 1)

06

05

←

STS wait state

STS instruction

15

←

00

MCU reset

SMRA write (IFS 1)

Transfer state

(Octal counter = 000)

8 transmit clocks

13

SMRA write (IFS 1)

16

Transfer state

(Octal counter = 000)

←

MCU reset10

←

Note: Refer to the Operating States section for the corresponding encircled numbers.

Figure 71 Serial Interface State Transitions

Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state,

the output level of the SO pin can be controlled by setting bit 1 (SMRB1) of serial mode register B (SMRB:
$028) to 0 or 1. The output level control example is shown in figure 72. Note that the output level cannot
be controlled in transfer state.

86

HD404829R Series

State

MCU reset

PMRA write

SMRA write

SMRB write

SRL, SRU write

STS instruction

SCK pin (input)

SO pin

IFS

State

Transmit clock
wait state

STS wait state

Port selection

External clock selection

Output level control in

Undefined LSBidle idleMSB

STS wait state Transfer state

idle states

Data write for transmission

External clock mode

Transmit clock
wait state

Transfer state

Output level control in

Flag reset at transfer completion

Transmit clock
wait state

STS wait state

Dummy write for
state transition

idle states

STS wait state

MCU reset

PMRA write

SMRA write

SMRB write

SRL, SRU write

STS instruction

SCK pin (output)

SO pin

IFS

Port selection

Internal clock selection

Output level control in

Undefined MSB

idle states

Data write for transmission

idle idleLSB

Internal clock mode

Flag reset at transfer completion

Output level control in

Figure 72 Example of Serial Interface Operation Sequence

idle states

87

HD404829R Series

Transfer completion

Interrupts inhibited

Transmit clock error detection flowchart

←

(IFS 1)

←

IFS 0

SMRA write

IFS = 1?

No

Normal
termination

Yes

Transmit clock
error processing

State

SCK pin (input)

SMRA write

IFS

Transmit clock
wait state

Transmit clock wait state

Transfer state Transfer state

Noise

12345678

Transfer state has been
entered by the transmit clock
error. When SMRA is written,
IFS is set.

Flag set because octal
counter reaches 000

Transmit clock error detection procedure

Flag reset at
transfer completion

Figure 73 Transmit Clock Error Detection

88

HD404829R Series

Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a

spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 73.

If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer completion processing is performed and IFS is reset, writing to serial mode
register A (SMRA: $005) changes the state from transfer to STS wait. At this time IFS is set again, and
therefore the error can be detected.

Notes on Use:

• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit

clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode
register A (SMRA: $005) again.

• Serial interrupt request flag (IFS: $023, bit 2) set: If the state is changed from transfer to another by

writing to serial mode register A (SMRA: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request
flag, serial mode register A write or STS instruction execution must be programmed to be executed after
confirming that the SCK pin is at 1, that is, after executing the input instruction to port R2.

Registers for Serial Interface

The serial interface operation is selected, and serial data is read and written by the following registers.

Serial Mode Register A (SMRA: $005)
Serial Mode Register B (SMRB: $028)
Serial Data Register (SRL: $006, SRU: $007)
Port Mode Register A (PMRA: $004)
Miscellaneous Register (MIS: $00C)

Serial Mode Register A (SMRA: $005): This register has the following functions (figure 74).

• R21/SCK pin function selection

• Transfer clock selection

• Prescaler division ratio selection

• Serial interface initialization

Serial mode register A (SMRA: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.
A write signal input to serial mode register A (SMRA: $005) discontinues the input of the transmit clock to

the serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is
performed during data transfer, the serial interrupt request flag (IFS: $023, bit 2) is set.

Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.

89

HD404829R Series

Serial mode register A (SMRA: $005)

Bit
Initial value
Read/Write
Bit name

SMRA3

0
1

3
0

W

SMRA3

R21/SCK
mode selection

R2

1

SCK

SMRA2

2
0

W

1
0

W

SMRA1

SMRA2 SMRA0SMRA1

0

1

0
0

W

SMRA0

0

1

0

1

SCK

Output

0
1
0
1
0
1

Output

0

Input

1

Clock source

Prescaler

System clock
External clock

Prescaler
division ratio

Refer to
table 23

—
—

Figure 74 Serial Mode Register A (SMRA)

Serial Mode Register B (SMRB: $028): This register has the following functions (figure 75).

• Prescaler division ratio selection

• Output level control in idle states

Serial mode register B is a 2-bit write-only register. It cannot be written during data transfer.
By setting bit 0 (SMRB0) of this register, the prescaler division ratio is selected. Only bit 0 (SMRB0) can

be reset to 0 by MCU reset. By setting bit 1 (SMRB1), the output level of the SO pin is controlled in idle
states. The output level changes at the same time that SMRB1 is written to.

90

Serial mode register B (SMRB: $028)

HD404829R Series

Bit
Initial value
Read/Write
Bit name

SMRB1

0
1

3
—
—

Not used

Output level control in idle states

Low level
High level

2
—
—

Not used

1

Undefined

W

SMRB1

0
0

W

SMRB0

SMRB0

0
1

Transmit clock division ratio

Prescaler output divided by 2
Prescaler output divided by 4

Figure 75 Serial Mode Register B (SMRB)

Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 76 and

77).

• Transmission data write and shift

• Receive data shift and read

Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the
transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 78.

Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.

Serial data register (lower digit) (SRL: $006)

Bit
Initial value
Read/Write
Bit name

3

Undefined

R/W
SR3

2

Undefined

R/W
SR2

1

Undefined

R/W
SR1

Undefined

Figure 76 Serial Data Register (SRL)

Serial data register (upper digit) (SRU: $007)

Bit
Initial value
Read/Write
Bit name

3

Undefined

R/W
SR7

2

Undefined

R/W
SR6

1

Undefined

R/W
SR5

Undefined

Figure 77 Serial Data Register (SRU)

0

R/W
SR0

0

R/W
SR4

91

HD404829R Series

Transmit clock

12345678

Serial output
data

Serial input data
latch timing

Port Mode Register A (PMRA: $004): This register has the following functions (figure 79).

• R22/SI pin function selection

• R23/SO pin function selection

Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset.

Port mode register A (PMRA: $004)

LSB MSB

Figure 78 Serial Interface Output Timing

Bit
Initial value
Read/Write
Bit name

PMRA1

0
1

3
—
—

Not used

R22/SI mode selection

R2

2

SI

2
—
—

Not used

Figure 79 Port Mode Register A (PMRA)

1
0

W

PMRA1

0
0

W

PMRA0

PMRA0

0
1

R23/SO mode selection

R2

3

SO

92

HD404829R Series

Miscellaneous Register (MIS: $00C): This register has the following function (figure 80).

• R23/SO pin PMOS control
Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.

Miscellaneous register (MIS: $00C)

Bit
Initial value
Read/Write
Bit name

MIS3

0
1

MIS2

0
1

3
0

W

MIS3

Pull-up MOS on/off selection

Off
On

R23/SO PMOS on/off selection

On
Off

2

0

W

MIS2

1
0

W

MIS1

0
0

W

MIS0

MIS1

MIS0

0

1

0

1
0
1

t

RC

0.12207 ms

0.24414 ms

7.8125 ms

31.25 ms
Not used

Figure 80 Miscellaneous Register (MIS)

A/D Converter

The MCU has a built-in A/D converter that uses a successive approximation method with a resistor ladder.
It can measure four analog inputs with 8-bit resolution. As shown in the block diagram of figure 81, the
A/D converter has a 4-bit A/D mode register, a 1-bit A/D start flag, and a 4-bit plus 4-bit A/D data register.

93

HD404829R Series

A/D interrupt request flag

(IFAD)

AN

0

AN

1

AN

2

AN

3

Off in stop, watch,

and subactive

AV

CC

AV

SS

Selector

modes

Resistance ladder

2

+

COMP

–

Encoder

A/D control

logic

A/D start flag

(ADSF)

A/D mdoe register

(AMR)

A/D data register

(ADR)

Conversion time

control

Internal data bus

Data bus
Signal line

Figure 81 Block Diagram of A/D Converter

A/D Mode Register (AMR: $016): Four-bit write-only register which selects the A/D conversion period

and indicates analog input pin information. Bit 0 of the A/D mode register selects the A/D conversion
period, and bits 3 and 2 select a channel, as shown in figure 82.

94

A/D mode register (AMR: $016)

HD404829R Series

Bit
Initial value
Read/Write
Bit name

AMR3

0
0
1
1

AMR2

0
1
0
1

3
0

W

AMR3

2
0

W

AMR2

Analog input selection

AN

0

AN

1

AN

2

AN

3

1
—
—

Not used

0
0

W

AMR0

AMR0

Conversion time

0
1

34t
67t

cyc

cyc

Figure 82 A/D Mode Register (AMR)

A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower

digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion,
the resultant eight-bit data is held in this register until the start of the next conversion (figures 83, 84, and

85).

ADRU: $018 ADRL: $017

3210

3210

MSB LSB

Figure 83 A/D Data Registers (ADRU, ADRL)

Bit 0Bit 7

95

HD404829R Series

A/D data register (lower digit) (ADRL: $017)

Bit
Initial value
Read/Write
Bit name

3

0

R

ADRL3

2
0

R

ADRL2

1

0

R

ADRL1

0

0

R

ADRL0

Figure 84 A/D Data Register Lower Digit (ADRL)

A/D data register (upper digit) (ADRU: $018)

Bit
Initial value
Read/Write
Bit name

3

1

R

ADRU3

2
0

R

ADRU2

ADRU1

1
0

R

0
0
R

ADRU0

Figure 85 A/D Data Register Upper Digit (ADRU)

A/D Start Flag (ADSF: $020, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the

completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is
cleared. Refer to figure 86.

A/D start flag (ADSF: $020, bit 2)

Bit
Initial value
Read/Write
Bit name

Refer to the description of operating
modes

1
0

3
0

R/W

DTON

DTON

ADSF (A/D start flag)

A/D conversion started
A/D conversion completed

2
0

R/W

ADSF

Figure 86 A/D Start Flag (ADSF)

1
0

R/W

WDON

0
0

R/W

LSON

WDON

Refer to the description of timers

LSON

Refer to the description of operating
modes

96

HD404829R Series

Note on Use: Use the SEM and SEMD instructions to write data to the A/D start flag (ADSF: $020, bit 2),

but make sure that the A/D start flag is not written to during A/D conversion. Data read from the A/D data
register (ADRL: $017, ADRU: $018) during A/D conversion cannot be guaranteed.

The A/D converter does not operate in the stop, watch, and subactive modes because of the OSC clock.
During these low-power dissipation modes, current through the resistor ladder is cut off to decrease the
power input.

97

HD404829R Series

LCD Controller/Driver

The MCU has an LCD controller and driver which drive 4 common signal pins and 52 segment pins. The
controller consists of a RAM area in which display data is stored, a display control register (LCR: $01B),
and a duty-cycle/clock-control register (LMR: $01C) (figure 87).

Four duty cycles and the LCD clock are programmable, and a built-in dual-port RAM ensures that display
data can be automatically transmitted to the segment signal pins without program intervention. If a 32-kHz
oscillation clock is selected as the LCD clock source, the LCD can even be used in watch mode, in which
the system clock stops.

V

COM1

COM2

COM3

COM4

Common
signal
output
circuit

CC

V

1

V

2

V

3

GND

Internal LCD power supply switch

LCD power supply

control circuit

Pin control

4

LCD control

register

(LCR)

LCD output

register 1

(LOR1)

SEG1

SEG4

SEG5

SEG8

SEG9

SEG20

SEG21

SEG52

Segment

signal
output

circuit

Note: Pin function switching circuit

Clock

CL0

2

52

2

Selector

CL1

4

3

Display
control

Display data

Duty
selection

CL2

CL3

LCD output

register 2

(LOR2)

LCD output

register 3

(LOR3)

Internal data bus

Dual-port

display RAM

(52 digits)

2

LCD mode

register

(LMR)

Data bus
Clock line
Signal line

98

Figure 87 LCD Controller/Driver Block Diagram