Datasheet HD-15531 Datasheet (intersil)

TM

HD-15531

March 1997

Features

• Support of MIL-STD-1553

• Data Rate (15531B) . . . . . . . . . . . . . . . .2.5 Megabit/Sec

• Data Rate (15531). . . . . . . . . . . . . . . . .1.25 Megabit/Sec

• Variable Frame Length to 32 Bits

• Sync Identification and Lock-In

• Separate Manchester II Encode, Decode

• Low Operating Power . . . . . . . . . . . . . . . . . 50mW at 5V

Ordering Information

PACKAGE

PDIP

CERDIP

DESC (CERDIP)

TEMP. RANGE

(oC)

-40 to 85 -

-40 to 85

-55 to 125

1.25MBIT /SEC

HD1-15531-9 HD1-15531B-9

HD1-15531-8 HD1-15531B-8

59629054901MQA

59629054902MQA

2.5MBIT /SEC

HD3-15531B-9

HD1-15531

HD1-15531B

PKG.

NO.

E40.6

F40.6

CMOS Manc hester Enc od er - D ec od er

Description

The Intersil HD-15531 is a high performance CMOS device intended to service the requirements of MIL-STD-1553 and similar Manchester II encoded, time division multiplexed serial data protocols. This LSI chip is divided into two sections, an Encoder and a Decoder. These sections operate independentl y of each other, except for the master reset and word length functions. This circuit provides many of the requirements of MIL-STD-1553. The Encoder produces the sync pulse and the parity bit as well as the encoding of the data bits. The Decoder recog nizes the sync pul se and identifies it as well as decod ing the data bits and checking parity.

The HD-15531 also surpasses the requirements of MILSTD-1553 by allowing the word length to be programmable (from 2 to 28 data bits). A frame consists of three bits for sync followed by the data word (2 to 28 data bits) followed by one bit of parity, thus, the frame length will vary from 6 to 32 bit periods. This chip also allows selection of either even or odd parity for the Encoder and Decoder separately.

This integrated circuit is fully guaranteed to support the 1MHz data rate of MIL-STD-1553 o ver both temperatu re and voltage. For high speed applications the 15531B will support a 2.5 Megabit/sec data rate.

The HD-15531 can also be used in many party line digital data communications applications, such as a local area network or an environmental cont rol sys tem drive n from a single twisted pair of fiber optic cable throughout a buil ding.

| Intersil (and design) is a trademark of Intersil Americas Inc.

1

FN2961.1

Pinout

V

VALID WORD

TAKE DATA’

TAKE DATA

SERIAL DATA OUT

SYNCHR DATA

SYNCHR DATA SEL

SYNCHR CLK

DECODER CLK SYNCHR CLK SEL BIPOLAR ZERO IN

BIPOLAR ONE IN

UNIPOLAR DATA IN

DECODER SHIFT CLK

TRANSITION SEL

NC

COMMAND SYNC

DECODER PARITY SEL

DECODER RESET

COUNT C

HD-15531

HD-15531 (CERDIP, PDIP)

TOP VIEW

1

CC

2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

0

40 39 38 37 36 35 34

33 32 31 30 29 28 27 26 25 24 23 22 21

COUNT C

1

COUNT C

4

DATA SYNC ENCODER CLK COUNT C

3

NC ENCODER SHIFT CLK

SEND CLK IN SEND DATA ENCODER PARITY SEL SYNC SEL ENCODER ENABLE SERIAL DATA IN BIPOLAR ONE OUT OUTPUT INHIBIT BIPOLAR ZERO OUT

÷ 6 OUT

COUNT C2 MASTER RESET GND

Block Diagrams

GND

21

MASTER RESET

22

SEND CLK IN

33

÷ 6 OUT

24

ENCODER

37

CLK

BIT

COUNTER

20 40 23 36 39

C0C1C2C3C

÷ 6

ENDODER

V

CC

1

OUTPUT

INHIBIT

ENCODER

PARITY

SELECT

27

25

÷ 2

CHARACTER

FORMER

34 28 29 31

32

SEND DATA

4

ENCODER

SHIFT

CLK

SERIAL

DATA IN

ENCODER

ENABLE

30 SYNC

SELECT

26

BIPOLAR ONE OUT

BIPOLAR ZERO OUT

2

HD-15531

DECODER

7 8

DATA

SELECT

GATE

CLOCK

SELECT

DATA

DECODER

RESET

DATADATA SELECT

CHARACTER

IDENTIFIER

BIT

RATE

CLK

19

20 40 23 36 39

C

BIT

COUNTER

0C1C2C3C4

PARITY CHECK

4

17

5

2

16

14

3

UNIPOLAR

DATA IN

BIPOLAR

ONE IN

BIPOLAR

ONE IN

DECODER

CLK

DECODER

CLK SELECT

SYNCHRONOUS

CLK

CLK SELECT

MASTER

RESET

SYNCHRONOUS SYNCHRONOUS

13

12

TRANSITION

FINDER

11

9

SYNCHRONIZER

15

8

10

22

Pin Description

NUMBER TYPE NAME SECTION DESCRIPTION

TAKE DATA COMMAND SYNC

DATA SYNC SERIAL

DATA OUT VALID WORD

PARITY SELECT

DECODER SHIFT CLK

TAKE DATA’

1V

CC

Both Positi ve supp ly pi n. A 0 .1 µF decoupling capacitor from VCC (pin 1) to GROUND

(pin 21) is recommended.

2 O VALID WORD Decoder Output high indicates receipt of a valid word, (valid parity and no Manchester

errors).

3 O TAKE DATA’ Dec oder A continuous , fr ee ru nnin g si gnal prov ided for host timi ng o r d ata ha ndli ng. When

data is presen t on the bus, this signal will b e synchronized to the incoming data and will be identical to TAKE DATA.

4 O TAKE DATA Decoder Output is high du rin g rec ei pt of data af ter id ent if ica t ion of a va l id syn c pu lse an d

two va li d Ma nc he ster bits. 5 O SERIAL DATA OUT Decoder Delivers received data in correct NRZ format. 6 I SYNCHRONOUS

DATA

Decoder Input presents Manchester data directly to character identification logic.

SYNCHRONOUS DATA SELECT must be held high to use this input. If not

used, this pin must be held high. 7 I SYNCHRONOUS

DATA SELECT

8 I SYNCHRONOUS

CLOCK

Decoder In high state allows the synchronous data to enter the character identification

logic. Tie this in put low for asynchronous data.

Decoder Input provide s externally synchronized clock to th e decoder, for use whe n re-

ceiving synchronous data. This input must be tied high when not in us e. 9 I DE CO DE R CLOCK Decoder Input drives t he tra ns it ion fi n de r, a nd the syn ch ron iz er whi ch i n tur n su ppli es t he

clock to the balance of the decoder. Input a frequency equal to 12X the data rate.

10 I SYNCHRONOUS

CLOCK SELCT

Decoder In high state directs the SYNCHRONOUS CLOCK to control the decoder char-

acter ide ntification logic. A low state selects the DECODER CLOCK.

11 I BIPOLAR ZERO IN Decoder A high input should be applied when the bus is in its negative state. This pin must

be held high when the unipolar input is used.

12 I BIPOLA R ONE IN Decoder A high input s ho ul d b e ap pl ie d whe n t h e bus i s i n i ts posi t iv e s ta te. T his pi n mus t

he held low when the unipolar input is used.

13 I UNIPOLAR DATA IN Decoder With pin 11 high and pin 12 low, this pin enters unipolar data into the tr ansition

finder circuit. If not used this input must be held low.

3

HD-15531

Pin Description (Continued)

NUMBER TYPE NAME SECTION DESCRIPTION

14 O DECODER SHIFT

CLOCK

15 I TRANSITION SE-

LECT

16 NC Blank Not connected. 17 O COMMA N D SYNC Decode r O utput of a high from this pin occur s dur in g ou tput of deco de d data whi ch was

18 I DECODER PARITY

SELECT

19 I DECODE R RESET Dec oder A high input to t hi s p in dur i ng a risi n g ed ge of DEC ODE R SHI F T CLOC K r es ets

20 I COUNT C0 Both One of f iv e b inar y i np uts w hi ch esta bl is h t he to ta l b it co un t to b e en co de d or de -

21 GROUND Both Su pply pin. 22 I MASTER RESET Both A hi gh on this pin clears 2:1 counters in both encoder and decoder, and resets

Decoder Output which delivers a frequency (DECOD ER CLOCK + 1 2), synchronous by

the recovered serial data stream.

Decoder A high input to this pin causes the transition finder to synchron ize on every tran -

sition of input da ta. A low i nput causes the transition finder to synchronize only

on mid-bit transitions.

preceded by a Comma nd (or Status) synchronizing charac ter.

Decoder An input for parity sense, calling for even parity with input high and odd parity

with input low.

the decoder bit counting logic to a cond ition ready for a new word.

coded.

the ÷ 6 circu it.

23 I COUNT C2 Both See pin 20. 24 O 25 O BIPOLAR

26 I OUTPUT 27 O BIPOLAR

28 I SERIAL DATA IN Encoder Accepts a serial data stream at a data rate equal to ENCODER SHIFT CLOCK. 29 I ENCODER ENABLE Encoder A high on this pin initiates the encode c ycle. (Subject to the preceding cycl e be-

30 I SYNC SELE CT Encoder Ac tuates a Command sync for an input high and Data sync for an input low. 31 I ENCODER PARITY

32 O SEND DATA Encoder Is an active high output which enables the external source of serial data. 33 I SEND CLOCK IN Encoder Clock in pu t at a f req ue ncy e qu al t o th e da ta rat e X2, u su al ly dri ve n by ÷ 6 ou tp ut . 34 O ENCODER SHIFT

35 NC Blank Not connected. 36 I COUNT C3 Both See pin 20. 37 I ENCODER CLOCK Encoder Input to the 6:1 divider, a frequency eq ual to 12 times the data rate is usually

38 O DATA SY NC Deco de r O u tput of a high fro m this pin occurs durin g ou tp ut of de co de d data whi ch was

39 I COUNT C4 Both See pin 20. 40 I COUNT C1 Both See pill 20.

÷ 6 OUT Encoder Output from 6:1 divider which is driven by the ENCODER CLOCK.

ZERO

OUT

INHIBIT Encoder A low on th is pin forc es pin 25 and 27 high , the inactive stat es.

ONE OUT Encoder An active lo w out p ut desi gn ed to dri ve t he one o r pos iti ve s en se o f a bi pola r li ne

SELECT

CLOCK

Encoder An active low output designed to drive the zero or negative sense of a bipolar

line driver.

driver.

ing complete).

Encoder Sets transmit parity odd for a high input, even for a low input.

Encoder Output for shifting data into the Encoder. The Encoder samples SDI pin-28 on

the low-to-high transition of ESC.

input here.

preceded by a data synchronizing character.

4

Encoder Operation

HD-15531

The Encoder requires a single clock with a frequency of twice the desired data rate applied at the SEND CLOCK input. An auxiliary divide by six counter is provided on chip which can be utilized to produce the SEND CLOCK by dividing the DECODER CLOCK. The frame length is set by programming the COUNT inputs. Parity is selected by programming ENCODER PARITY SELECT high for odd parity or low f o r even pa rity .

The Encoder’s cycle begins when ENCODER ENABLE is high during a falling edge of ENCODER SHIFT CLOCK . This cycle lasts for one word length or K + 4 ENCODER SHIFT CLOCK periods, where K is the number of bits to be sent. At the next low-to-high transition of the ENCODER SHIFT CLOCK, a high SYNC SELECT input actuates a Command sync or a low will produce a Data sync for the word . When the Encoder is ready to accept data, the

2

SEND DATA output will go high for K ENCODER SHIFT CLOCK periods . During these K periods the data should

TIMING 0 1 2 3 4 5 6 7 N-3 N-2 N-1 NN-4

SEND CLOCK

ENCODER

SHIFT CLOCK

ENCODER

ENABLE

SYNC

SELECT

SEND

DATA

4

DON’T CARE

VALID

DON’T CARE

be clocked into the SERIAL DATA input with every high-tolow transition of the ENCODER SHIFT CLOCK - so it can be sampled on the low-to-high transition. After the sync and Manchester II encoded data are transmitted through the BIPOLAR adds on an additional bit with the parity for that word . If ENCODER ENABLE is held high continuously, consecutive words will be encoded without an interframe gap. ENCODER ENABLE must go low by time (as shown) to prevent a consecutive word from being encoded . At any time

1

a low on OUTPUT puts to a high state but will not affect the Encoder in any other way.

To abort the Encoder transmission, a positive pulse must be applied at MASTER RESET. Any time after or during this pulse, a low-to-high transition on SEND CLOCK clears the internal counters and initializes th e Encoder for a new word.

3 4

ONE and BIPOLAR ZERO outputs, the Encoder

5

INHIBIT input will force both bipolar out-

SERIAL

DATA IN

BIPOLAR ONE OUT

BIPOLAR

ZERO OUT

1ST HALF 2ND HALF MSB BIT K-1 BIT K-2 BIT K-3 BIT K-4

SYNC SYNC MSB BIT K-1

BIT K-1 BIT K-3 BIT K-4 BIT K-5 BIT 4BIT K-2MSB BIT 3 BIT 2 BIT 1

BIT K-2 BIT K-3 BIT K-4

FIGURE 1. ENCODER

Decoder Operation

To operate the Decoder asynchronously requires a single clock with a frequency of 12 times the desired data rate applied at the DECODER CLOCK input. To operate the Decoder synchronously requires a SYNCHRONOUS CLOCK at a frequency 2 times the data rate which is synchronized with the data at every high-to-low transition applied to the SYNCHRONOUS CLK input. The Manchester II coded data can be presented to the Decoder asynchronously in one of two ways. The BIPOLAR ONE and BIPOLAR ZERO inputs will accept data from a comparator sensed transformer coupled bus as specified in Military Spec

1553. The UNIPOLAR DATA input can only accept noninverted Manchester II coded data. (e.g., from BIPOLAR

ONE

PARITYBIT 1BIT 2BIT 3BIT 4

BIT 4 BIT 3 BIT 2 BIT 1

PARITY

4 5321

OUT on an Encoder through an inverter to Unipolar Data Input).

The Decoder is free running and continuously monitors its data input lines for a valid sync character and two valid Manchester data bits to start an output cycle. When a valid sync is recognized , the type of sync i s indicated by a high

1

level at either COMMAND SYNC or DATA SYNC output. If the sync character was a command sync the COMMAND SYNC output will go high and remain high for K SHIFT CLOCK periods , where K is the number of bits to be

3

2

received. If the sync character was a data sync, the DATA SYNC output will go high. The TAKE DATA output will go high and remain high - while the Decoder is transmit-

2 3

5

HD-15531

ting the decoded data through SERIAL DATA OUT. The decoded data available at SERIAL DATA OUT is in NRZ format. The DECODER SHIFT CLOCK is provided so that the decoded bits can get shifted into an external register on every low-to-high transition of this clock - . Note that

2 3

DECODER SHIFT CLOCK may adjust its phase up until the time that TAKE DATA goes high.

After all K decoded bits have been transmitted the data is

3

checked for parity. A high input on DECODER PARITY SELECT will set the Decoder to check for even parity or a low input will set the Decoder to check for odd parity. A high

TIMING

SYNCHRONOUS

CLOCK

DECODER

SHIFT

CLOCK

BIPOLAR

ONE IN

BIPOLAR

ZERO IN

012345678 N-3N-2N-1N

1ST HA LF

2ND HALF

SYNC SYNC

MSB

BITK-1

BITK-2

BITK-3

on VALID WORD output indicates a successful reception

4

of a word without any Manchester or parity errors. At this time the Decoder is looking for a new sync character to start another output sequence. VALID WORD will go low approximately K + 4 DECODER SHIFT CLOCK periods after it goes high, if not reset low sooner by a valid sync and two valid Manchester bits as shown .

1

At any time in the above sequence a high input on DECODER RESET during a low-to-high transition of DECODER SHIFT CLOCK will abort transmission and initialize the Decoder to start looking for a new sync character.

BITK-5

BITK-4

BITK-4 BIT K-5

BIT 3 BIT 2 PARITYBIT 1

BIT 2BIT 3 B I T 1 PARITY

TAKE DATA

COMMAND

SYNC

DATA SYNC

SERIAL

DATA OUT

VALID WORD

UNDEFINED

(MAY BE HIGH FROM PREVIOUS RECEPTION)

FIGURE 2. DECODER

BITK-1

MSB BITK-2 BITK-3 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1

3 421

6

Frame Counter

DATA BITS

26LLHLH 37LLHHL 4 8 LLHHH 5 9 LHLLL 610LHLLH 711LHLHL 812LHLHH

913LHHLL 10 14 L H H L H 11 15 L H H H L 12 16 LHHHH 13 17 H L L L L

FRAME LENGTH

(BIT PERIODS)

HD-15531

C

4

PIN WORD

C

3

C

2

C

1

C

0

14 18 H L L L H 15 19 H L L H L 16 20 H L L H H 17 21 H L H L L 18 22 H L H L H 19 23 H L H H L 20 24 H L H H H 21 25 H H L L L 22 26 H H L L H 23 27 H H L H L 24 28 H H L H H 25 29 H H H L L 26 30 H H H L H 27 31 H H H H L 28 32 HHHHH

NOTE:

1. The abov e tabl e de mo nstr a tes al l po ssi b le combin at i ons of frame len gt hs ra ng in g fr om 6 to 32 bi t s. The pi n wor d de scri be d he re is common to both the Encoder and Decoder.

7

VALID WORD

HD-15531

V

CC

TAKE DATA

SYNC DATA

SELECT

SYNC

CLOCK

DECODER

CLOCK

SYNC CLOCK

SELECT

BIPOLAR

ZERO IN

BIPOLAR

ONE IN

UNIPOLAR

DATA IN

TRANSITION

SELECT

COMMAND

SYNC

DECODER

PARITY SELECT

COUNT C

0

NC

AB CKH AB CK

7416474164

PARALLEL OUT

COUNT C

1

COUNT C

DATA SYNC

COUNT C

ENCODER

PARITY SEL.

SYNC

SELECT

ENCODER

ENABLE

BIPOLAR

ONE OUT

INHIBIT

OUTPUT BIPOLAR

ZERO OUT

COUNT C

MASTER

RESET

4

3

2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

NC

SH/LD SI

O

H

CK SH/LD CK

O

H

7416574165

PARALLEL IN

SI

FIGURE 3. HOW TO MAKE OUR MTU LOOK LIKE A MANCHESTER ENCODED UART

Typical Timing Diagrams for a Manchester Encoded UART

ENCODER ENABLE

SYNC SELECT

VALID

PARALLEL IN

BIPOLAR

ONE OUT

BIPOLAR ZERO OUT

SYNC MSB

LSB

FIGURE 4. ENCODER TIMING

P

PARITY

VALID

8

HD-15531

SYNC MSB

BIPOLAR ONE IN

BIPOLAR ZERO IN

COMMAND SYNC

PARALLEL OUT

VALID WORD

VALID VALID

FROM PREVIOUS

RECEPTION

FIGURE 5. DECODER TIMING

MIL-STD-1553

The 1553 Standard defines a time division multiplexed data bus for application within aircraft. The bus is defined to be bipolar, and encoded in a Manchester II format, so no DC component appears on the bus . This allows t ransfor mer coupling and excellent isolation among systems and their environment.

The HD-15531 supports the full bipolar configuration, assuming a bus driver configuration similar to that in Figure 1. Bipolar inputs from the bus, like Figure 2, are also accommodated.

The signaling format in MIL-STD-1553 is specified on the assumption that the network of 32 or fewer terminals are controlled by a central control unit by means of Command-

LSB

PARITY

P

Words, and Data. Terminals respond with St atus Words, and Data. Each word is preceded by a synchronizing puls e, and

followed by parity bit, occupying a total of 20µs. The word formats are shown in Figure 4. The special abbrevi atio ns are as follows:

P Parity, which is defined to be odd, taken across all

17 bits. R/T Receive on logical zero, transm it on ONE. ME Message Error if logical 1. TF Terminal Flag, if set, calls for controller to request

self-test data.

BUS

”

“1

“0”

FIGURE 6. SIMPLIFIED MIL-STD-1553 DRIVER FIGURE 7. SIMPLIFIED MIL-STD-1553 RECEIVER

+

“1” REF

“0” REF

+

“1”

“0

”

9

COMMAND

SYNC

DATA

SYNC

HD-15531

BIT

PERIOD

LOGICAL ONE DATA

LOGICAL ZERO DATA

BIT

PERIOD

BIT

PERIOD

FIGURE 8. MIL-STD-1553 CHARACTER FORMATS

0 1 2 3 4 5 6 7 8 9 10111213141516171819

COMMAND WORD (FROM CONTROLLER TO TERMINAL)

515 51

SYNC

DATA WORD (SENT EITHER DIRECTION)

TERMINAL

ADDRESS

R/T

SUB ADDRESS

/MODE

DATA WORD

COUNT

P

16

SYNC

STATUS WORD (FROM TERMINAL TO CONTROLLER)

51 9 11

TERMINAL

ADDRESS

DATA WORD

CODE FOR FAILURE MODES PSYNC TF

FIGURE 9. MIL-STD-1553 WORD FORMATS

NOTE:

1. This page is a summa ry of MIL-S TD-1553 and is not intended to describ e the operation of the HD-15531.

10

1

P

HD-15531

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V

Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to V

CC

+0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating C o ndi t io ns

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range (T

HD-15531-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40

HD-15531-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55

Encoder/Decoder Clock Rise Time (TECR, TDCR). . . . . . .8ns Max

Encoder/Decoder Clock Fall Time (TECF, TDCF) . . . . . . . .8ns Max

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

)

A

o

C to +85oC

o

C to +125oC

Thermal Resistance (Typical) θ

CERDIP Package . . . . . . . . . . . . . . . . . . 35oC/W 9oC/W

PDIP Package . . . . . . . . . . . . . . . . . . . . . 50

JA

o

C/W N/A

Storage Temperature Range . . . . . . . . . . . . . . . . .-65

Maximum Junction Temperature

Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175

Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300

θ

JC

o

C to +150oC

o o o

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Gates

Sync. Transition Span (TD2). . . . . . . . . . . 18 TDC Typical, (Note 1)

Short Data Transition Span (TD4). . . . . . . . 6 TDC Typical, (Note 1)

Long Data Transition Span (TD5) . . . . . . . 12 TDC Typical, (Note 1)

C C C

DC Electrical Specifications V

= 5.0V ±10%, TA = -40oC to +85Co (HD-15531-9)

CC

PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS

Input LOW Voltage V Input HIGH Voltag e V Input LOW Clo ck Voltage V Input HIGH Cl ock Voltage V Outp ut LO W Volt a ge V Output HIGH Voltage V Input Leakage Cu rrent I Standby Supply Current I

CCSB

IL

IH

ILC

IHC

OL

OH

I

VCC = 4.5V and 5.5V - 0.2 V VCC = 4.5V and 5.5V 0.7 V VCC = 4.5V and 5.5V - GND +0.5 V VCC = 4.5V and 5.5V VCC -0.5 - V IOL = +1.8mA, VCC = 4.5V (Note 2) - 0.4 V IOH = -3.0mA, VCC = 4.5V (Note 2) 2.4 - V VI = VCC or GND, VCC = 5.5V -1.0 +1.0 µA VIN = V

Outputs Open

Operating Power Supply Current ICCOP V

Outputs Open

Functional Test F

T

(Note 3) - - -

NOTES:

1. TDC = Decoder clock period = 1/FDC.

2. Interchanging of force and sense conditions is permitted.

3. Tested as follows: f = 15MHz, V

= 70% VCC, VIL = 20% VCC, CL= 50pF, VOH ≥ VCC/2 and VOL ≤ VCC/2.

IH

= -55oC to +125Co (HD-15531-8)

T

A

= 5.5V,

CC

= VCC = 5.5V, f = 15MHz,

IN

V

CC

-V

-2mA

-10mA

Capacitance T

= +25oC, Frequency = 1MHz

A

SYMBOL PARAMETER TYP UNITS TEST CONDITIONS

C

IN

OUT

Input C ap ac itance 25 p F All me asurem en ts ar e ref e re nc ed to devic e G ND

Output Capacitance 25 pF

11

HD-15531

AC Electrical Specifications V

= 5V ±10%, TA = -40oC to +85oC (HD-15530-9)

CC

T

= -55oC to +125oC (HD-15530-8)

A

HD-15531 HD-15531B

SYMBOL PARAMETER

UNITS TEST CONDITIONS (NOTE 2)MIN MAX MIN MAX

ENCODER TIMING

FEC Encoder Clo ck Fr eq ue nc y - 15 - 30 MHz V

FESC Send Clock Frequency - 2.5 - 5.0 MHz V

FED En coder Data Rate - 1.25 - 2.5 MHz V TMR Master Reset Pulse Width 150 - 150 - ns V

TE1 Shift Clock Delay - 125 - 80 ns V TE2 Serial Data Setu p 75 - 50 - n s V TE3 Serial Data Hold 75 - 50 - ns V TE4 Enab le Setup 90 - 90 - ns V TE5 Enab le Pulse W idth 100 - 100 - ns V TE6 Sync Setup 55 - 55 - ns V TE7 Sync Pulse Width 150 - 150 - ns V TE8 Send Data Delay 0 50 0 50 ns V

TE9 Bipolar Output Delay - 130 - 130 ns V TE10 Enable Hold 10 - 10 - ns V TE11 Sync Hold 95 - 95 - ns V

DECODER TIMING

FDC Decoder Clock Frequency - 15 - 30 MHz V FDS Decoder Sync Clock - 2.5 - 5.0 MHz V FDD Decoder Data Rate - 1.25 - 2.5 MHz V

TDR Decoder R eset Pulse Width 150 - 150 - ns V TDRS Decoder Reset Setup Time 75 - 75 - ns V TDRH Decoder Reset Hold Time 10 - 10 - ns V

TMR Master Reset Pulse 150 - 150 - ns V

TD1 B ipolar Data Pulse Width TDC + 10

(Note 1 )

TD3 One Zero Over l ap - TDC - 10

- TDC + 10

(Note 1 )

-nsV

- TDC - 10 (Note 1 )

TD6 Sync Delay (ON) -2 0 110 -20 110 ns V TD7 Take Data Delay (ON) 0 110 0 110 ns V TD8 Serial Data Out Delay - 80 - 80 ns V

TD9 Sync Delay (OFF) 0 110 0 110 ns V TD10 Take Data Delay (OFF) 0 110 0 110 ns V TD11 V a li d Word Delay 0 11 0 0 11 0 ns V TD12 Sync Clock to S hift Clock

-75-75nsV

Delay

TD13 Syn c Data Setu p 75 - 75 - ns V

NOTES:

1. TDC = Decoder clock period = 1/FDC.

2. AC Testing as follows: Input levels: V levels: V

/2; Output load: CL = 50pF.

CC

= 70% VCC, VIL = 20% VCC; Input rise/fall times driven at 1ns/V; Timing Reference

IH

ns V

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

= 4.5V and 5.5V, CL = 50pF

CC

12

Timing Waveforms

SEND CLOCK

ENCODER SHIFT CLOCK

HD-15531

T

E1

T

E2

T

E3

SERIAL DATA IN

SEND CLOCK

ENCODER SHIFT CLOCK

ENCODER ENABLE

SYNC SELECT

ENCODER SHIFT CLOCK

SEND DATA

SEND CLOCK

BIPOLAR

ONE OUT OR

BIPOLAR

ZERO OUT

VALID

T

E1

T

E4

T

E5

T

E8

T

E10

T

E11

T

E6

VALID

T

E7

T

E9

FIGURE 10. ENCODER TIMING

13

Timing Waveforms (Continued)

BIT PERIOD BIT PERIOD BIT PERIOD

BOI

BZI

BOI

BZI

T

D1

T

D2

COMMAND SYNC

T

D2

T

D1

DATA SYNC

HD-15531

NOTE: UNIPOLAR IN = 0, FOR NEXT DIAGRAMS.

T

D3

T

D1

T

D2

T

D1

T

D3

T

D2

T

D3

T

D3

BOI

BZI

T

D1

T

D3

T

D4

T

D3

T

D2

T

D5

T

D1

T

D3

T

D5

T

D3

T

D1

T

D4

T

D3

ONEONE ZERO

NOTE: BIPOLAR ONE IN = 0, BIPOLAR ZERO IN = 1, FOR NEXT DIAGRAMS.

T

UI

D2

T

D2

COMMAND SYNC

UI

T

D2

T

D2

DATA SYNC

UI

T

D4

T

D5

T

D5

T

D4

T

D4

ZERO ONE ONEONE

FIGURE 11. DECODER TIMING

14

Timing Waveforms (Continued)

DECODER SHIFT CLOCK

COMMAND/DATA

DECODER SHIFT CLOCK

SERIAL DATA OUT

DECODER SHIFT CLOCK

COMMAND/DATA

SYNC

TAKE DATA

SYNC

TAKE DATA

HD-15531

T

D6

T

D7

T

D8

DATA BIT

T

D10

T

D9

T

D10

VALID WORD

DECODER SHIFT CLOCK

DECODER RESET

SYNCHRONOUS

CLOCK IN

DECODER SHIFT

CLOCK

SYNCHRONOUS

CLOCK IN

SYNCHRONOUS

DATA IN

T

D11

T

DRS

T

DR

T

DRH

SYNCHRONOUS INPUT (WITH EXTERNAL BIT SYNCHRONIZATION)

T

D12

T

D13

T

D13

MANCHESTER

PHASES

T

D13

T

D13

FIGURE 12. DECODER TIMINGS

15

HD-15531

Test Load Circuit

DUT

(NOTE 1)

C

L

FIGURE 13.

NOTE:

1. Includes stray and jig capacitance.

AC Testing Input, Output Waveform

INPUT

V

IH

50% 50%

V

IL

FIGURE 14.

NOTE:

1. AC Testing: All input signals must switch between V input rise and f all times are driven at 1ns per volt.

OUTPUT

V

OH

V

OL

and VIH,

IL

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