Datasheet HCTS160T Datasheet (Intersil Corporation)

HCTS160T

Data Sheet July 1999 File Number

Radiation Hardened Synchronous
Counter

Intersil’sSatellite Applications FlowTM(SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.

The Intersil HCTS160T is a Radiation Hardened High Speed
Presettable BCD Decade Synchronous Counter that
features an asynchronous reset and look-ahead carry logic.
Counting and parallel presetting are accomplished
synchronously with the low-to-high transition of the clock. A
low level on the synchronous parallel enable input,

SPE,
disables counting and allows data at the preset inputs, P0 ­P3, to be loaded into the counter. The counter is reset by a
low on the master reset input,

MR. Two count enables, PE
and TE are providedfor n-bit cascading. TE also controls the
terminal count output, TC. The terminal count output
indicates a maximum count for one clock pulse and is used
to enable the next cascaded stage to count.

Specifications

Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.

Detailed Electrical Specifications for the HCTS160T are
contained in SMD 5962-95742. A “hot-link” is provided from
our website for downloading.
www.intersil.com/spacedefense/ne wsafc lasst.asp

Intersil‘s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.

www.intersil.com/quality/manuals.asp

4626.1

Features

• QML Class T, Per MIL-PRF-38535

• Radiation Performance

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- Gamma Dose (γ) 1 x 10

RAD(Si)

- Latch-Up Free Under Any Conditions

- SEP Effective LET No Upsets: >100 MEV-cm

- Single Event Upset (SEU) Immunity < 2 x 10

2

/mg

-9

Errors/Bit-Day (Typ)

• 3 Micron Radiation Hardened SOS CMOS

• Fanout (Over Temperature Range)

- Standard Outputs 10 LSTTL Loads

• Significant Power Reduction Compared to LSTTL ICs

• DC Operating Voltage Range: 4.5V to 5.5V

• LSTTL Input Compatibility

-V

= 0.8V Max

IL

-V

= V

IH

• Input Current Levels Ii ≤ 5mA at V

CC/2

Min

OL

, V

OH

Pinouts

HCTS160DTR (SBDIP), CDIP2-T16

TOP VIEW

16

MR

CP

P0
P1
P2
P3

PE

GND

1
2
3
4
5
6
7
8

V

CC

15

TC

14

Q0

13

Q1

12

Q2
Q3

11
10

TE

9

SPE

Ordering Information

TEMP.

ORDERING

NUMBER PART NUMBER

5962R9574201TEC HCTS160DTR -55 to 125
5962R9574201TXC HCTS160KTR -55 to 125

NOTE:

Minimumorderquantity for -T is 150 units through

distribution, or 450 units direct.

1

RANGE

(oC)

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

HCTS160KTR (FLATPACK), CDFP4-F16

TOP VIEW

MR

CP

P0
P1
P2
P3

PE

GND

www.intersil.com or 407-727-9207

Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.

116
2
3
4
5
6
7
8

15
14
13
12
11
10

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| Copyright © Intersil Corporation 1999

V

CC

TC
Q0
Q1
Q2
Q3
TE
SPE

Functional Diagram

HCTS160T

SPE

MR

CP

PE

TE

3456

Q2 Q3

Q0 Q1

MR
D2
T2
CP

Q2

P

Q0Q1Q2

Q0 Q3

GND V

CC

MR
D0
T0
CP

Q3 Q0 Q3 Q0

P

Q0
Q0

MR
D1
T1
CP

P

Q1

P3P2P1P0

Q3
Q0

P

Q3 Q3

MR
D3
T3
CP

168

14 15

Q0

TC

Q1

13

Q0

12

11

Q1

TRUTH TABLE

INPUTS OUTPUTS

OPERATING MODE

MR CP PE TE SPE Pn Qn TC

Reset (Clear) L X X X X X L L
Parallel Load H X X l l L L

H X X l h H (Note 1)
Count H h h h (Note 3) X Count (Note 1)
Inhibit H X l (Note 2) X h (Note 3) X qn (Note 1)

H X X l (Note 2) h (Note 3) X qn L

H = HIGH voltage level.
L = LOW voltage level.
h = HIGH voltage level one setup time prior to the LOW-to-HIGH clock transition.
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.
X = Immaterial.
q = Lower case letter indicate the state of the referenced output prior to the LOW-to-HIGH clock transition.

= LOW-to-HIGH clock transition.

NOTES:

1. The TC output is HIGH when TE is HIGH and the counter is at terminal count (HHHH for 161 and HLLH for 160).

2. The HIGH-to-LOW transition of PE or TE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation.

3. The LOW-to-HIGH transition of SPE on the 54/74161 and 54/74160 should only occur while CP is high for conventional operation.

2

Die Characteristics

HCTS160T

DIE DIMENSIONS:

(2642µm x 2184µm x 533µm ±51.0µm)
104 x 86 x 21mils ±2mil

METALLIZATION:

Type: Al Si
Thickness: 11.0k

Å ±1kÅ

SUBSTRATE POTENTIAL:

Unbiased Silicon on Sapphire

BACKSIDE FINISH:

Sapphire

Metallization Mask Layout

P0 (3)

P1 (4)

CD
(2)

HCTS160T

MR

(1)

PASSIVATION:

Type: Silox (S
Thickness: 13.0k

)

iO2

Å ±2.6kÅ

WORST CASE CURRENT DENSITY:

< 2.0e5 A/cm

2

TRANSISTOR COUNT:

676

PROCESS:

CMOS SOS

V

CC

(16)

(15) TC

(14) Q0

(13) Q1

P2 (5)

(12) Q2

P3 (6)

(11) Q3

PE (7)

(8) (9)

GND

SPE

NOTE: The die diagramis a generic plot from a similar HCS device.It is intended to indicate approximate die size and bond pad location. The mask

series for the HCTS160 is TA14445A.

(10)

TE

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However ,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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