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HCS373T
Data Sheet July 1999 File Number
Radiation Hardened Octal Transparent
Latch, Three-State
Intersil’sSatellite Applications FlowTM(SAF) devices are fully
tested and guaranteed to 100kRAD total dose. These QML
Class T devices are processed to a standard flow intended
to meet the cost and shorter lead-time needs of large
volume satellite manufacturers, while maintaining a high
level of reliability.
The Intersil HCS373T is a Radiation Hardened Octal
Transparent Three-State Latch with an active-low output
enable. The HCS373T utilizes advanced CMOS/SOS
technology. The outputs are transparent to the inputs when
the Latch Enable (
goes LOW, the data is latched. The Output Enable (
LE) is HIGH. When the Latch Enable (LE)
OE)
controls the three-state outputs. When the Output Enable
(
OE) is HIGH, the outputs are in the high impedance state.
The latch operation is independent of the state of the Output
Enable.
Specifications
Specifications for Rad Hard QML devices are controlled by
the Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.
Detailed Electrical Specifications for the HCS373T are
contained in SMD 5962-95792. A “hot-link” is provided from
our website for downloading.
www.intersil.com/spacedefense/ne wsafc lasst.asp
Intersil’s Quality Management Plan (QM Plan), listing all
Class T screening operations, is also available on our
website.
www.intersil.com/quality/manuals.asp
4617.1
Features
• QML Class T, Per MIL-PRF-38535
• Radiation Performance
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- Gamma Dose (γ) 1 x 10
RAD(Si)
- Latch-Up Free Under Any Conditions
- SEP Effective LET No Upsets: >100 MEV-cm
- Single Event Upset (SEU) Immunity < 2 x 10
2
/mg
-9
Errors/Bit-Day (Typ)
• 3 Micron Radiation Hardened CMOS SOS
• Significant Power Reduction Compared to LSTTL ICs
• DC Operating Voltage Range: 4.5V to 5.5V
• Input Logic Levels
-VIL = 0.3 VCC Max
-V
= 0.7 VCC Min
IH
• Input Current Levels Ii ≤ 5mA at V
OL
, V
OH
Pinouts
HCS373DTR (SBDIP), CDIP2-T20
TOP VIEW
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
1
2
3
4
5
6
7
8
9
10
V
20
CC
Q7
19
D7
18
D6
17
Q6
16
Q5
15
D5
14
D4
13
12
Q4
11
LE
Ordering Information
TEMP.
ORDERING
NUMBER PART NUMBER
5962R9579201TRC HCS373DTR -55 to 125
5962R9579201TXC HCS373KTR -55 to 125
NOTE:
Minimumorderquantity for -T is 150 units through
distribution, or 450 units direct.
1
RANGE
(oC)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
HCS373KTR (FLATPACK), CDFP4-F20
TOP VIEW
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
www.intersil.com or 407-727-9207
Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.
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| Copyright © Intersil Corporation 1999
V
Q7
D7
D6
Q6
Q5
D5
D4
Q4
LE
CC
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Functional Diagram
1 OF 8
(3, 4, 7, 8, 13,
14, 17, 18)
D
LE
(11)
OE
(1)
OE LE D Q
COMMON CONTROLS
HCS373T
LATCH
DQ
LE
TRUTH TABLE
OE
Q
(2, 5, 6, 9, 12,
15, 16, 19)
LHHH
LHLL
LLIL
LLhH
HXXZ
H = High Level, L = Low Level.
X = Immaterial, Z = High Impedance.
I = Low voltage level prior to the high-to-low latch enable transition.
h = High voltage level prior to the high-to-low latch enable transition.
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Die Characteristics
HCS373T
DIE DIMENSIONS:
(2747µm x 2693µm x 533µm ±51.0µm)
108 x 106 x 21mils ±2mil
METALLIZATION:
Type: Al Si
Thickness: 11k
Å ±1kÅ
SUBSTRATE POTENTIAL:
Unbiased Silicon on Sapphire
BACKSIDE FINISH:
Sapphire
Metallization Mask Layout
D1 (4)
D0
(3)
Q0
(2)
HCS373T
OE
(1)
PASSIVATION:
Type: Silox (S
Thickness: 13k
)
iO2
Å ±2.6kÅ
WORST CASE CURRENT DENSITY:
< 2.0e5 A/cm
2
TRANSISTOR COUNT:
376
PROCESS:
CMOS SOS
V
(20)
CC
Q7
(19)
(18) D7
Q1 (5)
Q2 (6)
D2 (7)
(12)
(9)
(8) (11)
Q3
NOTE: The die diagram is a generic plot from a similar HCS device. It is intended to indicate approximate die size and bond pad location. The
mask series for the HCS373 is TA14303A.
(10)
GND
Q4
(13)
D4
(17) D6
(16) Q6
(15) Q5
(14) D5
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However ,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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