Datasheet HCPL-0601, HCPL-0600 Datasheet (Fairchild Semiconductor)

Lead Coplanarity : 0.004 (0.10) MAX

0.202 (5.13)

Pin 1

0.019 (0.48)

0.182 (4.63)

0.021 (0.53)

0.011 (0.28)

0.050 (1.27)
TYP

0.244 (6.19)

0.224 (5.69)

0.143 (3.63)

0.123 (3.13)

0.008 (0.20)

0.003 (0.08)

0.010 (0.25)

0.006 (0.16)

SEATING PLANE

0.164 (4.16)

0.144 (3.66)

HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

HCPL-0600 HCPL-0601

DESCRIPTION

The HCPL-0600/0601optocouplers consist of a 870 nm AlGaAS LED, optically coupled to a very high speed integrated photo­detector logic gate with a strobable output. The devices are housed in a compact small-outline package. This output features an
open collector, thereby permitting wired OR outputs. The coupled parameters are guaranteed over the temperature range of -40°C
to +85°C. A maximum input signal of 5 mA will provide a minimum output sink current of 13 mA (fan out of 8). An internal noise
shield provides superior common mode rejection of typically 10 kV/µs.

FEATURES

• Compact SO8 package

•Very high speed-10 MBit/s

• Superior CMR-10 kV/µs

•Fan-out of 8 over -40°C to +85°C

• Logic gate output

• Strobable output

• Wired OR-open collector

•U.L. recognized (File # E90700)

PACKAGE DIMENSIONS

APPLICATIONS

• Ground loop elimination

• LSTTL to TTL, LSTTL or
5-volt CMOS

• Line receiver, data transmission

• Data multiplexing

• Switching power supplies

• Pulse transformer replacement

• Computer-peripheral interface

N/C

1

+

2

V

F

_

3

N/C

4 5

Single-channel

circuit drawing

V

8

CC

V

7

E

V

6

O

GND

NOTE

All dimensions are in inches (millimeters)

TRUTH TABLE

(Positive Logic)

Input Enable Output

HHL

LHH

HLH

LLH

A 0.1 µF bypass capacitor must be connected between pins 8 and 5. (See note 1)

HNCL

LNCH

© 2003 Fairchild Semiconductor Corporation

Page 1 of 12

4/10/03

HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

HCPL-0600 HCPL-0601

ABSOLUTE MAXIMUM RATINGS

(No derating required up to 85°C)

Parameter Symbol Value Units

Storage Temperature T

Operating Temperature T

Lead Solder Temperature T

EMITTER

DC/Average Forward Input Current I

Enable Input Voltage
Not to exceed VCC by more than 500 mV

Reverse Input Voltage V

Power Dissipation P

DETECTOR

Supply Voltage

V

(1 minute max)

Output Current I

Output Voltage V

Collector Output Power Dissipation P

RECOMMENDED OPERATING CONDITIONS

STG

OPR

SOL

F

V

E

R

CC

O

O

O

-55 to +125 °C

-40 to +85 °C

260 for 10 sec °C

50 mA

5.5 V

5.0 V

I

45 mW

7.0 V

50 mA

7.0 V

85 mW

Parameter Symbol Min Max Units

Input Current, Low Level I

Input Current, High Level I

Supply Voltage, Output V

Enable Voltage, Low Level V

Enable Voltage, High Level V

Operating Temperature T

FL

FH

CC

EL

EH

A

0 250 µA

*6.3 15 mA

4.5 5.5 V

0 0.8 V

2.0 V

CC

V

-40 +85 °C

Fan Out (TTL load) N 8

*6.3 mA is a guard banded value which allows for at least 20% CTR degradation. Initial input current threshold value is 5.0 mA or
less

© 2003 Fairchild Semiconductor Corporation

Page 2 of 12

4/10/03

HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

HCPL-0600 HCPL-0601

ELECTRICAL CHARACTERISTICS

(T

= -40°C to +85°C Unless otherwise specified.)

A

INDIVIDUAL COMPONENT CHARACTERISTICS

Parameter Test Conditions Symbol Min Typ** Max Unit

EMITTER

Input Forward Voltage T
Input Reverse Breakdown Voltage (I
Input Capacitance (V
Input Diode Temperature Coefficient (I

= 10 mA)

(I

F

=25°C 1.75

A

= 10 µA) B

R

= 0, f = 1 MHz) C

F

= 10 mA) ∆ VF/ ∆ TA -1.4 mV/°C

F

V

F

VR

IN

5.0 V
60 pF

DETECTOR

High Level Supply Current

Low Level Supply Current

Low Level Enable Current (V
High Level Enable Current (V
High Level Enable Voltage (V
Low Level Enable Voltage (V

= 5.5 V, I

CC

SWITCHING CHARACTERISTICS

= 5.5 V, I

CC

(V

= 5.5 V, I

CC

= 5.5 V, V

CC

= 5.5 V, V

CC

= 5.5 V, I

CC

= 10 mA) (Note 2) V

F

(T

= -40°C to +85°C, V

A

= 0 mA)

F

(V

= 0.5 V)

E

= 10 mA)

F

(V

= 0.5 V)

E

= 0.5 V) I

E

= 2.0 V) I

E

= 10 mA) V

F

= 5 V, I

CC

I

CCH

I

CCL

710mA

913mA

EL

EH

EH

EL

2.0 V

= 7.5 mA Unless otherwise specified.)

F

-0.8 -1.6 mA

-0.6 -1.6 mA

(V

AC Characteristics Test Conditions Device Symbol Min Typ Max Unit

Propagation Delay Time
to Output High Level

(R

Propagation Delay Time
to Output Low Level

(R
Pulse Width Distortion (R
Output Rise Time

(10-90%)
Output Fall Time

(90-10%)
Enable Propagation

Delay Time
to Output High Level

Enable Propagation
Delay Time
to Output Low Level

Common Mode
Tr ansient Immunity

(I

= 0 mA, V

F

(R

= 350 Ω ) (T

L

(at Output High Level)
Common Mode

Tr ansient Immunity

(I

(R

= 350Ω) (TA =25°C)

= 7.5 mA, VOL (Max.) = 0.8 V)

F

L

(at Output Low Level)

(Note 3) (T

= 350 Ω , C

L

= 15 pF) (Fig. 12) 100

L

(Note 4) (T

= 350 Ω , C

L

= 350 Ω , C

L

= 15 pF) (Fig. 12) 100

L

= 15 pF) (Fig. 12) All |T

L

(R

= 350 Ω , C

L

(Note 5) (Fig. 12)

= 350 Ω , C

(R

L

(Note 6) (Fig. 12)

(I

= 7.5 mA, V

F

(R

= 350 Ω , C

L

(Note 7) (Fig. 13)

(I

= 7.5 mA, V

F

(R

= 350 Ω , C

L

(Note 8) (Fig. 13)

=25°C)

A

(Min.) = 2.0 V)

OH

(Note 9)(Fig. 14)

(Note 10)(Fig. 14)

=25°C)

A

=25°C)

A

= 15 pF)

L

= 15 pF)

L

= 3.5 V)

EH

= 15 pF)

L

= 3.5 V)

EH

= 15 pF)

L

|V

| = 10 V HCPL-0600

CM

|V

| = 50 V HCPL-0601 5000 10,000

CM

| = 10 V HCPL-0600

|V

CM

|V

| = 50 V HCPL-0601 5000 10,000

CM

All T

All T

PHL

All t

All t

All t

All t

|CM

|CM

PLH

PHL

-T

r

f

ELH

EHL

H

H

20 45 75

25 45 75

|335ns

PLH

|

|

1.8

0.8 V

50 ns

12 ns

20 ns

20 ns

10,000

10,000

V

ns

ns

V/µs

V/µs

© 2003 Fairchild Semiconductor Corporation

Page 3 of 12

4/10/03

HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

HCPL-0600 HCPL-0601

TRANSFER CHARACTERISTICS (T

= -40°C to +85°C Unless otherwise specified.)

A

DC Characteristics Test Conditions Symbol Min Typ** Max Unit

= 5.5 V, VO = 5.5 V)

(V

High Level Output Current

Low Level Output Voltage

(I

= 250 µA, VE = 2.0 V) (Note 2)

F

(V

= 2.0 V, IOL = 13 mA) (Note 2)

E

Input Threshold Current

ISOLATION CHARACTERISTICS (T

CC

= 5.5 V, IF = 5 mA)

(V

CC

= 5.5 V, VO = 0.6 V,

(V

CC

V

= 2.0 V, IOL = 13 mA)

E

= -40°C to +85°C Unless otherwise specified.)

A

I

OH

V

OL

I

FT

100 µA

.35 0.6 V

35mA

Characteristics Test Conditions Symbol Min Typ** Max Unit

(Relative humidity = 45%)
Input-Output
Insulation Leakage Current

(T

= 25°C, t = 5 s)

A

(V

= 3000 VDC)

I-O

I

I-O

1.0* µA

(Note 11)

Withstand Insulation Test Voltage

Resistance (Input to Output) (V

Capacitance (Input to Output) (f = 1 MHz) (Note 11) C

(RH < 50%, TA = 25°C)

(Note 11) ( t = 1 min.)

= 500 V) (Note 11) R

I-O

V

ISO

I-O

I-O

2500 V

12

10

0.6 pF

** All typical values are at VCC = 5 V, TA = 25°C

RMS

Ω

NOTES

1. The V
tantalum capacitor with good high frequency characteristic and should be connected as close as possible to the package V
and GND pins of each device.

2. Enable Input - No pull up resistor required as the device has an internal pull up resistor.

3. t

PLH

1.5V level on the LOW to HIGH transition of the output voltage pulse.

4. t

PHL

1.5V level on the HIGH to LOW transition of the output voltage pulse.

5. t

r

6. t

f

7. t

ELH

to the 1.5V level on the LOW to HIGH transition of the output voltage pulse.

8. t

EHL

to the 1.5V level on the HIGH to LOW transition of the output voltage pulse.

9. CM
V

10. CM
(i.e., V

11. Device considered a two-terminal device: Pins 1,2,3 and 4 shorted together, and Pins 5,6,7 and 8 shorted together.

© 2003 Fairchild Semiconductor Corporation

supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic or solid

CC

- Propagation delay is measured from the 3.75 mA level on the HIGH to LOW transition of the input current pulse to the

- Propagation delay is measured from the 3.75 mA level on the LOW to HIGH transition of the input current pulse to the

- Rise time is measured from the 90% to the 10% levels on the LOW to HIGH transition of the output pulse.

- Fall time is measured from the 10% to the 90% levels on the HIGH to LOW transition of the output pulse.

- Enable input propagation delay is measured from the 1.5V level on the HIGH to LOW transition of the input voltage pulse

- Enable input propagation delay is measured from the 1.5V level on the LOW to HIGH transition of the input voltage pulse

- The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e.,

H

> 2.0 V). Measured in volts per microsecond (V/µs).

OUT

- The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state

L

< 0.8 V). Measured in volts per microsecond (V/µs).

OUT

Page 4 of 12

CC

4/10/03

HCPL-0600 HCPL-0601

TYPICAL PERFORMANCE CURVES

HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

Fig. 1 Forward Current vs. Input Forward Voltage

1000

TA = 25˚C

100

10

1

- FORWARD CURRENT (mA)

0.1

F

I

0.01

1.100 1.200 1.300 1.400 1.500 1.600

VF - FORWARD VOLTAGE (V)

Fig. 3 Input Threshold Current vs. Temperature

6

VCC = 5.0 V

= 0.6 V

V

O

5

4

RL = 350 Ω

Fig. 2 Output Voltage vs. Forward Current

6

5

4

3

2

- OUTPUT VOLTAGE (V)

o

V

1

RL = 1 kΩ

0

0123456

I

- FORWARD INPUT CURRENT (mA)

F

RL = 350 Ω

Vcc = 5 V

= 25 ˚C

T

A

Fig. 4 High Level Output Current vs. Temperature

8

6

3

2

RL = 1 kΩ

1

- INPUT THRESHOLD CURRENT (mA)

TH

I

0

-60 -40 -20 0 20 40 60 80 100

TA - TEMPERATURE (˚C) TA - TEMPERATURE (˚C)

© 2003 Fairchild Semiconductor Corporation

Page 5 of 12

4

VCC = 5.5 V

= 5.5 V

V

O

= 2.0 V

2

V

E

= 250 µA

I

F

- HIGH LEVEL OUTPUT CURRENT (µA)

OH

I

0

-60 -40 -20 0 20 40 60 80 100

4/10/03

HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

HCPL-0600 HCPL-0601

Fig. 5 Low Level Output Voltage vs. Temperature

0.8

VCC = 5.5 V

0.7

0.6

0.5

0.4

0.3

0.2

- LOW LEVEL OUTPUT VOLTAGE (V)

0.1

OL

V

0.0

= 2.0 V

V

E

= 5.0 mA

I

F

IO = 12.8 mA

IO = 9.6 mA

-60 -40 -20 0 20 40 60 80 100

IO = 16 mA

IO = 6.4 mA

TA - TEMPERATURE (˚C)

Fig. 7 Propagation Delay vs. Temperature Fig. 8 Propagation Delay vs. Pulse Input Current

100

VCC = 5.0 V

= 7.5 mA

I

F

80

60

40

20

- PROPAGATION DELAY (ns)

P

T

0

-60 -40 -20 0 20 40 60 80 100

t

= 1 kΩ

PLH, RL

t

= 350 Ω

PLH, RL

t

= 350 Ω, 1 kΩ

PHL, RL

- TEMPERATURE (˚C)

T

A

Fig. 6 Low Level Output Current vs. Temperature

70

VCC = 5.0 V

= 2.0 V

V

E

= 0.6 V

V

OL

60

IF = 10-15 mA

50

40

30

- LOW LEVEL OUTPUT CURRENT (mA)

OL

I

20

-60 -40 -20 0 20 40 60 80 100

120

VCC = 5.0 V

= 25˚C

T

A

105

90

75

60

- PROPAGATION DELAY (ns)

P

T

45

t

= 350 Ω, 1 kΩ

PHL, RL

30

5791113 15

I

- PULSE INPUT CURRENT (mA)

F

IF = 5 mA

T

- TEMPERATURE (˚C)

A

t

= 1 kΩ

PLH, RL

t

= 350 Ω

PLH, RL

© 2003 Fairchild Semiconductor Corporation

Page 6 of 12

4/10/03

HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

HCPL-0600 HCPL-0601

Fig. 9 Typical Enable Propagation Delay vs. Temparature

90

Vcc = 5.0 V

= 3.0 V

V

EH

= 0 V

V

EL

= 7.5 mA

I

F

60

30

- ENABLE PROPAGATION DELAY (ns)

E

t

0

-60 -40 -20 0 20 40 60 80 100

t

RL = 1 kΩ

ELH,

t

ELH,

t

RL = 350 Ω, 1 kΩ

EHL,

RL = 350 Ω

TA - TEMPERATURE (˚C) TA - TEMPERATURE (˚C)

Fig. 11 Typical Pulse Width Distortion vs. Temperature

40

30

20

RL = 1 kΩ

Fig. 10 Typical Rise and Fall Time vs. Temperature

180

Vcc = 5.0 V

160

140

120

100

- RISE, FALL TIME (ns)

f

t

r,

t

= 7.5 mA

I

F

RL = 1 kΩ

80

60

40

20

0

-60 -40 -20 0 20 40 60 80 100

Vcc = 5.0 V

= 7.5 mA

I

F

RL = 350 Ω, 1 kΩ

RL = 350 Ω

t

RISE

t

Fall

PWD - PULSE WIDTH DISTORTION (ns)

© 2003 Fairchild Semiconductor Corporation

10

0

-10

-60 -40 -20 0 20 40 60 80 100

RL = 350 Ω

T

- TEMPERATURE (˚C)

A

Page 7 of 12

4/10/03

Input

e

e

ato

t

it

o

r

t

t

t

t

t

Monitor
(I )

F

Pulse
Generator
tr = 5ns
Z = 50Ω

O

47Ω

HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

HCPL-0600 HCPL-0601

+5V

V

1

CC

2

3

4 5

GND

8

.1 f

7

bypass

6

R

C

L

L

Output
(V )

O

Input
(I )

F

Output
(V )

O

Output
(V )

O

t

PHL

t

f

90%

10%

I = 7.5 mA

F

I = 3.75 mA

F

t

PLH

1.5 V

t

r

Puls
Gen
tr = 5ns
Z = 50Ω

O

7.5 mA

veforms for

Inpu
Mon
(V )

E

+5V

V

1

2

3

4

CC

GND

8

7

.1µf
bypass

6

R

L

Output
(V )

O

C

L

5

Input
(V )

E

Output
(V )

O

t

EHL

PHL,

t

nd

3.0 V

1.5 V

ELH

1.5 V

nd

© 2003 Fairchild Semiconductor Corporation

Page 8 of 12

4/10/03

HIGH SPEED-10 MBit/s

y

LOGIC GATE OPTOCOUPLERS

HCPL-0600 HCPL-0601

V

CC

1

I

A

B

V

FF

F

2

3

8

7

6

µf

.1
bypass

350Ω

+5V

Output
(V )

O

V

CM

0V

5V

V

O

V

O

0.5 V

4

Pulse Gen

Switching Pos. (A), I = 0

V (Min)

O

Switching Pos. (B), I = 7.5 mA

Peak

GND

V

CM

F

V (Max)

O

5

CM

H

F

CM

L

© 2003 Fairchild Semiconductor Corporation

Page 9 of 12

ransient Immunit

4/10/03

HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

HCPL-0600 HCPL-0601

ORDERING INFORMATION

Order

Option

R1 .R1 Tape and Reel (500 per Reel)

R2 .R2 Tape and Reel (2500 per Reel)

MARKING INFORMATION

Entry

Identifier

Description

1

0600

43

Definitions

1Fairchild logo

2Device number

VDE mark (Note: Only appears on parts ordered with VDE

3

option – See order entry table)

4 One digit year code, e.g., ‘3’

5Two digit work week ranging from ‘01’ to ‘53’

6 Assembly package code

5

2

SYYXV

6

© 2003 Fairchild Semiconductor Corporation

Page 10 of 12

4/10/03

HCPL-0600 HCPL-0601

Carrier Tape Specifications

3.5 ± 0.2

0.3 MAX

8.3 ± 0.1

4.0 ± 0.1

HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

8.0 ±

0.1

2 ± 0.05

Ø1.5 MI

1.75 ± 0.10

5.5 ± 0.05

5.2 ± 0.2

N

12.0 ± 0.3

Reflow Profile

300

250

200

150

100

Temperature (°C)

50

0

0

6.4 ±

X

0.1 MA

ection of Feed

User Dir

230°C, 10–30 s

245°C peak

Time above 183°C, 120–180 sec

Ramp up = 2–10°C/sec

0.5 1 1.5 2 2.5 3 3.5 4 4.5

Time (Minute)

0.2

Ø1.5 + 0.1/-

• Peak reflow temperature: 245°C (package surface temperature)

• Time of temperature higher than 183°C for 120–180 seconds

• One time soldering reflow is recommended

0

© 2003 Fairchild Semiconductor Corporation

Page 11 of 12

4/10/03

HIGH SPEED-10 MBit/s

LOGIC GATE OPTOCOUPLERS

HCPL-0600 HCPL-0601

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.

2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

© 2003 Fairchild Semiconductor Corporation

Page 12 of 12

4/10/03