Page 1
FEATURES
• Propagation Delay of 2.4 ns (typ)
• Propagation Delay Skew <300 ps
• Low Offset ±3 mV
• Latch Control
GENERAL DESCRIPTION
The HCMP96850 is a single, very high speed monolithic
comparator. It is pin-compatible with and has improved
performance over the AD9685 and the AM6685. The
HCMP96850 is designed for use in Automatic Test Equipment (ATE), high speed instrumentation, and other high
speed comparator applications.
APPLICATIONS
• High Speed Instrumentation, ATE
• High Speed Timing
• Window Comparators
• Line Receivers
• A/D Conversion
• Threshold Detection
HCMP96850
SINGLE UL TRAFAST VOL T AGE COMPARA TOR
BLOCK DIAGRAM
-
+
NONINVERTING
INPUT
INVERTING
INPUT
GND
1
V
EE
GND
2
V
CC
LATCH ENABLE
Q OUTPUT
Q OUTPUT
Improvements over other sources include reduced power
consumption, reduced propagation delays, and higher input
impedance.
The HCMP96850 is available in a 16-lead ceramic DIP
package over the industrial temperature range. It is also
available in die form.
Signal Processing Technologies, Inc.
4755 Forge Road, Colorado Springs, Colorado 80907, USA
Phone: (719) 528-2300 FAX: (719) 528-2370 Website: http://www.spt.com E-Mail: sales@spt.com
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SPT
2 3/18/97
HCMP96850
ELECTRICAL SPECIFICATIONS
T A = +25 °C, VCC = +5.0 V, VEE = -5.2 V, RL = 50 Ohms, unless otherwise specified.
TEST TEST
PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
DC ELECTRICAL CHARACTERISTICS
Input Offset Voltage RS = 0 Ohms
1
IV -3 +3 mV
Input Offset Voltage (Vos)R
S
= 0 Ohms,
1
T
MIN
<TA<T
MAX
IV -3.5 +3.5 mV
(Vos) Tempco V 4 µV/°C
Input Bias Current I 4 ±20 µA
Input Bias Current T
MIN
<TA<T
MAX
IV 7 µA
Input Offset Current I -1.0 +1.0 µA
Input Offset Current T
MIN
<TA<T
MAX
IV -1.5 +1.5 µA
Positive Supply Current I 3.3 5 mA
Negative Supply Current I 13.5 18 mA
Positive Supply Voltage, V
CC
IV +4.75 +5.0 +5.25 V
Negative Supply Voltage, V
EE
IV -4.95 -5.2 -5.45 V
Input Common Mode Range I -2.5 +2.5 V
Latch Enable
Common Mode Range IV -2 0 V
Open Loop Gain V 4000 V/V
Input Resistance V 60 kΩ
Input Capacitance V 3 pF
Input Capacitance (LCC Package) V 1 pF
Power Supply Sensitivity VCC and V
EE
V70dB
Common Mode Rejection Ratio V 80 dB
Power Dissipation I
OUTPUT
= 0 mA IV 90 120 mW
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Positive Supply Voltage (VCC to GND) .... -0.5 to +6.0 V
Negative Supply Voltage (VEE to GND) ... -6.0 to +0.5 V
Ground Voltage Differential ...................... -0.5 to +0.5 V
Input Voltages
Input Voltage ............................................ -4.0 to +4.0 V
Differential Input Voltage .......................... -5.0 to +5.0 V
Input Voltage, Latch Controls ..................... VEE to 0.5 V
Output
Output Current......................................................30 mA
Temperature
Operating Temperature, ambient .............-25 to +85 °C
junction ...................... +150 °C
Lead Temperature, (soldering 60 seconds) ...... +300 °C
Storage Temperature ..............................-65 to +150 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
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SPT
3 3/18/97
HCMP96850
ELECTRICAL SPECIFICATIONS
T A = +25 °C, VCC = +5.0 V, VEE = -5.2 V, RL = 50 Ohms, unless otherwise specified.
TEST TEST
PARAMETERS CONDITIONS LEVEL MIN TYP MAX UNITS
OUTPUT LOGIC LEVELS (ECL 10 KH Compatible)
Output High 50 Ohms to -2 V I -.98 -.81 V
Output Low 50 Ohms to -2 V I -1.95 -1.63 V
AC ELECTRICAL CHARACTERISTICS
2
Propagation Delay 10 mV O.D. III 2.4 3.0 ns
Latch Set-up Time IV 0.6 1 ns
Latch to Output Delay 50 mV O.D. IV 3 ns
Latch Pulse Width V 2 ns
Latch Hold Time IV 0.5 ns
Rise Time 20% to 80% V 1.76 ns
Fall Time 20% to 80% V 1.76 ns
1
RS = source impedance.
2
100 mV input step.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA=25 °C, and sample
tested at the specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design
and characterization data.
Parameter is a typical value for information purposes
only.
100% production tested at TA = 25 °C. Parameter is
guaranteed over specified temperature range.
TEST LEVEL
I
II
III
IV
V
VI
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SPT
4 3/18/97
HCMP96850
Figure 1 - Timing Diagram
t
pLOL
LATCH ENABLE TO OUTPUT LOW DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to the 50%
point of an output HIGH to LOW transition.
t
H
MINIMUM HOLD TIME - The minimum time after the
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
t
pL
MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
t
S
MINIMUM SET-UP TIME - The minimum time before
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.
t
pdH
INPUT TO OUTPUT HIGH DELAY - The propagation
delay measured from the time the input signal crosses
the input reference voltage (± the input offset voltage)
to the 50% point of an output LOW to HIGH transition.
t
pdL
INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the input signal crosses
the input reference voltage (± the input offset voltage)
to the 50% point of an output HIGH to LOW transition.
t
pLOH
LATCH ENABLE TO OUTPUT HIGH DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to 50%
point of an output LOW to HIGH transition.
V
OD
VOLTAGE OVERDRIVE - The difference between the
differential input and reference input voltages.
SWITCHING TERMS (Refer to figure 1)
TIMING INFORMATION
The timing diagram for the comparator is shown in figure 1.
The latch enable (LE) pulse is shown at the top. If LE is high
in the HCMP96850, the comparator tracks the input difference voltage. When LE is driven low, the comparator outputs are latched into their existing logic states.
The leading edge of the input signal (which consists of a
10 mV overdrive voltage) changes the comparator output
50%
V
REF
±V
OS
50%
50%
t
pLOL
t
pLOH
t
pL
t
S
t
pdL
t
pdH
VIN+=100 mV (P-P), V
OD
=10 mV
LATCH ENABLE
DIFFERENTIAL
INPUT VOLTAGE
OUTPUT Q
OUTPUT Q
t
H
V
OD
The set-up and hold times are a measure of the time required for an input signal to propagate through the first
stage of the comparator to reach the latching circuitry. Input signal changes occurring before tS will be detected
and held; those occurring after tH will not be detected. Changes between tS and tH may or may not be detected.
after a time of t
pdL
or t
pdH
(Q or Q). The input signal must be
maintained for a time ts (set-up time) before the latch enable
falling edge and held for time tH after the falling edge for the
comparator to accept data. After tH, the output ignores the
input status until the latch is strobed again. A minimum latch
pulse width of tpL is needed for strobe operation, and the
output transitions occur after a time of t
pLOH
or t
pLOL
.
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SPT
5 3/18/97
HCMP96850
TYPICAL INTERFACE CIRCUIT
A typical interface circuit using the comparator is shown in
figure 3. Although it needs few external components and is
easy to apply, there are several considerations that should
be noted to achieve optimal performance. The very high
operating speeds of the comparator require careful layout,
decoupling of supplies, and proper design of transmission
lines.
Since the HCMP96850 comparator is a very high frequency
and high gain device, certain layout rules must be followed
to avoid spurious oscillations. The comparator should be
soldered to the board with component lead lengths kept as
short as possible. A ground plane should be used, while the
input impedance to the part is kept as low as possible, to
decrease parasitic feedback. If the output board traces are
longer than approximately one-half inch, microstripline techniques must be employed to prevent ringing on the output
waveform. Also, the microstriplines must be terminated at
the far end with the characteristic impedance of the line to
prevent reflections. All voltage supply pins should be decoupled with high-frequency capacitors as close to the
device as possible. All ground pins and no connects should
be connected to a common ground plane to further improve
noise immunity.
On the HCMP96850, all outputs, whether used or unused,
should have identical terminations to minimize ground current switching.
Noninverting
Input
Inverting
Input
.1 µF
.1 µF
-2 V
Pulldown
+
-
LE
= Represents line termination.
V
CC
V
EE
50 Ω
50 Ω
GND
2
GND
1
V
REF
V
IN
Q Outpu
t
Q Outpu
t
R
L
Figure 2 - Internal Function Diagram
REF1
REF
2
VEEV
CC
CLK
BUF
LE
LATCH
ECL
OUT
PRE
AMP
+
-
V
IN
V
IN
Q
GND
1
GND
2
GENERAL INFORMATION
The HCMP96850 is an ultrahigh speed single voltage comparator. It offers tight absolute characteristics which guarantee matching from package to package. The device has
differential analog inputs and complementary logic outputs
compatible with ECL systems. The output stage is adequate
for driving terminated 50 Ohm transmission lines.
The HCMP96850 has one latch enable control and should be
driven by standard ECL logic levels. It also has two separate
ground pins, one for the output to accommodate large
ground currents without affecting the rest of the circuit, while
the other is for the small signal intermediate stages. The
input stage is referenced to VCC and VEE.
Figure 3 - Typical Interface Circuit
Page 6
SPT
6 3/18/97
HCMP96850
Q
22
Q
21
4.5 mA
V
1
Q Output
Q Output
Q
23
Q
24
R
8
240 Ω
R
7
240 Ω
V
2
Figure 4 - Equivalent Input Circuit Figure 5 - Output Circuit
NOTES: 1. ALL BNC & SEMIRIGID COAX SHIELD ARE
GROUNDED.
2. ALL RESISTORS 1% (10 Ω = 49.9 Ω).
3. KEEP ALL LEADS AS SHORT AS POSSIBLE
WITH ELECTRICAL LENGTHS L1 = L2 + L3.
4. D.U.T. PLUGS INTO A 16 PIN HIGH
FREQUENCY PIN SOCKET.
5. MONITOR INPUT IMPEDANCE 50 Ω TO GND.
6. SEMIRIGID COAX SHIELD SHOULD BE
CONNECTED AS CLOSE TO THE DEVICE AS
POSSIBLE.
Figure 6 - Test Load
50 Ω Coax
50 Ω
R
z
V
pd
(-4.0 V)
100 Ω
R
L
100 Ω
R
Z
Figure 7 - AC Test Fixture
SEMI
RIGID
SEMI
RIGID
SEMI
RIGID
SEMI
RIGID
DUT
0.1 µF
0.1 µF
15 µF
50 Ω
16.7 Ω
100 Ω
50 Ω
6
6
SEMI
RIGID
15 µF
L1
L2
L2
L1
L3
4
V+
V-
+
-
LE
V
IN
-
V
IN
+
V
IN
+
MONITOR
V
CC
(+5.0V)
16.7 Ω
16.7 Ω
50 Ω
16.7 Ω
16.7 Ω
16.7 Ω
66
Q
Q
6
Q
3
R
2
R
1
V
CC
V
IN
R
IN
V
IN
V
R2
V
R1
V
EE
R
3
R
4
R
5
Q
2
Q
6
Q
8
Q
5
Q
7
Q
1
Q
4
IN
1PF
C
IN
1PF
C
100Ω
100Ω
R
IN
Page 7
SPT
7 3/18/97
HCMP96850
Figure 8 - HCMP96850 with Hysteresis
100 Ω
-5.2 V
V
LE
0.1 µF
300 Ω
V
O
V
IN
Noninverting
Input
Inverting
Input
.1 µF
.1 µF
-2 V
Pulldown
+
-
LE
Hysteresis is obtained by applying a DC bias to the LE pin.
VLE = -1.3 V ±100 mV
= Represents line termination.
V
CC
V
EE
50 Ω
50 Ω
GND
2
GND
1
V
REF
V
IN
Q Output
Q Output
R
L
PACKAGE OUTLINE
16-Lead Cerdip
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A 0.005 0.13
B 0.200 5.08
C 0.125 0.150 3.18 3.81
D 0.015 0.023 0.38 0.58
E 0.090 0.110 2.29 2.79
F 0.030 0.065 0.76 1.65
G0° 15° 0° 15°
H 0.008 0.015 0.20 0.38
I 0.290 0.320 7.37 8.13
J 0.250 0.310 6.35 7.87
K 0.140 0.200 3.56 5.08
L 0.015 0.050 0.38 1.27
M 0.745 0.785 18.92 19.94
N 0.015 0.050 0.38 1.27
E F
K
L
B
C
D
1
16
A
M
N
G
H
I
J
Page 8
SPT
8 3/18/97
HCMP96850
PIN ASSIGNMENTS
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE PACKAGE TYPE
HCMP96850SID -25 to +85 °C 16-Lead Cerdip
HCMP96850SCU +25 °C Die*
*Please see the die specification for guaranteed electrical performance.
1
2
3
16
15
14
4
5
6
7
89
10
11
12
13
GND
1
16 LEAD DIP
V
+IN
-IN
N/C
LE
N/C
V
CC
EE
N/C
N/C
Q
Q
N/C
N/C
N/C
GND
2
OUT
OUT
PIN FUNCTIONS
Name Function
GND
1
Circuit Ground
V
CC
Positive Supply Voltage
+IN Noninverting Input
-IN Inverting Input
N/C No Connection
LE Latch Enable
V
EE
Negative Supply Voltage
Q
OUT
Output
Q
OUT
Inverted Output
GND
2
Output Ground
Signal Processing Technologies, Inc. reserves the right to change products and specifications without notice. Permission is hereby
expressly granted to copy this literature for informational purposes only. Copying this material for any other use is strictly prohibited.
WARNING - LIFE SUPPORT APPLICATIONS POLICY - SPT products should not be used within Life Support Systems without the specific
written consent of SPT. A Life Support System is a product or system intended to support or sustain life which, if it fails, can be reasonably
expected to result in significant personal injury or death.
Signal Processing Technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device
failure. It is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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