Datasheet HCF4520BE Specification

Page 1
HCF4520B
DUAL BINARY UP COUNTER
■ MEDIUM SPEED OPERATION :
6MHz (Typ.) at 10V
■ POSITIVE -OR NEGATIVE- EDGE
TRIGGERING
■ SYNCHRONOUS INTERNAL CARRY
PROPAGATION
■ QUIESCENT CURRENT SPECIF. UP TO 20V
■ INPUT LEAKAGE CURRENT
I
= 100nA (MAX) AT VDD = 18V TA = 25°C
I
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTI ON OF B SERI ES CMOS DEVICES"
DESCRIPTION
HCF4520B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4520B, a Dual Binary Up Counter, consists of two identical, internal 4-stage counters. The counter stages are D-type Flip-Flops having interchangeable Clock and Enable lines for
DIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4520BEY
SOP HCF4520BM1 HCF4520M013TR
incrementing on either the positive-going or negative going transitions. For single-unit operations the Enable input is maintained High and the counter advances on each pos itive going transition of the Clock. The counters are cleared by high levels on their Reset lines. The counter can be cascaded in the ripple mode by connecting Q4 to the enable in put of the sub sequent counter while the clock input of the latter is held low.
PIN CONNECTION
1/12October 2002
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HCF4520B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1 CLOCK A Clock A input 2 ENABLE A Enable A Input 7 RESET A Reset A Input
3, 4, 5, 6 Q1A to Q4A Data Outputs
9 CLOCK B Clock B input 10 ENABLE B Enable B Input 15 RESET B Reset B Input
11,12,13,14 Q1B to Q4B Data Outputs
8 16
FUNCTIONAL DIAGRAM
V
SS
V
DD
Negative Supply Voltage Positive Supply Voltage
TRUTH TABLE
CLOCK ENABLE RESET ACTION
L L INCREMENT COUN TER
X L NO CHANGE
H L NO CHANGE X X H Q1 THRU Q4 = 0
X : Don’t Care
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H L INCREMENT COUN TER
X L NO CHANGE
L L NO CHANGE
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LOGIC DIAGRAM
HCF4520B
TIMING CHART
3/12
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HCF4520B
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to V
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
T
Supply Voltage
DD
DC Input Voltage -0.5 to VDD + 0.5
I
I
DC Input Current
I
Power Dissipation per Package 200 mW
D
-0.5 to +22 V
10 mA
±
Power Dissipation per Output Transistor 100 mW Operating Temperature
op
Storage Temperature
stg
pin voltage.
SS
Supply Voltage
DD
Input Voltage 0 to V
I
Operating Temperature
op
-55 to +125 °C
-65 to +150 °C
3 to 20 V
DD
-55 to 125 °C
V
V
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Page 5
DC SPECIFICATIONS
Test Condition Value
T
Symbol Parameter
I
Quiescent Current 0/5 5 0.04 5 150 150
L
V
(V)
V
I
(V)
|I
|
O
O
(µA)
V
DD
(V)
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
0/10 10 0.04 10 300 300 0/15 15 0.04 20 600 600 0/20 20 0.08 100 3000 3000
V
High Level Output
OH
Voltage
0/5 <1 5 4.95 4.95 4.95
0/15 <1 15 14.95 14.95 14.95
Low Level Output
V
OL
Voltage
5/0 <1 5 0.05 0.05 0.05
15/0 <1 15 0.05 0.05 0.05
High Level Input
V
IH
Voltage
0.5/4.5 <1 5 3.5 3.5 3.5
1.5/13.5 <1 15 11 11 11
V
IL
Low Level Input Voltage
4.5/0.5 <1 5 1.5 1.5 1.5
13.5/1.5 <1 15 4 4 4
I
OH
Output Drive Current
0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1
0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36 0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9 0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4
I
OL
Output Sink Current
0/5 0.4 <1 5 0.44 1 0.36 0.36
0/15 1.5 <1 15 3.0 6.8 2.4 2.4
Input Leakage
I
I
Current
C
Input Capacitance
I
The Noi se Margin fo r both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
0/18 Any Input 18
Any Input 5 7.5 pF
-5
10
±
-40 to 85°C -55 to 125°C
0.1
±
1
±
HCF4520B
Unit
A
µ
V0/10 <1 10 9.95 9.95 9.95
V10/0 <1 10 0.05 0.05 0.05
V1/9 <1 10 7 7 7
V9/1 <1 10 3 3 3
mA
mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9
1
±
A
µ
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HCF4520B
DYNAMIC ELECTRICAL CHARACTERISTICS (T
Symbol Parameter
t
PLH tPHL
t
PLH tPHL
t
TLH tTHL
t
f
MAX
t
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
Propagation Delay Time Clock or Enable to Output
Propagation Delay Time Reset to Output
Transition Time 5 100 200
Clock Pulse Width 5 200 100
t
W
Reset Pulse Width 5 250 125
t
W
Enable Pulse Width 5 400 200
t
W
Clock or Enable Rise and
, t
r
f
Fall Time
Maximum Clock Frequency
, t
Clock or Enable Rise and
r
f
Fall Time
(V)
V
DD
5 280 560
15 80 160
5 330 650
15 90 170
15 40 80
15 70 35
15 80 40
15 140 70
515
15 5
5 1.5 3
15 4 8
515
15 5
= 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
amb
Test Condition Value (*) Unit
Min. Typ. Max.
ns10 115 230
ns10 130 225
ns10 50 100
ns10 100 50
ns10 110 55
ns10 200 100
µ
MHz10 3 6
µ
s10 15
s10 5
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HCF4520B
TEST CIRCUIT
CL = 50pF or equivalent (in cludes jig and probe capac i t ance) R
= 200K
Ω
L
R
= Z
of pulse generator (typically 50Ω)
T
OUT
WAVEFORM 1 : MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1M H z; 50% duty c y cle)
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HCF4520B
WAVEFORM 2 : PROPAGATION DELAY TIME, MINIMUM PULSE WIDTH (f=1MHz; 50% duty cycle)
TYPICAL APPLICATION
RIPPLE CASCADIN G OF FOUR COUNT ERS WI TH POS I T IVE-EDGE TRIGGERI N G
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HCF4520B
TYPICAL APPLICATION
SYNCHRONOUS CASCADING OF 4 BINARY COUNTERS WITH NEGATIVE-EDGE TRIGGERING
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HCF4520B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065 b 0.5 0.020
b1 0.25 0.010
D 20 0.787 E 8.5 0.335 e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050
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P001C
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SO-16 MECHANICAL DATA
HCF4520B
DIM.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007 a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45˚ (typ.)
D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050
M 0.62 0.024
S ˚ (max.)
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
8
PO13H
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HCF4520B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility f or the consequences of use of such informatio n nor for any infringement of paten ts or o ther rig hts of t hird part ies which ma y result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previousl y suppl ied. STM icroel ectronics produc ts are not auth orized for use as c ritica l compone nts in l ife s upport dev ices or systems without express written approval of STMicroelectronics.
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