JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTI ON OF B SERI ES CMOS
DEVICES"
DESCRIPTION
HCF4520B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4520B, a Dual Binary Up Counter, consists of
two identical, internal 4-stage counters. The
counter stages are D-type Flip-Flops having
interchangeable Clock and Enable lines for
DIPSOP
ORDER CODES
PACKAGETUBET & R
DIPHCF4520BEY
SOPHCF4520BM1HCF4520M013TR
incrementing on either the positive-going or
negative going transitions. For single-unit
operations the Enable input is maintained High
and the counter advances on each pos itive going
transition of the Clock. The counters are cleared
by high levels on their Reset lines. The counter
can be cascaded in the ripple mode by connecting
Q4 to the enable in put of the sub sequent counter
while the clock input of the latter is held low.
PIN CONNECTION
1/12October 2002
Page 2
HCF4520B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
1CLOCK AClock A input
2ENABLE AEnable A Input
7RESET AReset A Input
3, 4, 5, 6 Q1A to Q4A Data Outputs
9CLOCK BClock B input
10ENABLE B Enable B Input
15RESET BReset B Input
11,12,13,14Q1B to Q4B Data Outputs
8
16
FUNCTIONAL DIAGRAM
V
SS
V
DD
Negative Supply Voltage
Positive Supply Voltage
TRUTH TABLE
CLOCKENABLERESETACTION
LLINCREMENT COUN TER
XLNO CHANGE
HLNO CHANGE
XXHQ1 THRU Q4 = 0
X : Don’t Care
2/12
HLINCREMENT COUN TER
XLNO CHANGE
LLNO CHANGE
Page 3
LOGIC DIAGRAM
HCF4520B
TIMING CHART
3/12
Page 4
HCF4520B
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
T
Supply Voltage
DD
DC Input Voltage-0.5 to VDD + 0.5
I
I
DC Input Current
I
Power Dissipation per Package200mW
D
-0.5 to +22V
10mA
±
Power Dissipation per Output Transistor100mW
Operating Temperature
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility f or the
consequences of use of such informatio n nor for any infringement of paten ts or o ther rig hts of t hird part ies which ma y result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previousl y suppl ied. STM icroel ectronics produc ts are not auth orized for use as c ritica l compone nts in l ife s upport dev ices or
systems without express written approval of STMicroelectronics.
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