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HCF4510B
PRESETTABLE BCD UP/DOWN COUNTER
■ MEDIUM SPEED OPERATION :
8 MHz (Typ.) at 10V
■ SYNCHRONOUS INTERNAL CARRY
PROPAGATION
■ RESET AND PRESET CAPABILITY
■ STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
■ QUIESCENT CURRENT SPECIF. UP TO 20V
■ 5V , 10V AND 15V PARAMETRIC RATINGS
■
INPUT LEAKAGE CURRENT
= 100nA (MAX) AT VDD = 18V TA = 25°C
I
I
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTI ON OF B SERI ES CMOS
DEVICES"
DESCRIPTION
HCF4510B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP package.
It is a PRESETTABLE BCD UP/DOWN
COUNTER consists of four synchronously
clocked D-type flip-flops (with a gating structure to
provide T-type flip-flop capab ility) connec ted a s a
counter. This counter can be cleared by a high
level on the RESET line, and ca n b e p r e se t to a n y
binary number present on the jam inputs by a high
level on the PRESET ENABLE line. This device
will count out of non-BCD counter states in a
maximum of t wo clock pul ses in the up mode and
DIP
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4510BEY
a maximum of four clock pulses in the down mode.
If the CARRY IN
input is held low, the counter
advances up or down on each positive going clock
transition. Synchronous cascading is
accomplished by connecting all clock inputs in
parallel and connecting the CARRY OUT
significant stage to the CARRY IN
of a less
of a more
significant stage. HCF4510B can be c ascaded in
the ripple mode by connecting all clock inputs in
parallel and connecting the CARRY OUT
to the
clock of the next stage. If the UP/DOWN input
changes during a terminal count, the CARRY OUT
must be gated with the clo ck, and the UP/DOW N
input must change while the clock is high. This
method provides a clean clock signal to the
subsequent counting stage.
PIN CONNECTION
1/11September 2002
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HCF4510B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1
4, 12, 13, 3 P1 to P4 Inputs
6, 11, 14, 2 Q1 to Q4 Outputs
15 CLOCK Clock Input
10 UP/DOWN Up/Down Control Input
5 CARRY-IN
7 CARRY-OUT
9 RESET Reset Input
8
16
FUNCTIONAL DIAGRAM
PRESET
ENABLE
V
SS
V
DD
Preset Enable Input
Carry Input
Carry Output
Negative Supply Voltage
Positive Supply Voltage
TRUTH TABLE
CL
X H X L L NO COUNT
X X X H L PRESET
XXXXH RESET
X : Don’t Care
2/11
CARRY-IN
(Cl)
L H L L COUNT UP
L L L L COUNT DOWN
UP/DOWN
PRESET
ENABLE
RESET ACTION
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LOGIC DIAGRAM
HCF4510B
TIMING CHART
3/11
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HCF4510B
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values ar e referred to V
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
T
Supply Voltage
DD
DC Input Voltage -0.5 to VDD + 0.5
I
I
DC Input Current
I
Power Dissipation per Package 200 mW
D
-0.5 to +22 V
10 mA
±
Power Dissipation per Output Transistor 100 mW
Operating Temperature
op
Storage Temperature
stg
pin voltage.
SS
Supply Voltage
DD
Input Voltage 0 to V
I
Operating Temperature
op
-55 to +125 °C
-65 to +150 °C
3 to 20 V
DD
-55 to 125 °C
V
V
4/11
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DC SPECIFICATIONS
Test Condition Value
T
Symbol Parameter
I
Quiescent Current 0/5 5 0.04 5 150 150
L
V
(V)
V
I
(V)
|I
|
O
O
(µA)
V
DD
(V)
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
0/10 10 0.04 10 300 300
0/15 15 0.04 20 600 600
0/20 20 0.08 100 3000 3000
V
High Level Output
OH
Voltage
0/5 <1 5 4.95 4.95 4.95
0/15 <1 15 14.95 14.95 14.95
Low Level Output
V
OL
Voltage
5/0 <1 5 0.05 0.05 0.05
15/0 <1 15 0.05 0.05 0.05
High Level Input
V
IH
Voltage
0.5/4.5 <1 5 3.5 3.5 3.5
1.5/13.5 <1 15 11 11 11
V
IL
Low Level Input
Voltage
4.5/0.5 <1 5 1.5 1.5 1.5
13.5/1.5 <1 15 4 4 4
I
OH
Output Drive
Current
0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1
0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36
0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9
0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4
I
OL
Output Sink
Current
0/5 0.4 <1 5 0.44 1 0.36 0.36
0/15 1.5 <1 15 3.0 6.8 2.4 2.4
Input Leakage
I
I
Current
C
Input Capacitance
I
The Noi se Margin for bot h " 1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
0/18 Any Input 18
Any Input 5 7.5 pF
-5
10
±
-40 to 85°C -55 to 125°C
0.1
±
1
±
HCF4510B
Unit
A
µ
V0/10 <1 10 9.95 9.95 9.95
V10/0 <1 10 0.05 0.05 0.05
V1/9 <1 10 7 7 7
V9/1 <1 10 3 3 3
mA
mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9
1
±
A
µ
5/11
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HCF4510B
DYNAMIC ELECTRICAL CHARACTERISTICS (T
= 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
amb
Test Condition Value (*) Unit
Symbol Parameter
t
PHL tPLH
Propagation Delay Time
Clock to Q Output
(V)
V
DD
Min. Typ. Max.
5 200 400
ns10 100 200
15 75 150
t
PHL tPLH
t
PHL tPLH
Propagation Delay Time
Preset or Reset to Q
Output
Propagation Delay Time
Clock to Carry Out
5 210 420
ns10 105 210
15 80 160
5 240 480
ns10 120 240
15 90 180
t
PHL tPLH
Propagation Delay Time
Carry in to Carry Out
5 125 250
ns10 60 120
15 50 100
t
PHL tPLH
t
THL tTLH
Propagation Delay Time
Preset or Reset to Carry
Out
Transition Time 5 100 200
5 320 640
ns10 160 320
15 125 250
ns10 50 100
15 40 80
f
MAX
Maximum Clock
Frequency
524
MHz10 4 8
15 5.5 11
Clock Pulse Width 5 150
t
W
ns10 75
15 60
(1)
t
REM
Preset Enable or Reset
Removal Time
5150
ns10 80
15 60
(2)
, t
t
r
Clock Rise or Fall Time 5 15
f
s10 5
µ
15 5
t
setup
Carry in Setup Time 5 130
ns10 60
15 45
t
setup
Up/Down Setup Time 5 360
ns10 160
15 110
Preset Enable or Reset
t
W
Pulse Width
5220
ns10 100
15 75
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) Time required after the falling edge of the reset or preset enable inputs before the rising edge of the clock will trigger the counter (similar
to setup time)
(2) If more than unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of the fixed pr opa gati on
delay at 15pF and the transition time of the carry output driving stage for the estimated capacitive load.
6/11
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TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
R
= 200K
Ω
L
R
= Z
of pulse generator (typically 50Ω)
T
OUT
WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycl e )
HCF4510B
7/11
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HCF4510B
WAVEFORM 2 : MINIMUM SETUP TIME (CI TO CLOCK) (f=1MHz; 50% duty cycl e )
WAVEFORM 3 : PROPAGATION DELAY TIMES, MINIMUM RESET PULSE WIDTH (f=1MHz; 50%
duty cycle)
8/11
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HCF4510B
TIPICAL APPLICATIONS TYPICAL 16-CHANNEL, 10 BIT DATA ACQUISITION SYSTEM
TIPICAL APPLICATIONS CASCADING COUNTER PACKAGES
9/11
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HCF4510B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
10/11
P001C
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HCF4510B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility f or the
consequences of use of such informatio n nor for any infringement of paten ts or o ther rig hts of t hird part ies which ma y result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previousl y suppl ied. STM icroel ectronics produc ts are not auth orized for use as c ritica l compone nts in l ife s upport dev ices or
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11/11
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