HCF4095B
GATED J-K MASTER SLAVE FLIP-FLOP
■ 16MHz TOGGLE RATE (Typ.) at
V
- VSS = 10V
DD
■ GATED INPUTS
■ QUIESCENT CURRENT SPECIFIED UP TO
20V
■ 5V, 10V AND 15V PARAMETRIC RAT INGS
■ INPUT LEAKAGE CURRENT
I
= 100nA (MAX) AT VDD = 18V TA = 25°C
I
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTI ON OF B SERI ES CMOS
DEVICES"
DESCRIPTION
HCF4095B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4095B is J-K Master-Slave Flip-Flops
featuring separate AND gating of multiple J and K
inputs. The gated J-K input control transfers
DIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4095BEY
SOP HCF4095BM1 HCF4095M013TR
information into the master section during clocked
operation. Information on the J-K inputs is
transferred to the Q and Q
outputs on the positive
edge of the c lock pulse. SET and R ESET inputs
(active high) are provided for asynchronous
operation.
PIN CONNECTION
1/11September 2002
HCF4095B
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
3, 4, 5 J1 to J3 J Inputs
11, 10, 9 K1 to K3 K Inputs
8 Q Q Output
6Q
13 SET (S) Set Inputs(Active High)
2 RESET (R) Reset Inputs(Active High)
12 CLOCK Clock Inputs
1 NC Not Connected
7
14
V
SS
V
DD
TRUTH TABLE : SYNCHRONOUS OPERATION (S=0 R=0)
INPUTS BEFORE POSITIVE CLOCK TRANSITION OUTPUTS AFTER POSITIVE CLOCK TRANSITION
J* K* Q Q
L L NO CHANGE
LHLH
HLHL
H H TOGGLES
(*) : J=J1 • J2 • J3, K=K1 • K2 • K3
Q Output
Negative Supply Voltage
Positive Supply Voltage
TRUTH TABLE : ASYNCHRONOUS OPERATION (J and K DON’T CARE)
INPUTS BEFORE POSITIVE CLOCK TRANSITION OUTPUTS AFTER POSITIVE CLOCK TRANSITION
SRQQ
L L NO CHANGE
LHLH
HLHL
HHLL
(*) : L = Vss, H = Vdd
2/11
FUNCTIONAL DIAGRAM
LOGIC DIAGRAM
HCF4095B
3/11
HCF4095B
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are re ferred to V
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
T
Supply Voltage
DD
DC Input Voltage -0.5 to VDD + 0.5
I
I
DC Input Current
I
Power Dissipation per Package 200 mW
D
-0.5 to +22 V
10 mA
±
Power Dissipation per Output Transistor 100 mW
Operating Temperature
op
Storage Temperature
stg
pin voltage.
SS
Supply Voltage
DD
Input Voltage 0 to V
I
Operating Temperature
op
-55 to +125 °C
-65 to +150 °C
3 to 20 V
DD
-55 to 125 °C
V
V
DC SPECIFICATIONS
Symbol Parameter
I
Quiescent Current 0/5 5 0.02 1 30 30
L
V
High Level Output
OH
Voltage
Low Level Output
V
OL
Voltage
High Level Input
V
IH
Voltage
Low Level Input
V
IL
Voltage
Output Drive
I
OH
Current
Output Sink
I
OL
Current
Test Condition Value
V
(V)
= 25°C
V
I
(V)
|I
|
O
O
(µA)
V
DD
(V)
A
Min. Typ. Max. Min. Max. Min. Max.
-40 to 85°C -55 to 125°C
T
0/10 10 0.02 2 60 60
0/15 15 0.02 4 120 120
0/20 20 0.04 20 600 600
0/5 <1 5 4.95 4.95 4.95
0/15 <1 15 14.95 14.95 14.95
5/0 <1 5 0.05 0.05 0.05
15/0 <1 15 0.05 0.05 0.05
0.5/4.5 <1 5 3.5 3.5 3.5
1.5/13.5 <1 15 11 11 11
4.5/0.5 <1 5 1.5 1.5 1.5
13.5/1.5 <1 15 4 4 4
0/5 2.5 <1 5 -1.36 -3.2 -1.15 -1.1
0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36
0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9
0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4
0/5 0.4 <1 5 0.44 1 0.36 0.36
0/15 1.5 <1 15 3.0 6.8 2.4 2.4
Unit
A
µ
V0/10 <1 10 9.95 9.95 9.95
V10/0 <1 10 0.05 0.05 0.05
V1/9 <1 10 7 7 7
V9/1 <1 10 3 3 3
mA
mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9
4/11
Test Condition Value
= 25°C
Symbol Parameter
V
(V)
I
Input Leakage
I
Current
C
Input Capacitance
I
The Noi se Margin for both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
0/18 Any Input 18
V
I
(V)
|I
|
O
O
(µA)
V
DD
(V)
Any Input 5 7.5 pF
T
A
Min. Typ. Max. Min. Max. Min. Max.
-5
10
±
-40 to 85°C -55 to 125°C
0.1
±
1
±
HCF4095B
Unit
1
±
A
µ
DYNAMIC ELECTRICAL CHARACTERISTICS (T
Symbol Param eter
t
PLH tPHL
t
PLH tPHL
t
TLH tTHL
t
t
setup
(*) Typical temperatur e coefficient for a ll VDD value is 0.3 %/°C.
Propagation Delay Time 5 250 500
Propagation Delay Time
(Set or Reset)
Transition Time 5 100 200
Maximum Clock Input
f
CL
Frequency
Clock Pulse Width 5 140 70
t
W
Clock input Rise or Fall Time 5 15
r, tf
Set or Reset Pulse Width 5 200 100
t
W
Data Setup Time 5 400 200
(V)
V
DD
15 75 150
5 150 300
15 50 100
15 40 80
5 3.5 7
15 12 24
15 40 20
15 5
15 50 25
15 100 50
= 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
amb
Test Condition Value (*) Unit
Min. Typ. Max.
ns10 100 200
ns10 75 150
ns10 50 100
MHz10 8 16
ns10 60 30
s10 5
µ
ns10 100 50
ns10 160 80
5/11
HCF4095B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
R
= 200K
Ω
L
R
= Z
of pulse generator (typically 50Ω)
T
OUT
WAVEFORM : PROPAGATION DELAY, TRANSITION AND SETUP TIME
6/11
WAVEFORM : CLOCK PULSE, RISE AND FALL TIME
TYPICAL APPLICATION: T-TYPE FLIP-FLOP
HCF4095B
7/11
HCF4095B
TYPICAL APPLICATION: SYNCHRONOUS BINARY DIVIDE BY TEN COUNTER
TRUTH TABLE
STATEQAQBQCQD
0LLLL
1HLLL
2LHLL
3HHLL
4LLHL
5HLHL
6LHHL
7HHHL
8LLLH
9HLLH
NOTE: In all units the Set and Reset are Connect ed t o VSS.
8/11
HCF4095B
Plastic DIP-14 MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 1.39 1.65 0.055 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 15.24 0.600
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 2.54 0.050 0.100
P001A
9/11
HCF4095B
SO-14 MECHANICAL DATA
DIM.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45˚ (typ.)
D 8.55 8.75 0.336 0.344
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 7.62 0.300
F 3.8 4.0 0. 149 0. 157
G 4.6 5.3 0. 181 0.208
L 0.5 1.27 0.019 0.050
M 0.68 0.026
S ˚ (max.)
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
8
10/11
PO13G
HCF4095B
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its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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11/11
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