JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTI ON OF B SERI ES CMOS
DEVICES"
DESCRIPTION
HCF4089B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF4089B is a low power 4-bit digital rate
multiplier that provides an output pulse rate that is
the clock input pulse rate multiplied by 1/1 6 t imes
the binary input. For example, when the binary
input number is 13, ther will be 13 output pulses
for every 16 input pulses.
HCF4089B has an internal synchronous 4-bit
counter, which, together with one of the four
DIPSOP
ORDER CODES
PACKAGETUBET & R
DIPHCF4089BEY
SOPHCF4089BM1HCF4089M013TR
binary inputs bits, produces pulse trains as shown
in the timing diagram.
If more than one binary input bit is high, the
resulting pulse train is a combination of the above
separate pulse trains. This device may be used to
perform arithmetic operations (add, subtract,
divide, raise to a power), solve algebrical and
differential equations, generate natural logarithms
and trigonometric functions, A/D and D/A
conversions, and frequency division.
PIN CONNECTION
1/11September 2002
Page 2
HCF4089B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
14, 15, 2, 3A, B, C, DBinary Rate Select Inputs
5OUT
6OUTRate Output
4SET TO "15" Set Input
1"15" OUTO utput
The Noi se Margin for bot h " 1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
DYNAMIC ELECTRICAL CHARACTERISTICS (T
= 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
amb
Test ConditionValue (*)Unit
SymbolParameter
t
PHL tPLH
Propagation Delay Time
CLOCK to OUT
V
DD
(V)
Min.Typ. Max.
5110220
154590
t
PHL tPLH
t
PHL tPLH
t
PHL tPLH
Propagation Delay Time
CLOCK or STROBE to
OUT
Propagation Delay Time
CLOCK to INHIBIT High
Level to Low Level
Propagation Delay Time
LOW Level to HIGH Level
5150300
1560120
5360720
15110220
5250500
1575150
ns1055110
ns1075150
ns10160320
ns10100200
5/11
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HCF4089B
SymbolParameter
t
PHL tPLH
Propagation Delay Time
CLEAR to OUT
(V)
V
DD
5380760
15130260
t
PHL tPLH
Propagation Delay Time
CLOCK to "9" or "15" OUT
5300600
1590180
t
PHL tPLH
Propagation Delay Time
CASCADE to OUT
590180
153570
t
PHL tPLH
t
PHL tPLH
Propagation Delay Time
INHIBIT IN to INHIBIT
OUT
Propagation Delay Time
SET to OUT
5160320
1555110
5330660
15110220
t
THL tTLH
Transition Time 51002 00
154080
f
CL
Maximum Clock
Frequency
51.22.4
153.57
Clock Pulse Width5330165
t
W
1510050
t
Clock Rise or Fall Time515
r, tf
1515
SET or CLEAR pulse
t
W
Width
516080
156030
t
setup
t
INHIBIT Input Set-Up
Time, High Level to Low
Level
INHIBIT Input Removal
R
Time
510050
152010
5240120
151105 5
Minimum SET Removal
t
R
Time
515075
155025
CLEAR Removal Time56030
t
R
153015
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
Test ConditionValue (*)Unit
Min.Typ. Max.
ns10175350
ns10125250
ns104590
ns1075150
ns10150300
ns1050100
MHz102.55
ns1017085
µ
ns109045
ns104020
ns101306 5
ns108040
ns104020
s1015
6/11
Page 7
HCF4089B
APPLICATION NOTES
For words of more than 4 bits, HCF4089B device may be cascaded in two different modes : an ADD mode
and a MULTIPLY mode.
TWO HCF4089B’S CASCADED IN THE "ADD" MODE WITH A PRESET NUMBER OF 189
In the ADD mode some of the gap s left by the more significant unit at the count of 15 are filled in by the less significant units. For example,
when two units are cascaded in the ADD mode and programmed to 11 and 13, respectively, the mo re significant unit will have 11 output
pulses and the other unit will have 13 outp ut pulses for ev ery 256 input pu l ses for a total of :
11 13 189
+ =
16 256 256
TWO HCF4089B’S CASCADED IN THE "MULTIPLY" MODE FOR MULTIPLICATION OF TWO
VARIABLES A AND B WITH LOOP CIRCUIT CONTROL
A B 1 N
When the loop stabilities rate R2 = rate R3, thus fclock( •
16 16 16 16
= fclock ( •
)
)
therefore N = AB
7/11
Page 8
HCF4089B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitanc e)
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