Datasheet HCF4089BE Specification

Page 1
HCF4089B
BINARY RATE MULTIPLIER
■ CASCADABLE IN MULTIPLES OF 4-BIT S
■ SET TO "15" INPUT AND "15" DETECT
OUTPUT
■ QUIESCENT CURRENT SPECIFIED UP TO
20V
■ STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
■ INPUT LEAKAGE CURRENT
I
= 100nA (MAX) AT VDD = 18V TA = 25°C
I
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTI ON OF B SERI ES CMOS DEVICES"
DESCRIPTION
HCF4089B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4089B is a low power 4-bit digital rate multiplier that provides an output pulse rate that is the clock input pulse rate multiplied by 1/1 6 t imes the binary input. For example, when the binary input number is 13, ther will be 13 output pulses for every 16 input pulses. HCF4089B has an internal synchronous 4-bit counter, which, together with one of the four
DIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4089BEY
SOP HCF4089BM1 HCF4089M013TR
binary inputs bits, produces pulse trains as shown in the timing diagram. If more than one binary input bit is high, the resulting pulse train is a combination of the above separate pulse trains. This device may be used to perform arithmetic operations (add, subtract, divide, raise to a power), solve algebrical and differential equations, generate natural logarithms and trigonometric functions, A/D and D/A conversions, and frequency division.
PIN CONNECTION
1/11September 2002
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HCF4089B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
14, 15, 2, 3 A, B, C, D Binary Rate Select Inputs
5OUT 6 OUT Rate Output 4 SET TO "15" Set Input 1 "15" OUT O utput
7
13 CLEAR Clear Input 12 CASCADE Cascade
11 10 STROBE Strobe
9 CLOCK Clock Input 8
16
FUNCTIONAL DIAGRAM
INHIBIT OUT
(CARRY)
INHIBIT IN
(CARRY)
V
SS
V
DD
Rate Output
Inhibit Out (Carry)
Inhibit Input (Carry)
Negative Supply Voltage Positive Supply Voltage
2/11
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TRUTH TABLE
HCF4089B
INPUTS OUTPUTS
Number of Pulses or Input Logic Level
D C B A CLOCK INH IN STR. CAS. CLEAR SET OUT OUT
LLLL16LLLLLLH11 LLLH16LLLLL1111 LLHL16LLLLL2211 LLHH16LLLLL3311 LHLL16LLLLL4411 LHLH16LLLLL5511 LHHL16LLLLL6611
LHHH16LLLLL7711 HLLL16LLLLL8811 HLLH16LLLLL9911 HLHL16LLLLL101011 HLHH16LLLLL111111 HHLL16LLLLL121211 HHLH16LLLLL131311 HHHL16LLLLL141411 HHHH16LLLLL151511 XXXX 16 H L L L L XXXX16LHLLLLH11 XXXX 16 L L H L L H * 1 1 H X X X 16 L L L H L 16 16 H L
L X X X 16 L L L H L L H H L XXXX 16 L L L L H L H L H
X : Don’t Care
:
Depends on internal state of counter
•
*: Output sam e as the first 1 6 l in es of this truth tabl e (depending on values of A, B, C, D)
Number of Pulses or Output Logic
Level
••
INH
OUT
H
"15" OUT
•
LOGIC DIAGRAM
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HCF4089B
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
P
Supply Voltage
DD
DC Input Voltage -0.5 to VDD + 0.5
I
I
DC Input Current
I
Power Dissipation per Package 200 mW
D
-0.5 to +22 V
10 mA
±
V
Power Dissipation per Output Transistor 100 mW
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
All voltage values ar e referred to V
Operating Temperature
op
Storage Temperature
stg
pin voltage.
SS
-55 to +125 °C
-65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
T
Supply Voltage
DD
Input Voltage 0 to V
I
Operating Temperature
op
3 to 20 V
DD
-55 to 125 °C
V
4/11
Page 5
DC SPECIFICATIONS
Symbol Parameter
I
Quiescent Current 0/5 5 0.04 5 150 150
L
V
High Level Output
OH
Voltage
Low Level Output
V
OL
Voltage
High Level Input
V
IH
Voltage
Low Level Input
V
IL
Voltage
Output Drive
I
OH
Current
Output Sink
I
OL
Current
Input Leakage
I
I
Current
C
Input Capacitance
I
HCF4089B
Test Condition Value
T
= 25°C
V
(V)
V
I
(V)
|I
|
O
O
(µA)
V
DD
(V)
A
Min. Typ. Max. Min. Max. Min. Max.
0/10 10 0.04 10 300 300 0/15 15 0.04 20 600 600 0/20 20 0.08 100 3000 3000
0/5 <1 5 4.95 4.95 4.95
0/15 <1 15 14.95 14.95 14.95
5/0 <1 5 0.05 0.05 0.05
15/0 <1 15 0.05 0.05 0.05
0.5/4.5 <1 5 3.5 3.5 3.5
1.5/13.5 <1 15 11 11 11
4.5/0.5 <1 5 1.5 1.5 1.5
13.5/1.5 <1 15 4 4 4 0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1 0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36
0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9 0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4
0/5 0.4 <1 5 0.44 1 0.36 0.36
0/15 1.5 <1 15 3.0 6.8 2.4 2.4 0/18 Any Input 18
-5
10
±
Any Input 5 7.5 pF
-40 to 85°C -55 to 125°C
0.1
±
1
±
1
±
Unit
A
µ
V0/10 <1 10 9.95 9.95 9.95
V10/0 <1 10 0.05 0.05 0.05
V1/9 <1 10 7 7 7
V9/1 <1 10 3 3 3
mA
mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9
A
µ
The Noi se Margin for bot h " 1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
DYNAMIC ELECTRICAL CHARACTERISTICS (T
= 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
amb
Test Condition Value (*) Unit
Symbol Parameter
t
PHL tPLH
Propagation Delay Time CLOCK to OUT
V
DD
(V)
Min. Typ. Max.
5 110 220
15 45 90
t
PHL tPLH
t
PHL tPLH
t
PHL tPLH
Propagation Delay Time CLOCK or STROBE to OUT
Propagation Delay Time CLOCK to INHIBIT High Level to Low Level
Propagation Delay Time LOW Level to HIGH Level
5 150 300
15 60 120
5 360 720
15 110 220
5 250 500
15 75 150
ns10 55 110
ns10 75 150
ns10 160 320
ns10 100 200
5/11
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HCF4089B
Symbol Parameter
t
PHL tPLH
Propagation Delay Time CLEAR to OUT
(V)
V
DD
5 380 760
15 130 260
t
PHL tPLH
Propagation Delay Time CLOCK to "9" or "15" OUT
5 300 600
15 90 180
t
PHL tPLH
Propagation Delay Time CASCADE to OUT
590180
15 35 70
t
PHL tPLH
t
PHL tPLH
Propagation Delay Time INHIBIT IN to INHIBIT OUT
Propagation Delay Time SET to OUT
5 160 320
15 55 110
5 330 660
15 110 220
t
THL tTLH
Transition Time 5 100 2 00
15 40 80
f
CL
Maximum Clock Frequency
5 1.2 2.4
15 3.5 7
Clock Pulse Width 5 330 165
t
W
15 100 50
t
Clock Rise or Fall Time 5 15
r, tf
15 15
SET or CLEAR pulse
t
W
Width
5 160 80
15 60 30
t
setup
t
INHIBIT Input Set-Up Time, High Level to Low Level
INHIBIT Input Removal
R
Time
5 100 50
15 20 10
5 240 120
15 110 5 5
Minimum SET Removal
t
R
Time
5 150 75
15 50 25
CLEAR Removal Time 5 60 30
t
R
15 30 15
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
Test Condition Value (*) Unit
Min. Typ. Max.
ns10 175 350
ns10 125 250
ns10 45 90
ns10 75 150
ns10 150 300
ns10 50 100
MHz10 2.5 5
ns10 170 85
µ
ns10 90 45
ns10 40 20
ns10 130 6 5
ns10 80 40
ns10 40 20
s10 15
6/11
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HCF4089B
APPLICATION NOTES
For words of more than 4 bits, HCF4089B device may be cascaded in two different modes : an ADD mode and a MULTIPLY mode.
TWO HCF4089B’S CASCADED IN THE "ADD" MODE WITH A PRESET NUMBER OF 189
In the ADD mode some of the gap s left by the more significant unit at the count of 15 are filled in by the less significant units. For example, when two units are cascaded in the ADD mode and programmed to 11 and 13, respectively, the mo re significant unit will have 11 output pulses and the other unit will have 13 outp ut pulses for ev ery 256 input pu l ses for a total of : 11 13 189
+  = 
16 256 256
TWO HCF4089B’S CASCADED IN THE "MULTIPLY" MODE FOR MULTIPLICATION OF TWO VARIABLES A AND B WITH LOOP CIRCUIT CONTROL
A B 1 N When the loop stabilities rate R2 = rate R3, thus fclock( • 16 16 16 16
= fclock ( •
)
)
therefore N = AB
7/11
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HCF4089B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitanc e)
= 200K
R R
Ω
L
= Z
of pulse generator (typically 50Ω)
T
OUT
8/11
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HCF4089B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065 b 0.5 0.020
b1 0.25 0.010
D 20 0.787 E 8.5 0.335 e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050
P001C
9/11
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HCF4089B
SO-16 MECHANICAL DATA
DIM.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007 a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45˚ (typ.)
D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050
e3 8.89 0.350
F 3.8 4. 0 0. 149 0. 157 G 4.6 5. 3 0. 181 0. 208 L 0.5 1.27 0.019 0.050
M 0.62 0.024
S ˚ (max.)
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
8
10/11
PO13H
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HCF4089B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility f or the consequences of use of such informatio n nor for any infringement of paten ts or o ther rig hts of t hird part ies which ma y result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previousl y suppl ied. STM icroel ectronics produc ts are not auth orized for use as c ritica l compone nts in l ife s upport dev ices or systems without express written approval of STMicroelectronics.
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