JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTI ON OF B SERI ES CMOS
DEVICES"
DESCRIPTION
HCF4054B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
DIPSOP
ORDER CODES
PACKAGETUBET & R
DIPHCF4054BEY
SOPHCF4054BM1HCF4054M013TR
HCF4054B provides level shifting similar to
HCF4055B and HCF4056B, independently
strobed latches, and common DF control on 4
signal lines. This device is intended to provide
drive signal compatibility with HCF4055B and
HCF4056B 7-segment decoder types for the
decimal point, colon, polarity, and similar display
lines. A level-shifted high amplitude DF output can
be obtained from any HCF4054B output line by
connecting the corresponding input and strobe
lines to a low and high levels. HCF4054B may
also be utilized for logic level "up conversion" or
"down conversion" respectively. For example,
input signal swings (V
to VSS) from +5V to 0V
DD
PIN CONNECTION
1/11September 2002
Page 2
HCF4054B
can be converte d to outp ut signal swing s (VDD to
V
) of +5V to -5V. The level shifted function
EE
permits the use of different input and output signal
swings. The input swings from a low l evel of V
to a hi gh level of V
from a low level of V
V
. Thus, the input and output swings can be
DD
while the outputs swings
DD,
to the same high level of
EE
SS
selected independently of each ot her over a 3 to
18V range. V
may be connected to VEE when
SS
no level-shift function is required. Data is
transferred from input to output by placing a high
voltage level at the strobe input. A low voltage
level at the strobe input latches the data input and
the corresponding output segments remain
selected (or non selected) while the strobe is low.
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
6, 5, 4, 3
9, 11, 13, 15IN1 to IN4Inputs
10, 12, 14, 1
2
7
8
16
OUT1 to
OUT4
STROBE1
STROBE4
DISPLAY
FREQ. IN
V
EE
V
SS
V
DD
TRUTH TABLE
Outputs
Strobe Input
Display Frequency Input
Negative Supply Voltage
Negative Supply Voltage
Positive Supply Voltage
DFINSTROBEOUT
LLHL
HLHH
LHHH
HHHL
XXL *
X = Don’t Care.
(*) Depe nds upon the input mode p reviously applied wh en S T =1.
2/11
Page 3
LOGIC DIAGRAM
HCF4054B
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
P
Supply Voltage
DD
DC Input Voltage-0.5 to VDD + 0.5
I
I
DC Input Current
I
Power Dissipation per Package200mW
D
-0.5 to +22V
10mA
±
V
Power Dissipation per Output Transistor100mW
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage value s are referred to V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibi lity f or the
consequences of use of such informatio n nor for any infringement of paten ts or o ther rig hts of t hird part ies which ma y result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previousl y suppl ied. STM icroel ectronics produc ts are not auth orized for use as c ritica l compone nts in l ife s upport dev ices or
systems without express written approval of STMicroelectronics.
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