Page 1
ANALOG MULTIPLEXER/DEMULTIPLEXER
■ LOW "ON" RESISTANCE : 125Ω (Typ.)
OVER 15V p.p SIGNAL-INPUT RANG E FOR
V
DD-VEE
■ HIGH "OFF" RESISTANCE : CHANNEL
LEAKAGE ± 100pA (Typ.) at V
■ BINARY ADDRESS DECODING ON CHIP
■ HIGH DEGREE OF LINEARITY : < 0.5%
DISTORTION TYP. at f
V
DD-VSS
■ VERY LOW QUIESCENT POWER
DISSIPATION UNDER ALL DIGITAL
CONTROL INPUT AND SUPPLY
CONDITIONS : 0.2
at V
■ MATCHED SWITCH CHARACTERISTICS :
R
ON
■ WIDE RANGE OF DIGITAL AND ANALOG
SIGNAL LEVELS : DIGITAL3 to 20,
ANALOG TO 20V p.p.
■ QUIESCENT CURRENT SPECIFIED UP TO
20V
■ 5V, 10V AND 15V PARAMETRIC RATINGS
■ INPUT LEAKAGE CURRENT
I
= 100nA (MAX) AT VDD=18VTA= 25°C
I
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
PIN CO NNECTION
= 15V
DD-VEE
=1KHz,VIS=5Vpp,
IS
> 10V, RL = 10KΩ
µW(Typ.)
DD-VSS=VDD-VEE
=10V
=5Ω (Typ.) FOR VDD-VEE= 15V
=18V
HCF4051B
SINGLE 8-CHANNEL
DIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4051BEY
SOP HCF4051BM1 HCF4051M013TR
DESCRIPTION
The HCF4051B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4051B analog multiplexer/demultiplexer
is a digitally controlled analog switch having low
ON impedance and very low OFF leaka ge current.
This multiplexer circuit dissipate extremely low
quiescent power over the full V
V
supply voltage range, independent of the
EE
DD-VSS
logic state of the c ontrol signals.
When a logic "1" is present at the i nhibit input
terminal all channel are off. This device is a single
8-channel multiplexer having three binary c ontrol
inputs, A, B, and C, and an inhibit input. The three
binary signals select 1 of 8 channels to be turned
on, and connect one of the 8 inp uts to the output.
and VDD-
1/10October 2002
Page 2
HCF4051B
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
11, 10, 9 A, B, C Binary Control Inputs
6 INH Inhibit Inputs
13, 14, 15,
12,1,5,2,4
3
7
8
16
TRUTH TABLE
0to7
CHANNEL
IN/OUT
COM OUT/
V
V
V
IN
EE
SS
DD
Indipendent inputs/outputs
Common Output/Input
Supply Voltage
Negative Supply Voltage
Positive Supply Voltage
INHIBIT C B A
0 000 0
0 001 1
0 010 2
0 011 3
0 100 4
0 101 5
0 110 6
0 111 7
1 XXX NONE
FUNCTIONAL DIAGRAM
INPUT STATES
"ON" CHANNEL (S)
2/10
Page 3
HCF4051B
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
(*) 500mWat 65
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
T
Supply Voltage
DD
DC Input Voltage -0.5 to VDD+ 0.5
I
DC Input Current
I
I
Power Dissipation per Package 500 (*) mW
D
-0.5 to +22 V
± 10 mA
Power Dissipation per Output Transistor 100 mW
Operating Temperature
op
Storage Temperature
stg
pin voltage.
°C; derate to 300mW by 10mW/°Cfrom65°Cto85°C
Supply Voltage
DD
Input Voltage 0 to V
I
Operating Temperature
op
SS
-55 to +125 °C
-65 to +150 °C
3to20 V
DD
-55 to 125 °C
V
V
3/10
Page 4
HCF4051B
DC SPECIFICATIONS
Test Condition Value
Symbol Parameter
I
Quiescent Device
L
Current (all
switches ON or all
switches OFF)
V
(V)
V
V
IS
EE
(V)
(V)
SS
V
DD
(V)
5 0.04 5 150 150
10 0.04 10 300 300
15 0.04 20 600 600
20 0.08 100 3000 3000
SWITCH
Resistance
R
ON
∆
Resistance ∆
ON
RON
(between any 2 of
4 switches)
OFF* Channel Leakage
0<
0<
V
V
VI<
DD
VI<
DD
00
00
0018 ±0.1 100 1000 1000 nA
5 470 1050 1200 1200
15 125 280 360 360
510
15 5
Current (All
Channel OFF)
(COMMON O/I)
OFF* Channel Leakage
0018 ±0.1 100 1000 1000 nA
Current (Any
Channel OFF)
C
Input Capacitance
I
Output
C
O
Capacitance
C
Feedthrough 0.2
IO
-5 -5 5
CONTROL (Address or Inhibit)
Input Low Voltage
V
IL
= VDD
V
Input High Voltage 5 3.5 3.5 3.5
IH
thru
1KΩ
V
EE=VSS
RL=1KΩ
to V
SS
IIS<2µA
5 1.5 1.5 1.5
15 4 4 4
(on all OFF
channels)
I
* Determined by minimum feasible leakage measurement for automating testing.
Input Leakage
IH,IIL
Current
Input Capacitance
C
I
VI= 0/18V
15 11 11 11
18
T
Min. Typ. Max. Min. Max. Min. Max.
= 25°C
A
-40 to 85°C -55 to 125°C
5
30
-3
±10
±0.1 ±1 ±1 µA
5 7.5 pF
Unit
µA
Ω10 180 400 520 520
Ω10 10
pF
V10 3 3 3
V10 7 7 7
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Page 5
HCF4051B
DYNAMIC ELECTRICAL CHARACTERISTICS (T
fall time = 20 ns )
Test Condition Value Unit
Parameter
V
(V)
Propagation Delay
Time (signal input to
output)
Frequency Response
Channel "ON" (sine
wave input) at
20 log V
O/VI
= - 3dB
=V
Feedthrough (all
channels OFF) at
20 log V
O/VI
= - 40dB
=V
Frequency Signal
Crosstalk at
20 log V
O/VI
= -40dB
Sine Wave Distortion
= 1KHz Sine Wave
f
IS
=V
=V
CONTROL (Address or Inhibit)
Propagation Delay:
Address to Signal
OUT (Channels ON
or OFF)
Propagation Delay:
Inhibit to Signal OUT
(Channel turning ON)
0 0 5 360 720
0 0 10 160 320
0 0 15 120 240
-5 0 5 225 450
0
0 0 10 160 320
0 0 15 120 240
-10 0 5 200 400
Propagation Delay:
Inhibit to Signal OUT
(Channel turning
OFF)
Address or Inhibit to
Signal Crosstalk
(1) Both ends of channel.
* Peak to Peak voltage symmetrical about (V
0
01090210
01570160
-10 5 130 300
0
EE
R
L
(KΩ)
200
1 5(*) 10
SS
1 5(*) 10
SS
1 5(*) 10
SS
f
I
(KHz)
V
V
(V)
DD
I
2(*) 5 0.3
10 1
SS
5(*) 15 0.12
1
10
(1)
10
DD-VEE
)/2
= 25°C, CL= 50pF, all input square wave rise and
amb
V
(V)
SS
V
(V)
DD
Min. Typ. Max.
53060
15 11 20
V
at Common
O
OUT/IN
V
at any
O
channel
at Common
V
O
OUT/IN
V
at any
O
channel
20
60
12
8
Between any 2
channels
3 MHz
05 360720
5 200 450
V
010
C=VDD-VSS
(square wave)
65
ns10 15 30
MHz
MHz
%3(*) 10 0.2
ns
ns
ns
mV
peak
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Page 6
HCF4051B
TYPICAL BIAS VOLTAGES
The ADDRESS (digtal-control inputs) and INHIBIT logic levels are : "0"=VSSand "1"=VDD. The analog signal (through the TG) may swing
from VEEto V
SPECIAL CONSIDERATIONS
Control of analog signals up to 20V peak t o peak
can be achieved by digital signal amplitudes of 4.5
to 20V (if V
can be controlled; for V
above 13V, a V
required. For example, if V
V
EE
can be controlled by digital inputs of 0 to 4.5V. In
DD
DD-VSS
=3V,aVDD-VEEof up t o 13V
DD-VEE
-VSSof at least 4.5V is
DD
level differences
=+5,VSS=0,and
DD
= -13.5, analog s ignals from -13.5V to 4.5V
certain appl ications , the external load resistor
current may include both V
components. To avoid drawin g V
and signal-line
DD
current when
DD
switch current flows into the transmission gate
inputs, the voltage drop across the bidirectional
switch must not exceed 0,8V (calculated from R
values shown in DC SPECIFICATIONS). No V
current will flow through RLif the switch current
flows into lead 3.
ON
DD
TEST CIRCUIT
CL= 50pF or equivalent (includes jig and probe capacitance)
R
=200KΩ
L
RT=Z
6/10
of pulse generator (typically 50Ω)
OUT
Page 7
WAVEFORM 1 : CHANNE L BEING TURNED ON (RL=1KΩ, f=1MHz; 50% duty cycle)
HCF4051B
WAVEFORM 2 : CHANNE L BEING TURNED OFF (R
=1KΩ, f=1MHz; 50% duty cycle)
L
7/10
Page 8
HCF4051B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
8/10
P001C
Page 9
SO-16 MECHANICAL DATA
HCF4051B
DIM.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45˚ (typ.)
D 9.8 10 0.385 0.393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0. 149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.62 0.024
S ˚ (max.)
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
8
PO13H
9/10
Page 10
HCF4051B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibi lity f or the
consequences of use of such informatio n nor for any infringement of paten ts or o ther rig hts of t hird part ies which ma y result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previousl y suppl ied. STM icroel ectronics produc ts are not auth orized for use as c ritica l compone nts in l ife s upport dev ices or
systems without express written approval of STMicroelectronics.
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