Datasheet HCF4018BE Specification

Page 1
HCF4018B
PRESETTABLE DIVIDE-BY-N COUNTER
■ MEDIUM SPEED OPERATION 10 MHz (T yp. )
at V
■ FULLY STATIC OPERATION
- VSS= 10V
DD
CHARACTERISTICS
■ QUIESCENT CURRENT SPECIFIED UP TO
20V
■ 5V, 10V AND 15V PARAMETRIC RATINGS
■ INPUT LEAKAGE CURRENT
I
= 100nA (MAX) AT VDD = 18V TA = 25°C
I
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTI ON OF B SERI ES CMOS DEVICES"
DESCRIPTION
The HCF4018B is a m onolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4018B consist of 5 Johnson counter stages, buffered Q outputs f rom each s tage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4 or 2 counter configuration can be implemented by feeding the Q5
, Q4, Q3, Q2, Q1 signals, respectively, back to the data input. Divide-by-9, 7, 5, or 3 counter configurations c an be implemented by the use of a HCF4011B gate
DIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4018BEY
SOP HCF4018BM1 HCF4018M013TR
package to properly gate the feedback connection to the DATA input. Divide-by-functions greater than 10 can be achieved by use of multiple HCF4018B units. The counter is advanced one count at the positive clock signalstransition. Schmitt trigger action on the clock line permits unlimited clock rise a nd fall tim es. A high RESET signal clears the counter to an all-zero condition. A high PRESENT-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence.
PIN CONNECTION
1/11September 2001
Page 2
HCF4018B
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
2, 3, 7, 9, 12
1 DATA Data Input
4, 5, 6, 11,
13 15 RESET Reset Input 14 CLOCK Clock Input
10
8
16
FUNCTIONAL DIAGRAM
JAM1 to
JAM5
to Q5 Buffered Outputs
Q1
PRESET ENABLE
V
SS
V
DD
Jam Inputs
Preset Enable Input Negative Supply Voltage
Positive Supply Voltage
2/11
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LOGIC DIAGRAM
HCF4018B
TIMING CHART
3/11
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HCF4018B
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values ar e referred to V
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
T
Supply Voltage
DD
DC Input Voltage -0.5 to VDD + 0.5
I
I
DC Input Current
I
Power Dissipation per Package 200 mW
D
-0.5 to +22 V
± 10 mA
Power Dissipation per Output Transistor 100 mW Operating Temperature
op
Storage Temperature
stg
pin voltage.
SS
Supply Voltage
DD
Input Voltage 0 to V
I
Operating Temperature
op
-55 to +125 °C
-65 to +150 °C
3 to 20 V
DD
-55 to 125 °C
V
V
4/11
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DC SPECIFICATIONS
Test Condition Value
T
Symbol Parameter
I
Quiescent Current 0/5 5 0.04 5 150 150
L
V
(V)
V
I
(V)
|I
|
O
O
(µA)
V
DD
(V)
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
0/10 10 0.04 10 300 300 0/15 15 0.04 20 600 600 0/20 20 0.08 100 3000 3000
V
High Level Output
OH
Voltage
0/5 <1 5 4.95 4.95 4.95
0/15 <1 15 14.95 14.95 14.95
Low Level Output
V
OL
Voltage
5/0 <1 5 0.05 0.05 0.05
15/0 <1 15 0.05 0.05 0.05
High Level Input
V
IH
Voltage
0.5/4.5 <1 5 3.5 3.5 3.5
1.5/13.5 <1 15 11 11 11
V
IL
Low Level Input Voltage
4.5/0.5 <1 5 1.5 1.5 1.5
13.5/1.5 <1 15 4 4 4
I
OH
Output Drive Current
0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1
0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36 0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9 0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4
I
OL
Output Sink Current
0/5 0.4 <1 5 0.44 1 0.36 0.36
0/15 1.5 <1 15 3.0 6.8 2.4 2.4
Input Leakage
I
I
Current
C
Input Capacitance
I
The Noi se Margin for bot h " 1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
0/18 Any Input 18
Any Input 5 7.5 pF
±10
-5
-40 to 85°C -55 to 125°C
±0.1 ±1 ±1 µA
HCF4018B
Unit
µA
V0/10 <1 10 9.95 9.95 9.95
V10/0 <1 10 0.05 0.05 0.05
V1/9 <1 10 7 7 7
V9/1 <1 10 3 3 3
mA
mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9
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HCF4018B
DYNAMIC ELECTRICAL CHARACTERISTICS (T
Symbol Parameter
t
PLH tPHL
t
THL tTLH
t
t
setup
PRESET
t
PLH, tPHL
t
REM
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) At PRESET ENABLE or JAM inputs
Propagation Delay Time 5 200 400
Transition Time 5 100 200
Maximum Clock Input
f
CL
Frequency
Minimum Clock Pulse
t
W
Width
Clock Input Rise or Fall
, t
r
f
Time
Data Setup Time Minimum Clock Inhibit
Data Input Hold-Time 5 140 70
t
H
(1)
or RESET OPERATION
Propagation Delay Time (reset or reset to Q
Preset or Reset Pulse
t
W
Width
)
Preset or Reset Removal Time
(V)
V
DD
15 65 130
15 40 80
536
15 8.5 17
5 160 80
15 50 25
5
15
54020
15 6 3
15 60 30
5 275 550
15 90 180
5 160 80
15 50 25
58040
15 20 10
= 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
amb
Test Condition Value (*) Unit
Min. Typ. Max.
ns10 90 180
ns10 50 100
MHz10 7 14
ns10 70 35
unlimited µs10
ns10 12 6
ns10 80 40
ns10 125 250
ns10 70 35
ns10 30 15
6/11
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TYPICAL APPLICATION
External connections for divide by 10, 9, 8, 7, 6, 5, 4, 3, 2 operation
DIVIDE BY 10 Q5
DIVIDE BY 8 Q DIVIDE BY 6 Q DIVIDE BY 4 Q DIVIDE BY 2 Q
4 3 2 1 NO CONNECTED
CONNECTED BACK TO "DATA"
HCF4018B
NO EXTERNAL COMPONENTS
REQUIRED
7/11
Page 8
HCF4018B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance)
= 200KΩ
R
L
R
= Z
of pulse generator (typically 50Ω)
T
OUT
8/11
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HCF4018B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065 b 0.5 0.020
b1 0.25 0.010
D 20 0.787 E 8.5 0.335 e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050
P001C
9/11
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HCF4018B
SO-16 MECHANICAL DATA
DIM.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007 a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050
M 0.62 0.024
S8° (max.)
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
10/11
PO13H
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HCF4018B
Information furnished is bel ieved to be accurate and reliable. However, STMicroe lectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No li cense is granted by implica tion or otherwise under any pat ent or patent rights of S TMicroelec tronics. Specifications mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or systems without express written approval of STMicroelectronics.
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