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HCF40163B
SYNCHRONOUS PROGRAMMABLE 4-BIT BINARY
COUNTER WITH SYNCHRONOUS CLEAR
■ INTERNAL LOOK-AHEAD FOR FAST
COUNTING
■ CARRY OUTPUT FOR CASCADING
■ SYNCHRONOUSLY PROGRAMMABLE
■ LOW-POWER TTL COMPATIBILITY
■ STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
■ QUIESCENT CURRENT SPECIF . UP TO 20V
■ 5V , 10V AND 15V PARAMETRIC RAT INGS
■ INPUT LEAKAGE CURRENT
I
= 100nA (MAX) AT VDD = 18V TA = 25°C
I
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTI ON OF B SERI ES CMOS
DEVICES"
DESCRIPTION
HCF40163B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
HCF40163B is a 4-bit synchronous programmable
counter. The CLEAR
low level at the CLEAR
function is synchronous. A
input sets all four ou tputs
low on the next positive CLOCK edge. A low level
at the LOAD inputs disables the counter and
causes the output to agree with the set-up data
after the following CLOCK pulse regardless of the
condition of the ENABLE inputs. The carry
DIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP HCF40163BEY
SOP HCF40163BM1 HCF40163M013TR
look-ahead circuitry provides for cascading
counter for n-bit synchronous application without
additional gating. Counting is enabled when both
the PE and TE inputs are high. The TE input is fed
forward to enable COUT. This enable output
produces a positive output pulse with a duration
approximately equa l to the positive port ion of the
Q1 output. This positive ove rflow carry pulse can
be used to enable suc cessive cascaded stages.
Logic transitions at the PE and TE inputs may
occur when the clock is either high or low.
PIN CONNECTION
1/14September 2002
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HCF40163B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1 CLEAR
2 CLOCK
3, 4, 5, 6 P1 to P4 Data Inputs
7 PE Count Enable Input
10 TE Count Enable Carry Input
9LOAD
14, 13, 12,
11
15 CARRY OUT Terminal Count Output
8
16
Q1 to Q4 Flip Flop Outputs
V
SS
V
DD
Asynchronous Master
Reset
Clock Input (LOW to
HIGH, Edge-trigge red)
Parallel Enable Input
Negative Supply Voltage
Positive Supply Voltage
LOGIC DIAGRAM
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TRUTH TABLE
CLOCK CLR LOAD PE TE OPERATION
H L X X PRESET
HHLXNC
HHXLNC
HHHHCOUNT
LXXXX
HXXXX
(X) : Don’t Care
NC : No Change
TIMING DIAGRAM
HCF40163B
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HCF40163B
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to V
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
T
Supply Voltage
DD
DC Input Voltage -0.5 to VDD + 0.5
I
I
DC Input Current
I
Power Dissipation per Package 200 mW
D
-0.5 to +22 V
10 mA
±
Power Dissipation per Output Transistor 100 mW
Operating Temperature
op
Storage Temperature
stg
pin voltage.
SS
Supply Voltage
DD
Input Voltage 0 to V
I
Operating Temperature
op
-55 to +125 °C
-65 to +150 °C
3 to 20 V
DD
-55 to 125 °C
V
V
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DC SPECIFICATIONS
Test Condition Value
T
Symbol Parameter
I
Quiescent Current 0/5 5 0.04 5 150 150
L
V
(V)
V
I
(V)
|I
|
O
O
(µA)
V
DD
(V)
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
0/10 10 0.04 10 300 300
0/15 15 0.04 20 600 600
0/20 20 0.08 100 3000 3000
V
High Level Output
OH
Voltage
0/5 <1 5 4.95 4.95 4.95
0/15 <1 15 14.95 14.95 14.95
Low Level Output
V
OL
Voltage
5/0 <1 5 0.05 0.05 0.05
15/0 <1 15 0.05 0.05 0.05
High Level Input
V
IH
Voltage
0.5/4.5 <1 5 3.5 3.5 3.5
1.5/13.5 <1 15 11 11 11
V
IL
Low Level Input
Voltage
4.5/0.5 <1 5 1.5 1.5 1.5
13.5/1.5 <1 15 4 4 4
I
OH
Output Drive
Current
0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1
0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36
0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9
0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4
I
OL
Output Sink
Current
0/5 0.4 <1 5 0.44 1 0.36 0.36
0/15 1.5 <1 15 3.0 6.8 2.4 2.4
Input Leakage
I
I
Current
C
Input Capacitance
I
The Noi se Margin fo r bot h " 1" and "0" le vel is: 1V min. wi th VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
0/18 Any Input 18
Any Input 5 7.5 pF
-5
10
±
-40 to 85°C -55 to 125°C
0.1
±
1
±
HCF40163B
Unit
A
µ
V0/10 <1 10 9.95 9.95 9.95
V10/0 <1 10 0.05 0.05 0.05
V1/9 <1 10 7 7 7
V9/1 <1 10 3 3 3
mA
mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9
1
±
A
µ
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HCF40163B
DYNAMIC ELECTRICAL CHARACTERISTICS (T
Symbol Parameter
t
PLH tPHL
t
PLH tPHL
t
PLH tPHL
t
setup
Propagation Delay Time
Clock to Q
Propagation Delay Time
Clock to C
OUT
Propagation Delay Time
TE to C
OUT
Setup Time
Data to Clock
t
setup
t
setup
Setup Time
Load
to Clock
Setup Time
PE or TE to Clock
t
t
THL tTLH
t
t
SETUP
t
t
(*) Typical temperat ure coeffici ent for all VDD value is 0.3 %/°C.
Hold Time 5 0
hold
Transition Time 5 10 0 200
Clock Input Pulse Width 5 170 85
t
W
Maximum Clock Input
f
CL
Frequency
Clock Input Rise or Fall
r tf
Time
Proagation Delay Time
Clear to Clock
Hold Time Clear to Clock 5 0
hold
Clear Removal Time 5 200 100
rem
(V)
V
DD
5 200 400
15 60 120
5 225 450
15 70 140
5 125 250
15 40 80
5 240 120
15 60 30
5 240 120
15 60 30
5 340 170
15 100 50
15 0
15 40 80
15 50 25
523
15 8 12
5200
15 15
5 340 170
15 100 50
15 0
15 70 35
= 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
amb
Test Condition Value (*) Unit
Min. Typ. Max.
ns10 80 160
ns10 95 190
ns10 55 110
ns10 90 45
ns10 90 45
ns10 140 70
ns10 0
ns10 50 100
ns10 70 35
MHz10 5.5 8.5
ns10 70
ns10 140 70
ns10 0
ns10 100 50
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HCF40163B
TEST CIRCUIT
CL = 50pF or equivalent (incl udes jig and p robe capacit ance)
R
= 200K
Ω
L
R
= Z
of pulse generator (typically 50Ω)
T
OUT
WAVEFORM 1 : PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (COUNT MODE) (f=1MHz;
50% duty cycle)
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HCF40163B
WAVEFORM 2 : SETUP AND HOLD TIMES (CLEAR MODE) (f=1MHz; 50% duty cycle)
WAVEFORM 3 : SETUP AND HOLD TIMES (PRESET MODE) (f=1MHz; 50% duty cycle)
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HCF40163B
WAVEFORM 4 : SETUP AND HOLD TIMES (COUNTENABLE MODE) (f=1MHz; 50% duty cycle )
WAVEFORM 5 : PROPAGATION DELAY TIMES (CASCADE MODE) (f=1MHz; 50% duty cycle)
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HCF40163B
TYPICAL APPLICATION: DETAIL OF FLIP-FLOPS (Asynchronous Clear)
TYPICAL APPLICATION: CASCADING CO UNTER PACKAGES IN THE PARALLE L-CLOCKED MODE
10/14
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HCF40163B
TYPICAL APPLICATION: CASCADING COUNTER PACKAGES IN THE RIPPLE-CLOCKED MODE
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HCF40163B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
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P001C
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SO-16 MECHANICAL DATA
HCF40163B
DIM.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45˚ (typ.)
D 9.8 10 0. 385 0. 393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0. 050
M 0.62 0.024
S ˚ (max.)
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
8
PO13H
13/14
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HCF40163B
Information furnished is believed to be accurate and reliable. However, STMicroelect ronics assumes no responsibility for t he
consequences of use of such informatio n nor for any infringement of paten ts or o ther rig hts of t hird part ies which ma y result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previousl y suppl ied. STM icroel ectronics produc ts are not auth orized for use as c ritica l compone nts in l ife s upport dev ices or
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