HCF4013B
DUAL D-TYPE FLIP FL OP
■ SET - RESET CAPABILITY
■ STATIC FLIP-FLOP OPERATION - RETAINS
STATE INDEFINITELY WITH CLOCK LEVEL
EITHER "HIGH" OR "LOW"
■ MEDIUM SP EED OPERATION 1 6MHz (TY P.)
CLOCK TOGGLE RATE AT 10V
■ STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
■ QUIESCENT CURRENT SPECIFIED UP TO
20V
■ 5V, 10V AND 15V PARAMETRIC RA T INGS
■ INPUT LEAKAGE CURRENT
I
= 100nA (MAX) AT VDD = 18V TA = 25°C
I
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTI ON OF B SERI ES CMOS
DEVICES"
DESCRIPTION
The HCF4013B is a m onolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4013B consists of two identical,
independent data type flip-flops. Each flip-flop has
independent data, set, reset, and clock inputs and
DIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4013BEY
SOP HCF4013BM1 HCF4013M013TR
Q and Q
register applications, and, by connecting Q
outputs. This device can be used for shift
output
to the data input, for counter and toggle
applications. The logic level present at the D input
is transferred to the Q
output during the
positive-going transition of the clock pulse. Setting
or resetting is independent of the clock and is
accomplished by a hi gh level on the set or reset
line, respectivel y
PIN CONNECTION
1/9September 2001
HCF4013B
INPUT EQUIVALENT CIRCUIT
LOGIC DIAGRAM
PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
3, 11
4, 10
CLOCK1
CLOCK2
RESET1
RESET2
Clock Inputs
Reset Inputs
6, 8 SET1, SET2 Set Inputs
5, 9 D1, D2 Data Inputs
1, 13 Q1, Q2 Data Outputs
2, 12 Q
7
14
1, Q2 Data Outputs
V
SS
V
DD
Negative Supply Voltage
Positive Supply Voltage
TRUTH TABLE
∆
CLOCK
XXHLLH
XXLHHL
X XHHHH
X : Don’t Care
∆ :
Low Level
D RESET SET Q Q
LLLLH
HLLHL
XLLQQ
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
P
Supply Voltage
DD
DC Input Voltage -0.5 to VDD + 0.5
I
I
DC Input Current
I
Power Dissipation per Package 200 mW
D
-0.5 to +22 V
± 10 mA
V
Power Dissipation per Output Transistor 100 mW
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values ar e referred to V
Operating Temperature
op
Storage Temperature
stg
pin voltage.
SS
-55 to +125 °C
-65 to +150 °C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
T
Supply Voltage
DD
Input Voltage 0 to V
I
Operating Temperature
op
3 to 20 V
DD
-55 to 125 °C
V
2/9
DC SPECIFICATIONS
Test Condition Value
T
Symbol Parameter
I
Quiescent Current 0/5 5 0.02 1 30 30
L
V
(V)
V
I
(V)
|I
|
O
O
(µA)
V
DD
(V)
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
0/10 10 0.02 2 60 60
0/15 15 0.02 4 120 120
0/20 20 0.04 20 600 600
V
High Level Output
OH
Voltage
0/5 <1 5 4.95 4.95 4.95
0/15 <1 15 14.95 14.95 14.95
Low Level Output
V
OL
Voltage
5/0 <1 5 0.05 0.05 0.05
15/0 <1 15 0.05 0.05 0.05
High Level Input
V
IH
Voltage
0.5/4.5 <1 5 3.5 3.5 3.5
1.5/13.5 <1 15 11 11 11
V
IL
Low Level Input
Voltage
4.5/0.5 <1 5 1.5 1.5 1.5
13.5/1.5 <1 15 4 4 4
I
OH
Output Drive
Current
0/5 2.5 <1 5 -1.36 -3.2 -1.15 -1.1
0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36
0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9
0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4
I
OL
Output Sink
Current
0/5 0.4 <1 5 0.44 1 0.36 0.36
0/15 1.5 <1 15 3.0 6.8 2.4 2.4
Input Leakage
I
I
Current
C
Input Capacitance
I
The Noi se Margin for both "1" and "0 " le vel is: 1V min. wi th VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
0/18 Any Input 18
Any Input 5 7.5 pF
±10
-5
-40 to 85°C -55 to 125°C
±0.1 ±1 ±1 µA
HCF4013B
Unit
µA
V0/10 <1 10 9.95 9.95 9.95
V10/0 <1 10 0.05 0.05 0.05
V1/9 <1 10 7 7 7
V9/1 <1 10 3 3 3
mA
mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9
3/9
HCF4013B
DYNAMIC ELECTRICAL CHARACTERISTICS (T
= 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
amb
Test Condition Value (*) Unit
Symbol Parameter
t
TLH tTHL
Propagation Delay Time
(CLOCK to Q or Q
outputs)
(V)
V
DD
Min. Typ. Max.
5 150 300
ns10 65 130
15 45 90
t
PLH
Propagation Delay Time
(SET to Q or RESET to Q
)
5 150 300
ns10 65 130
15 45 90
t
PHL
t
THL tTLH
Propagation Delay
Time(SET to Q
or RESET
to Q)
Transition Time 5 100 200
5 200 400
ns10 85 170
15 60 120
ns10 50 100
15 40 80
(1)
f
CL
Maximum Clock Input
Frequency
5 3.5 7
MHz10 8 16
15 12 24
Clock Pulse Width 5 140 70
t
W
ns10 60 30
15 40 20
(2)
, t
t
r
Clock Input Rise or Fall
f
Time
515
µs10 4
15 1
Set or Reset Pulse Width 5 180 90
t
W
ns10 80 40
15 50 25
t
setup
Data Setup Time 5 40 20
ns10 20 10
15 15 7
(*) Typical temperat ure coefficient for all VDD value is 0.3 %/°C.
(1) Input tr, tf = 5ns
(2) If more than unit is cascaded in a parallel clock ed application, tr should be m ade less than or equal to the sum of t he fixed propagati on
delay time at 15pF and th e t ransition tim e of the carry ou tput driving stage for the esti m ated capaci tive load.
4/9
HCF4013B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and p robe capacitance)
R
= 200KΩ
L
= Z
R
WAVEFORM 1 : CLOCK TO Qn, Qn PROPAGATION DELAY TIMES, Dn TO CLOCK SETUP AND
HOLD TIMES, CLOCK MINIMUM PULSE WITDH, MAXIMUM CLOCK FREQUENCY
(f=1MHz; 50% duty cycle)
of pulse generator (typically 50Ω)
T
OUT
5/9
HCF4013B
WAVEFORM 2 : PROPAGATION DELAY TIMES (Qn, Qn TO SET, RESET) , MIN IMU M PULSE W ID TH
(SET AND RESET) (f=1MHz; 50% duty cycl e)
6/9
HCF4013B
Plastic DIP-14 MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 1.39 1.65 0.055 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 15.24 0.600
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 2.54 0.050 0.100
P001A
7/9
HCF4013B
SO-14 MECHANICAL DATA
DIM.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 8.55 8.75 0.336 0.344
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 7.62 0.300
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.68 0.026
S8° (max.)
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
8/9
PO13G
HCF4013B
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