JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTI ON OF B SERI ES CMOS
DEVICES"
DESCRIPTION
The HCF4012B is a m onolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4012B DUAL 4-INPUT NAND GATE
provides the system designer with direct
DIPSOP
ORDER CODES
PACKAGETUBET & R
DIPHCF4012BEY
SOPHCF4012BM1HCF4012M013TR
implementation of the NAND function and
supplement the existing family of CMOS gates. All
inputs and outputs are buffered.
PIN CONNECTION
1/7September 2001
HCF4012B
INPUT EQUIVALENT CIRCUIT
LOGIC DIAGRAM
PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
6, 8NCNot Connected
2, 3, 4, 5A, B, C, DData Inputs
9, 10, 11, 12E, F, G, H Data Inputs
1, 13J, KData Outputs
14
7
V
SS
V
DD
Negative Supply Voltage
Positive Supply Voltage
TRUTH TABLE
INPUTSOUTPUTS
A, B, C, DE, F, G, HJ, K
LLH
LHH
HLH
HHL
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
P
Supply Voltage
DD
DC Input Voltage-0.5 to VDD + 0.5
I
I
DC Input Current
I
Power Dissipation per Package200mW
D
-0.5 to +22V
± 10mA
V
Power Dissipation per Output Transistor100mW
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values ar e referred to V
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