Datasheet HCF40105BE Specification

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HCF40105B

FIFO REGISTER

■ INDEPENDENT ASYNCHRONOUS INPUTS

AND OUTPUTS

■ 3-STATE OUTPUTS

■ EXPANDABLE IN EITHER DIRECTION

■ STATUS INDICATORS ON INPUT AND

OUTPUT

■ RESET CAPABILITY

■ ST ANDARDIZED, SYMMETRICAL OUTPUT

CHARACTERISTIC S

■

QUIESCENT CURRENT SPECIF. UP TO 20V

■ 5V , 10V AND 15V PARAMETRIC RATINGS

■ INPUT LEAKAGE CURRENT

= 100nA (MAX) AT VDD = 18V TA = 25°C

■ 100% TESTED FOR QUIESCENT CURRENT

■ MEETS ALL REQUIREMENTS OF JEDEC

JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTI ON OF B SERI ES CMOS DEVICES"

DESCRIPTION

HCF40105B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP packages. HCF40105B is a low power first-in-first-out (FIFO) "elastic" storage register that can store 164-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. "1" signifies that the position’s data is filled and "0" denotes a vacancy in that

DIP

ORDER CODES

PACKAGE TUBE T & R

DIP HCF40105BEY

position. The control flip-flop dete cts the state of the preceding flip-flop and c ommunicates its ow n status to the succeeding f lip-flop. When a control flip flop is in the "0" state and sees a "1" in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripples through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATA-OUT READY) indicates if the FIFO contains data. As the earliest data is removed from the bottom of the data stack (the output and), all data entered later will automatically propagate (ripple) toward the output.

PIN CONNECTION

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HCF40105B

INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION

1 2 DIR Data-In Ready

3 SI Shift In 15 SO Shift Out 14 DOR Data-Out Ready

4, 5, 6, 7 D0 to D3 Input Buffers

13, 12, 11,

9 MR Master Reset

8 VSS Negative Supply Voltage 16 VDD Positive Supply Voltage

FUNCTIONAL DIAGRAM

3-STATE

CONTROL

Q0 to Q3 Output Buffers

3-State Control

TRUTH TABLE

CONTROL INPUTS

CLR

HHHH H H H L Count Down H H L X Preset on Next Positive Clock Transition HLXX

L X X X Clear to Maximum Count

X : Don’t Care Clock connected t o Cl ock input Synchronous Operation : changes occur on negative to positive clock transitions.

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APE SPE CI/CE

PRESET MODE ACTION

Inhibit Counter

Synchronous

Asynchronous

Preset Asynchronously

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LOGIC DIAGRAM

HCF40105B

TIMING CHART

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HCF40105B

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to V

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

Supply Voltage

DC Input Voltage -0.5 to VDD + 0.5

DC Input Current

Power Dissipation per Package 200 mW

-0.5 to +22 V

10 mA

Power Dissipation per Output Transistor 100 mW Operating Temperature

Storage Temperature

stg

pin voltage.

Supply Voltage

Input Voltage 0 to V

Operating Temperature

-55 to +125 °C

-65 to +150 °C

3 to 20 V

-55 to 125 °C

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DC SPECIFICATIONS

Test Condition Value

Symbol Parameter

Quiescent Current 0/5 5 0.04 5 150 150

(V)

(µA)

(V)

= 25°C

Min. Typ. Max. Min. Max. Min. Max.

0/10 10 0.04 10 300 300 0/15 15 0.04 20 600 600 0/20 20 0.08 100 3000 3000

High Level Output

Voltage

0/5 <1 5 4.95 4.95 4.95

0/15 <1 15 14.95 14.95 14.95

Low Level Output

Voltage

5/0 <1 5 0.05 0.05 0.05

15/0 <1 15 0.05 0.05 0.05

High Level Input

Voltage

0.5/4.5 <1 5 3.5 3.5 3.5

1.5/13.5 <1 15 11 11 11

Low Level Input Voltage

4.5/0.5 <1 5 1.5 1.5 1.5

13.5/1.5 <1 15 4 4 4

Output Drive Current

0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1

0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36 0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9 0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4

Output Sink Current

0/5 0.4 <1 5 0.44 1 0.36 0.36

0/15 1.5 <1 15 3.0 6.8 2.4 2.4

Input Leakage

Current

Input Capacitance

The Noi se Margin fo r both "1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V

0/18 Any Input 18

Any Input 5 7.5 pF

-5

-40 to 85°C -55 to 125°C

0.1

HCF40105B

Unit

V0/10 <1 10 9.95 9.95 9.95

V10/0 <1 10 0.05 0.05 0.05

V1/9 <1 10 7 7 7

V9/1 <1 10 3 3 3

mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9

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HCF40105B

DYNAMIC ELECTRICAL CHARACTERISTICS (T

Symbol Parameter

Propagation Delay Time

PHL

Shift-out or Reset to Data out Ready

PZH tPLZ

PHZ tPLZ

THL tTLH

setup

Propagation Delay Time

PHL

Shift-in to Data-in Ready

Propagation Delay Time 3-State Control to Data-out

Propagation Delay Time 3-State Control to data-out

Ripple-trough Delay Input

PLH

to Output

Transition Time 5 100 200

Shift-in or Shift-out Rate 5 1.5 3

Shift-in Pulse Width 5 200 100

Shift-out Pulse Width 5 360 180

Shift-in or Shift-out Rise

Time

Shift-in Fall Time 5 15

Shift-out Fall Time 5 15

Data Setup Time 5 0

Data Hold Time 5 350 175

hold

Data-in Ready Pulse Width 5 260 520

(V)

5 185 370

15 65 130

5 160 320

15 45 90

5 140 280

15 40 80

5 100 200

15 40 80

524

15 0.7 1.4

15 40 80

15 4 8

15 60 30

15 100 50

515

15 15

15 5

15 0

15 120 60

15 70 140

= 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)

amb

Test Condition Value (*) Unit

Min. Typ. Max.

ns10 90 180

ns10 65 130

ns10 60 120

ns10 50 100

µs10 1 2

ns10 50 100

MHz10 3 6

ns10 80 40

ns10 160 80

µs10 15

µs10 5

ns10 0

ns10 150 75

ns10 100 120

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HCF40105B

Symbol Parameter

Data-out Ready Pulse

Width

(V)

5 220 440

15 665 130

Test Condition Value (*) Unit

Master Reset Pulse Width 5 200 100

15 60 30

(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.

TYPICAL APPLICATION: EXPANSION, 4 BIT-WIDE-BY-16 N-BITS LONG.

Min. Typ. Max.

ns10 90 180

ns10 90 45

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HCF40105B

TYPICAL APPLICATION: EXPANSION, 8 BITS-WIDE-BY-16 N-BITS LONG.

APPLICATION INFORMATION

LOADING DATA Data can be entered whenever the DATA-IN

READY (DIR) flag is high by a low to high transition on the SHIFT-IN (SI) input. This input must go low mom entarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily until the data has been transferred to the second location. The flag will remain low when all 16-word locations are filled with valid data, and further pulses on the SI in put will be ign ored until DIR goes high.

UNLOADING DATA As soon as the first word has rippled to the output,

DATA-OUT READY (DOR) goes high, and data can be removed by a falling edge on the SO input. This falling edge causes the DOR signal to go low while the word on the output is dum ped and the next word mov es to the output. As long as vali d data is available in the FIFO, the DOR s ignal will go high again signifying that the next word is ready at the output. When t he FIFO is empt y, DOR will remain low, and any further commands will be ignored until a "1" marker ripples down to the last control register, when DOR goe s high. Un loading of data is inhibited while the 3-state control input is high. The 3-state control signal should not be shifted from high to low (data outputs turned on)

while the SHIFT-OUT is at logic "0". This level change causes the first word to be shifted out (unloaded) immediately and the data to be lost.

CASCADING HCF40105B can be cascaded to form longer

registers simply by connect ing the DIR to SO a nd DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For w ords wider than 4 -bits, the DIR and the DOR outputs must be gated together with AND gates. T heir outputs drive the SI and SO inputs in p arallel, if ex panding is done in both directions.

3-STATE OUTPUTS In order to f acilitate data busi ng, 3-state outputs

are provided on the data output lines, while the load condition of the regi ster can be detected by the state of the DOR output.

MASTER RESET A high on the MASTER RESET (MR) sets all the

control logic marker bits to "0". DOR goes low and DIR goes high. The cont ents of the data register do not change, only declared invalid, an d will be superseded when the first word is loaded.

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TEST CIRCUIT

TEST SWITCH

, t

PLH

PHL

, t

PZL

PLZ

, t

PZH

PHZ

CL = 50pF or equivalent (in cludes jig and probe capac i t ance)

= 200K

R R

Ω

= Z

of pulse generator (typically 50Ω)

OUT

HCF40105B

Open

WAVEFORM 1 : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle)

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HCF40105B

WAVEFORM 2 : OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)

WAVEFORM 3 : MINIMUM SETUP AND HOLD TIME (f=1MHz; 5 0% duty cycl e )

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HCF40105B

Plastic DIP-16 (0.25) MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.77 1.65 0.030 0.065 b 0.5 0.020

b1 0.25 0.010

D 20 0.787 E 8.5 0.335 e 2.54 0.100

e3 17.78 0.700

F 7.1 0.280

I 5.1 0.201 L 3.3 0.130 Z 1.27 0.050

P001C

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HCF40105B

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibi lity f or the consequences of use of such informatio n nor for any infringement of paten ts or o ther rig hts of t hird part ies which ma y result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previousl y suppl ied. STM icroel ectronics produc ts are not auth orized for use as c ritica l compone nts in l ife s upport dev ices or systems without express written approval of STMicroelectronics.

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