Datasheet HCF40105B Datasheet (SGS Thomson Microelectronics)

HCC40105B

HCF 401 05 B

FIFO REGISTER

.INDEPENDENT ASYNCHRONOUS INPUTS

AND OUTPUTS

.3-STATEOUTPUTS

.EXPANDABLE IN EITHERDIRECTION

.STATUS INDICATORS ON INPUT AND OUT-

PUT

.RESETCAPABILITY

.STANDARDIZED, SYMMETRICAL OUTPUT

CHARACTERISTICS

.QUIESCENT CURRENT SPECIFIED AT 20V

FOR HCC DEVICE

.5V, 10V,AND 15VPARAMETRIC RATINGS

.INPUT CURRENTOF100nA AT 18V AND25°C

FOR HCC DEVICE

.100% TESTEDFOR QUIESCENTCURRENT

.MEETSALLREQUIREMENTSOFJEDECTEN-

TATIVE STANDARD No13A, ”STANDARD
SPECIFICATIONSFOR DESCRIPTION OF ”B”
SERIESCMOS DEVICES”

DESCRIPTION
TheHCC40105B (extended temperature range) and

HCF40105B (intermediate temperature range) are

monolithicintegratedcircuits,available in16-leaddual
in-line plastic orceramic package.

TheHCC/HCF40105B is alow-power first-in-first-out
(FIFO)”elastic”storageregisterthatcanstore164-bit
words. It iscapable ofhandling input and output data
atdifferent shiftingrates.Thisfeaturemakesitparticu­larly useful as a buffer between asynchronous sys­tems.Eachword position in the register is clocked by
a controlflip-flop, which stores a markerbit.A”1”sig­nifiesthattheposition’sdata is filledanda”0” denotes
a vacancy inthatposition. Thecontrolflip-flopdetects
the state of the preceding flip-flop and communicates
itsownstatus tothesucceeding flip-flop.When acon­trol flip-flop is in the ”0” state and sees a ”1” in the
preceding flip-flop, it generates a clock pulse that
transfers data from the preceding four data latches
intoitsownfourdata latches andresetsthepreceding
flip-flopto ”0”. The first and lastcontrolflip-flops have
buffered outputs. Since all empty locations ”bubble”
automatically tothe input end, and allvaliddataripple
throughtotheoutput end,thestatusof thefirstcontrol
flip-flop(DATA-IN READY)indicatesiftheFIFOisfull,
and the status of the last flip-flop (DATA-OUT

READY) indicates if the FIFO contains data. As the
earliest data areremoved from thebottomofthe data
stack(theoutputend), alldata entered later willauto­maticallypropagate (ripple) toward the output.

EY

(Plastic Package)

C1

(ChipCarrier)

ORDERCODES :

HCC40105BF HCF40105BEY

HCF40105BC1

PIN CON NECT I ONS

(CeramicPackage)

F

June 1989

1/12

HCC/HCF40105B

FUNCTIONAL DIAGRAM

ABSOLUTE MAXI MU M RATING S

Symbol Parameter Val ue Unit

V

* Supply Voltage : HCC Types

DD

HCF Types

V

Input Voltage – 0.5 to VDD+ 0.5 V

i

DC Input Current (any one input) ± 10 mA

I

I

P

Total Power Dissipation (per package)

tot

– 0.5to + 20
– 0.5to + 18

200

V
V

mW
Dissipation per Output Transistor
for T

T

T

Stresses above those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability.
* All voltage values are referred to VSSpin voltage.

Operating Temperature : HCC Types

op

Storage Temperature – 65 to + 150 °C

stg

= Full Package-temperature Range

op

HCF Types

100

–55to+125

–40to+85

mW

°C
°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

V

Supply Voltage : HC C Types

DD

HCF Types

V

Input Voltage 0 to V

I

T

Operating Temperature : HCC Types

op

HCF Types

3to18
3to15

DD

– 55 to + 125

–40to+85

V
V

V

°C
°C

2/12

LOGIC DIAGRAM

HCC/HCF40105B

TIMING DIAGRAM

3/12

HCC/HCF40105B

STATIC ELECTRICAL CHARACTERISTICS (over recommended operatingconditions)

Test Conditions Valu e

Symbol Parameter

(V) (V) (µA) (V)

I

L

Quiescent
Current

HCC
Types

0/ 5 5 5 0.04 5 150
0/10 10 10 0.04 10 300
0/15 15 20 0.04 20 600
0/20 20 100 0.08 100 3000

HCF
Types

OH

Output High

V

Voltage

0/ 5 5 20 0.04 20 150
0/10 10 40 0.04 40 300
0/15 15 80 0.04 80 600
0/ 5 < 1 5 4.95 4.95 4.95
0/10 < 1 10 9.95 9.95 9.95
0/15 < 1 15 14.95 14.95 14.95

OL

Output Low

V

Voltage

5/0 < 1 5 0.05 0.05 0.05
10/0 < 1 10 0.05 0.05 0.05
15/0 < 1 15 0.05 0.05 0.05

IH

Input High

V

Voltage

IL

Input Low

V

Voltage

OH

Output
Drive
Current

HCC
Types

I

0/ 5 2.5 5 – 2 – 1.6 – 3.2 – 1.15
0/ 5 4.6 5 – 0.64 – 0.51 – 1 – 0.36
0/10 9.5 10 – 1.6 – 1.3 – 2.6 – 0.9
0/15 13.5 15 – 4.2 – 3.4 – 6.8 – 2.4
0/ 5 2.5 5 – 1.53 – 1.36 – 3.2 – 1.1

HCF
Types

0/ 5 4.6 5 – 0.52 – 0.44 – 1 – 0.36
0/10 9.5 10 – 1.3 – 1.1 – 2.6 – 0.9
0/15 13.5 15 – 3.6 – 3.0 – 6.8 – 2.4

OL

Output
Sink
Current

HCC
Types

I

HCF
Types

I

IH,IIL

Input
Leakage

HCC
Types

Current

Types

IOH,IOL**

3-State
Output

Types
Leakage
Current

Input Capacitance Any Input 5 7.5 pF

C

I

*T
*T

* * Forcedoutput disable.

=–55°C for HCC device : – 40°C for HCF device.

Low

=+125°C for HCC device : + 85°C for HCF device.

High

TheNoiseMargin forboth ”1” and ”0” level is : 1V min. with VDD= 5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V.

Types

0/ 5 0.4 5 0.64 0.51 1 0.36
0/10 0.5 10 1.6 1.3 2.6 0.9
0/15 1.5 15 4.2 3.4 6.8 2.4
0/ 5 0.4 5 0.52 0.44 1 0.36
0/10 0.5 10 1.3 1.1 2.6 0.9
0/15 1.5 15 3.6 3.0 6.8 2.4

0/18

HCF

0/15

HCC

0/18 0/18 18 ± 0.4 ±10

HCF

0/15 0/15 15 ± 1.0 ±10

V

V

I

O

|IO|V

DD

T

* 25°CT

Low

Min. Max. Min. Typ. M ax. Min. Max.

0.5/4.5 < 1 5 3.5 3.5 3.5
1/9 < 1 10 7 7 7

1.5/13.5 < 1 15 11 11 11

4.5/0.5 < 1 5 1.5 1.5 1.5
9/1 < 1 10 3 3 3

13.5/1.5 < 1 15 4 4 4

18

± 0.1 ±10

–5

± 0.1 ± 1

Any Input

–5

15 ± 0.3 ±10

± 0.3 ± 1

–4

± 0.4 ± 12

–4

± 1.0 ± 7.5

High

Unit

*

µA

V

V

V

V

mA

mA

µA

µA

4/12

HCC/HCF40105B

DYNAMIC ELECTRICAL CHARACTERISTICS (T

=25°C,CL= 50 pF, RL= 200 kΩ,

amb

typical temperature coefficient for all VDDvalues is 0.3 %/°C, all inputrise and fall time = 20 ns)

Symbol Parameter

t

PHL

Propagation Delay Time
Shift-out or Reset to Data-out
Ready

t

PHL

Propagation Delay Time
Shift-in to Data-in Ready

t

PZH,tPZL

Propagation Delay Time
3-state Control to Data-out

t

PHZ,tPLZ

Propagation Delay Time
3-State Control to Data-out

t

PLH

Ripple-through Delay Input to
Output

t

THL,tTL H

f

t

WH

t

WL

t

t

t

t

setup

Transition Time 5 100 200

Shift-in or Shift-out Rate 5 1.5 3

I

Shift-in Pulse Width 5 200 100

Shift-out Pulse Width 5 360 180

Shift-in or Shift-out Rise Time 5 15

r

Shift-in Fall Time 5 15

f

Shift-out Fall Time 5 15

f

Data Setup Time 5 0

Test Conditions Value

(V) Min. T yp. Max.

V

DD

5 185 370
10 90 180
15 65 130

5 160 320
10 65 130
15 45 90

5 140 280
10 60 120
15 40 80

5 100 200
10 50 100
15 40 80

524
10 1 2
15 0.7 1.4

10 50 100
15 40 80

10 3 6
15 4 8

10 80 40
15 60 30

10 160 80
15 100 50

10 15
15 15

10 15
15 15

10 5
15 5

10 0
15 0

Unit

ns

ns

ns

ns

µs

ns

MHz

ns

ns

µs

µs

µs

ns

5/12

HCC/HCF40105B

DYNAMIC ELECTRICAL CHARACTERISTICS (continued)

Symbol Parameter

t

hold

Data Hold Time 5 350 175

Test Conditions Value

V

(V) Min. Typ . Max.

DD

10 150 75
15 120 60

t

WL

Data–in Ready Pulse Width 5 260 520

10 100 120
15 70 140

t

WL

Data–out Ready Pulse Width 5 220 440

10 90 180
15 665 130

t

WH

Master Reset Pulse Width 5 200 100

10 90 45
15 60 30

OutputLow (sink)CurrentCharacteristics. Output High (source) Current Characteristics.

Unit

ns

ns

ns

ns

TypicalTransition Timevs. Load Capacitance. Typical Dynamic Power Dissipation vs. Fre-

quency.

6/12

TEST CIRCUITS

Quiescent Device Current. Input Voltage.

Input Leakage Current. DynamicPower Dissipation.

HCC/HCF40105B

TYPICAL APPLICATIONS

EXPANSION, 4 BITS–WIDE–BY–16 N–BITS LONG.

7/12

HCC/HCF40105B

EXPANSION, 8 BITS–WIDE–BY–16 N–BITS LONG.

APPLICATIONS INFORMATION

LOADINGDATA
Datacanbe enteredwhenever theDATA-IN READY

(DIR) flag is high, by a low to high transition on the
SHIFT-IN(SI) input. This input must go lowmomen­tarily before the next wordis accepted by the FIFO.
The DIR flagwill go low momentarily, until the data
havebeentransferred tothesecondlocation. Theflag
will remain low when all 16-word locations are filled
withvaliddata,and further pulseson the SI input will
be ignored until DIR goeshigh.

UNLOADINGDATA
As soon as the first word has rippled to the output,

DATA-OUTREADY (DOR)goes high, anddatacan
beremovedbyafallingedgeontheSOinput.Thisfall­ing edge causes the DORsignal to go low whilethe
word on the output is dumped and the next word
moves to theoutput. Aslong as valid dataare avail­ableintheFIFO,theDORsignal willgohigh againsig­nifyingthat thenextword is readyattheoutput.When
theFIFOisempty, DOR will remain low, andany fur­ther commands will be ignored until a ”1” marker
ripples down to the last control register, when DOR
goes high. Unloading of data is inhibited whilethe3­statecontrol input is high. The 3-state control signal
should not be shifted from high to low (data outputs

turnedon)whiletheSHIFT-OUTisatlogic0.Thislevel
change would cause the first word to be shifted out
(unloaded) immediately and thedata tobe lost.

CASCADING
The HCC/HCF40105B can be cascaded to form

longer registers simply byconnecting the DIRto SO
and DOR to SI. In the cascaded mode, a MASTER
RESETpulsemustbeapplied afterthesupplyvoltage
isturnedon.Forwords wider than 4 bits,theDIRand
the DOR outputs mustbe gated together with AND
gates.TheiroutputsdrivetheSIandSOinputsinpar­allel, if expanding is donein both directions.

3-STATE OUTPUTS
In order to facilitate data busing, 3-state outputs are

provided on the data output lines, whiletheload con­dition of the register can be detected by the state of
theDORoutput.

MASTERRESET
Ahigh on theMASTERRESET (MR)setsall the con-

trol logic marker bits to ”0”. DOR goes low and DIR
goes high. The contents of the data register are not
changed, only declared invalid, and will be super­sededwhenthefirstwordisloaded.

8/12

Plastic DIP14 MECHANICAL DATA

HCC/HCF40105B

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 1.39 1.65 0.055 0.065

b 0.5 0.020

b1 0.25 0.010

D 20 0.787
E 8.5 0.335

e 2.54 0.100

e3 15.24 0.600

F 7.1 0.280

I 5.1 0.201
L 3.3 0.130
Z 1.27 2.54 0.050 0.100

mm inch

P001A

9/12

HCC/HCF40105B

Ceramic DIP14/1 MECHANICAL DATA

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 20 0.787
B 7.0 0.276
D 3.3 0.130
E 0.38 0.015

e3 15.24 0.600

F 2.29 2.79 0.090 0.110

G 0.4 0.55 0.016 0.022
H 1.17 1.52 0.046 0.060

L 0.22 0.31 0.009 0.012

M 1.52 2.54 0.060 0.100

N 10.3 0.406
P 7.8 8.05 0.307 0.317

Q 5.08 0.200

mm inch

10/12

P053C

PLCC20 MECHANICAL DATA

HCC/HCF40105B

DIM.

MIN. TYP. MAX. MIN. TYP. MAX.

A 9.78 10.03 0.385 0.395
B 8.89 9.04 0.350 0.356

D 4.2 4.57 0.165 0.180
d1 2.54 0.100
d2 0.56 0.022

E 7.37 8.38 0.290 0.330

e 1.27 0.050

e3 5.08 0.200

F 0.38 0.015
G 0.101 0.004
M 1.27 0.050

M1 1.14 0.045

mm inch

P027A

11/12

HCC/HCF40105B

Information furnished is believed tobe accurate and reliable.However, SGS-THOMSON Microelectronics assumes no responsability for the
consequences of useof such information nor for any infringement of patents or other rights of third parties which may results fromits use. No
license isgranted byimplication or otherwiseunder any patentor patent rights ofSGS-THOMSON Microelectronics. Specificationsmentioned
in this publication are subject to changewithout notice. This publication supersedes and replaces allinformation previously supplied.
SGS-THOMSON Microelectronicsproductsare notauthorized for use ascritical componentsinlife supportdevices orsystems without express
written approval of SGS-THOMSONMicroelectonics.

 1994 SGS-THOMSON Microelectronics - All RightsReserved

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