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HCF40104B
4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
■ MEDIUM SPEED OPERATION :
12 MHz (Typ.) at 10V
■ FULLY STATIC OPERATION
■ SYNCHRONOUS PARALLEL OR SERIAL
OPERATION
■ THREE-STA TE OUTPU TS
■ STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
■ QUIESCENT CURRENT SPECIF. UP TO 20V
■
5V , 10V AND 15V PARAMETRIC RATINGS
■ INPUT LEAKAGE CURRENT
= 100nA (MAX) AT VDD = 18V TA = 25°C
I
I
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B "STANDARD S PECIFICATIONS
FOR DESCRIPTI ON OF B SERI ES CMOS
DEVICES"
DESCRIPTION
HCF40104B is a monolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP packages.
HCF40104B is a universal shift register featuring
parallel inputs, parallel outputs, SHIFT RIGHT and
SHIFT LEFT serial inputs, and a high-imped ance
third output state allowing the device to be used in
bus-organized s ystem s. In t he parallel-load mode
(SO and S1 are high), data is loaded into the
DIP
ORDER CODES
PACKAGE TUBE T & R
DIP HCF40104BEY
associated flip-flop and appears at the output after
the positive transition of the CLO CK inpu t. Duri ng
loading, serial data flow is inhibited. Shift-right and
shift-left are synchronously accomplished on the
positive clock edge with seria l data entered at the
SHIFT RIGHT and SHIFT LEFT serial inputs,
respectively. Clearing the register is accomplished
by setting both mode controls low and clocking the
register. When the output enab le input is low, all
outputs assume the high impedance state.
PIN CONNECTION
1/10September 2002
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HCF40104B
IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1
3, 4, 5, 6 D0 to D3 Inputs
15, 14, 13,
12
2 Shift Right IN Shift Righ Input
7 Shift Left IN Shift Left Input
11 CLOCK Clock Input
9, 10 S0, S1 Input (High)
8
16
FUNCTIONAL DIAGRAM
OUTPUT
ENABLE
Q0 to Q3 Outputs
V
SS
V
DD
Output Enable
Negative Supply Voltage
Positive Supply Voltage
TRUTH TABLE
CLOCK
XXXL
X : Don’t Care
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MODE SELECT
S0 S1
L L H RESET
HLH
LHH
H H H PARALLEL LOAD
OUTPUT ENABLE ACTION
SHIFT RIGHT (Q0
toward Q3)
SHIFT LEFT (Q3
toward Q0)
Operations occur as
shown above, but out-
puts assume high
impedance
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LOGIC DIAGRAM
HCF40104B
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HCF40104B
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values ar e referred to V
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
T
Supply Voltage
DD
DC Input Voltage -0.5 to VDD + 0.5
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I
DC Input Current
I
Power Dissipation per Package 200 mW
D
-0.5 to +22 V
10 mA
±
Power Dissipation per Output Transistor 100 mW
Operating Temperature
op
Storage Temperature
stg
pin voltage.
SS
Supply Voltage
DD
Input Voltage 0 to V
I
Operating Temperature
op
-55 to +125 °C
-65 to +150 °C
3 to 20 V
DD
-55 to 125 °C
V
V
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DC SPECIFICATIONS
Test Condition Value
T
Symbol Parameter
I
Quiescent Current 0/5 5 0.04 5 150 150
L
V
(V)
V
I
(V)
|I
|
O
O
(µA)
V
DD
(V)
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
0/10 10 0.04 10 300 300
0/15 15 0.04 20 600 600
0/20 20 0.08 100 3000 3000
V
High Level Output
OH
Voltage
0/5 <1 5 4.95 4.95 4.95
0/15 <1 15 14.95 14.95 14.95
Low Level Output
V
OL
Voltage
5/0 <1 5 0.05 0.05 0.05
15/0 <1 15 0.05 0.05 0.05
High Level Input
V
IH
Voltage
0.5/4.5 <1 5 3.5 3.5 3.5
1.5/13.5 <1 15 11 11 11
V
IL
Low Level Input
Voltage
4.5/0.5 <1 5 1.5 1.5 1.5
13.5/1.5 <1 15 4 4 4
I
OH
Output Drive
Current
0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1
0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36
0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9
0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4
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OL
Output Sink
Current
0/5 0.4 <1 5 0.44 1 0.36 0.36
0/15 1.5 <1 15 3.0 6.8 2.4 2.4
Input Leakage
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I
Current
C
Input Capacitance
I
The Noi se Margin for bot h " 1" and "0" level is: 1V min. with VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
0/18 Any Input 18
Any Input 5 7.5 pF
-5
10
±
-40 to 85°C -55 to 125°C
0.1
±
1
±
HCF40104B
Unit
A
µ
V0/10 <1 10 9.95 9.95 9.95
V10/0 <1 10 0.05 0.05 0.05
V1/9 <1 10 7 7 7
V9/1 <1 10 3 3 3
mA
mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9
1
±
A
µ
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HCF40104B
DYNAMIC ELECTRICAL CHARACTERISTICS (T
Symbol Parameter
t
PHL tPLH
t
PZH,tPZL,
t
t
t
THL tTLH
t
setup
Propagation Delay Time
Clock to Q
3-State Outputs
High Impedance
PLZ
PHZ
Transition Time 5 100 200
Setup Time D0, D3, SR,
SL to Clock
SO, S1 to Clock 5 200 400
t
Hold Time D0, D3, SR, SL
hold
to Clock
SO, S1 to Clock 5 -170 0
Clock Pulse Width 5 90 180
t
W
Clock Input Frequency 5 3 6
f
CL
Clock Input Rise or Fall
, t
t
r
f
Time
(V)
V
DD
5 220 440
15 70 140
580160
15 25 50
54590
15 20 40
15 40 80
580100
15 20 50
15 65 130
5-650
15 -15 0
15 -55 0
15 25 50
15 8 15
51000
15 100
= 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
amb
Test Condition Value (*) Unit
Min. Typ. Max.
ns10 100 200
ns10 35 70
ns10 25 50
ns10 50 100
ns10 35 70
ns10 110 220
ns10 -25 0
ns10 -95 0
ns10 40 180
MHz10 6 12
µ
s10 100
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TEST CIRCUIT
t
, t
PLH
PHL
, t
t
PZL
PLZ
t
, t
PZH
PHZ
HCF40104B
TEST SWITCH
Open
V
DD
V
SS
CL = 50pF or equivalent (includes jig and probe capacitanc e)
R
= 200K
Ω
L
R
= Z
of pulse generator (typically 50Ω)
T
OUT
WAVEFORM 1 : CK TO Q PROPAGATION DELAY TIMES (f= 1M Hz; 5 0% duty cycl e )
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HCF40104B
WAVEFORM 2 : SI, SO SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 3 : OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% d uty cycle)
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HCF40104B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 0.050
P001C
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HCF40104B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility f or the
consequences of use of such informatio n nor for any infringement of paten ts or o ther rig hts of t hird part ies which ma y result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previousl y suppl ied. STM icroel ectronics produc ts are not auth orized for use as c ritica l compone nts in l ife s upport dev ices or
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