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HCF4006B
18-STAGE STATIC SHIFT REGISTER
■ PERMANENT REGISTE R ST ORAG E WI TH
CLOCK LINE "HIGH" OR "LOW" ... NO
INFORMATION RECIRCULAT IO N
REQUIRED
■ FULLY STATIC OPERATION
■ SHIFTING RA TE S UP TO
12MHzat 10V (Typ.)
■ STANDARDIZED SYMMETRICAL OUTPUT
CHARACTERISTICS
■ QUIESCENT CURRENT SPECIFIED UP TO
20V
■ 5V, 10V AND 15V PARAMETRIC RAT INGS
■ INPUT LEAKAGE CURRENT
I
= 100nA (MAX) AT VDD = 18V TA = 25°C
I
■ 100% TESTED FOR QUIESCENT CURRENT
■ MEETS ALL REQUIREMENTS OF JEDEC
JESD13B " STANDARD SPECIFICATIONS
FOR DESCRIPTI ON OF B SERI ES CMOS
DEVICES"
DESCRIPTION
The HCF4006B is a m onolithic integrated circuit
fabricated in Metal Oxide Semiconductor
technology available in DIP and SOP packages.
The HCF4006B is comprised of 4 separate "shift
register" sections; two sections of four stages and
two sections of five stages with an output tap at
the fourth stage. Each section has an independent
"single rail" data path. A common clock signal is
DIP SOP
ORDER CODES
PACKAGE TUBE T & R
DIP HCF4006BEY
SOP HCF4006BM1 HCF4006M013TR
used for all stages. Data is shifted to the next
stage on negative going transitions of the clock.
Through appropriate connections of inputs and
outputs, multiple register sections of 4, 5, 8 and 9
stages or single register sections of 10, 12, 13, 14,
16, 17 and 18 can be implemented using one
HCF4006B package. Longer shift register
sections can be assembled by using more than
one HCF4006B. To facilitate cascading stages
when clock rise and fall times are slow, an optional
output (D1+4’) that is delayed one-half
clock-cycle, is provided (see truth table for output
from pin 2)
PIN CONNECTION
1/8September 2001
Page 2
HCF4006B
INPUT EQUIVALENT CIRCUIT
FUNCTIONAL DIAGRAM
PIN DESCRIPTION
PIN No SYMBOL NAME AND FUNCTION
1, 4, 5, 6 D1 to D4 Data inputs
2 D1+4’ Delayed Optional Output
13, 11, 10, 8 Dn + 4
12, 9 Dn + 5
3 CLOCK Clock Input
7
14
V
SS
V
DD
4 stage shift register
Output
5 stage shift register
Output
Negative Supply Voltage
Positive Supply Voltage
TRUTH TABLE FOR SHIFT REGISTER STAGE
D CLOCK* D + 1
LL
HH
X NO CHANGE
TRUTH TABLE FOR OUTPUT FROM PIN 2
D1 + 4 CLOCK* D1 + 4’
LOGIC DIAGRAM
LL
HH
X NO CHANGE
* : Level Ch ange
X : Don’t Care
2/8
Page 3
HCF4006B
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
V
P
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referr ed to V
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Value Unit
V
V
T
Supply Voltage
DD
DC Input Voltage -0.5 to VDD + 0.5
I
I
DC Input Current
I
Power Dissipation per Package 200 mW
D
-0.5 to +22 V
± 10 mA
Power Dissipation per Output Transistor 100 mW
Operating Temperature
op
Storage Temperature
stg
pin voltage.
SS
Supply Voltage
DD
Input Voltage 0 to V
I
Operating Temperature
op
-55 to +125 °C
-65 to +150 °C
3 to 20 V
DD
-55 to 125 °C
V
V
3/8
Page 4
HCF4006B
DC SPECIFICATIONS
Test Condition Value
T
Symbol Parameter
I
Quiescent Current 0/5 5 0.04 5 150 150
L
V
(V)
V
I
(V)
|I
|
O
O
(µA)
V
DD
(V)
= 25°C
A
Min. Typ. Max. Min. Max. Min. Max.
0/10 10 0.04 10 300 300
0/15 15 0.04 20 600 600
0/20 20 0.08 100 3000 3000
V
High Level Output
OH
Voltage
0/5 <1 5 4.95 4.95 4.95
0/15 <1 15 14.95 14.95 14.95
Low Level Output
V
OL
Voltage
5/0 <1 5 0.05 0.05 0.05
15/0 <1 15 0.05 0.05 0.05
High Level Input
V
IH
Voltage
0.5/4.5 <1 5 3.5 3.5 3.5
1.5/13.5 <1 15 11 11 11
V
IL
Low Level Input
Voltage
4.5/0.5 <1 5 1.5 1.5 1.5
13.5/1.5 <1 15 4 4 4
I
OH
Output Drive
Current
0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1
0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36
0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9
0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4
I
OL
Output Sink
Current
0/5 0.4 <1 5 0.44 1 0.36 0.36
0/15 1.5 <1 15 3.0 6.8 2.4 2.4
Input Leakage
I
I
Current
C
Input Capacitance
I
The Noi se Margin fo r both "1" and "0 " le vel is: 1V min. wi t h VDD=5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
0/18 Any Input 18
Any Input 5 7.5 pF
±10
-5
-40 to 85°C -55 to 125°C
±0.1 ± 1 ±1 µA
Unit
µA
V0/10 <1 10 9.95 9.95 9.95
V10/0 <1 10 0.05 0.05 0.05
V1/9 <1 10 7 7 7
V9/1 <1 10 3 3 3
mA
mA0/10 0.5 <1 10 1.1 2.6 0.9 0.9
4/8
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HCF4006B
DYNAMIC ELECTRICAL CHARACTERISTICS (T
Symbol Parameter
t
PLH tPHL
t
TLH tTHL
t
t
setup
f
MAX
(*) Typical temperature coeffic i ent for all VDD value is 0.3 %/°C.
Propagation Delay Time 5 200
Output Transition Time 5 100
Clock Pulse Width 5 100
t
W
Clock Input Rise or Fall
r, tf
Time*
Data Setup Time 5 50
Maximum Clock Input
Frequency
(V)
V
DD
15 80
15 40
15 30
515
15 15
15 20
55
15 16
= 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)
amb
Test Condition Value (*) Unit
Min. Typ. Max.
ns10 100
ns10 50
ns10 45
µs10 15
ns10 25
MHz10 12
TEST CIRCUIT
CL = 50pF or equivalent (incl udes jig and p robe capacit ance)
R
= 200KΩ
L
= Z
R
of pulse generator (typically 50Ω)
T
OUT
5/8
Page 6
HCF4006B
Plastic DIP-14 MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 1.39 1.65 0.055 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787
E 8.5 0.335
e 2.54 0.100
e3 15.24 0.600
F 7.1 0.280
I 5.1 0.201
L 3.3 0.130
Z 1.27 2.54 0.050 0.100
6/8
P001A
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SO-14 MECHANICAL DATA
HCF4006B
DIM.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45° (typ.)
D 8.55 8.75 0.336 0.344
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 7.62 0.300
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.68 0.026
S8° (max.)
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
PO13G
7/8
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HCF4006B
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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by imp lica tion or otherwise under a ny patent or patent rig hts of STMicroelectronics. Spec ificat ions
mentioned in this publication ar e subject to change without notice. This publication supersedes and replaces all information
previously supplied. S TMicroelectronics products are not authorized for use as critica l components in life suppo rt devices or
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