94)
/Subject
(ADSL
Analog
Front
End
Chip)
/Autho
r ()
/Keywords
(Harris
Semiconductor,
Telecom,
SLICs,
SLACs
, Telephone,
Telephony,
WLL,
Wireless
Local
Loop,
PBX,
Private
Branch
Exchan
ge,
NT1+,
CO,
Cen-
Semiconductor
NO RECOMMENDED REPLACEMENT
February 1999
Call Central Applications 1-800-442-7747
or email: centapp@harris.com
Features
• 14-Bit 5 MSPS DAC
• Programmable Gain Stages
• Anti-Aliasing and Reconstruction Filters
Applications
• FDM DMT ADSL
• CAP ADSL
• EC DMT ADSL
• Communications Receiver
Pinout
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
OBSOLETE PRODUCT
Description
The HC6094 performs the Analog processing for the ADSL
chip set. The transmit chain has a 14 Bit DAC, a third-order
Chebyshev reconstruction filter and a programmable attenuator (-12 to 0dB) capable of driving a 220Ω differential load.
The receiver chain has a high impedance input stage, programmable gain stage (0 to 24dB), additional programmable
gain (-9 to 18dB) and a third-order Chebyshev anti-aliasing
filter for driving an off-chip A/D.
Laser trimmable thin-film resistors are used to set the filter
cutoff frequency and DAC linearity. The transmit and receive
signal chains are specified at 65dB MTPR.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(Lead Tips Only)
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications V
=5V,VSS= -5V, RLOpen, Over Temperature Range; Unless Otherwise Specified. Designed for ±5%
DD
Power Supply.
TEST
PARAMETERSYMBOL
CONDITIONSMINTYPMAXUNITS
OVERALL
Supply CurrentsI
I
I
VDD (Note 2)-66-mA
DD
VSS (Note 3)--79-mA
SS
CC
V
CC
-0- µA
Power DissipationPDQuiescent, No Load-725-mW
DIGITAL INTERFACE
Input Voltage ThresholdsV
Input CurrentsI
IL
V
IH
VIN = 0V-10.0010.0µA
IL
I
VIN = V
IH
DD
--0.8V
2.7--V
-10.0010.0µA
Serial Clock PeriodT10.1-5.0µs
CS Active Before Shift EdgeT2T1/2 -10--ns
Write Data Valid After Shift
T3--10ns
Edge
CS Inactive After Latch EdgeT4T1 - 10-T1 +10ns
Write Data Hold After Latch
T5T1/2 -5-T1/2 +5ns
Edge
DAC Setup Timet
DAC Hold Timet
S
H
--100ns
--100ns
14-BIT DAC
Resolution/Monotonicity14--Bits
Integral LinearityI
Differential LinearityD
Measured at TX Outputs-±1.5-LSB
LE
LE
-±0.9-LSB
Max Sample Rate4.416--Ms/s
TRANSMITTER OUTPUT
Output DriveTXODSink or Source3055-mA
Differential Output SwingTXOSRL= 220Ω11.712.0312.3V
PP
Differential BalanceTXDBGain Match Between Outputs-0.5-%
Transmit Output OffsetTXOFFMax Gain Single Ended (Note 4)-20025200mV
Multi-Tone Power RatioTXMTPRRL= 220Ω-65- dB
Power Supply RejectionPSRRInput Referred - V
Input Referred - V
DD
SS
4065-dB
5584-dB
3
Page 4
HC6094
Electrical Specifications V
=5V,VSS= -5V, RLOpen, Over Temperature Range; Unless Otherwise Specified. Designed for ±5%
DD
Power Supply. (Continued)
TEST
PARAMETERSYMBOL
CONDITIONSMINTYPMAXUNITS
TRANSMITTER GAIN STAGE
Gain ErrorTXPGRL= 220Ω, 0dB Setting-0.22+0.020.22dB
RL= 220Ω, Each Step Relative to 0dB-0.150.020.15dB
TRANSMITTER FREQUENCY RESPONSE
Gain Ripple Peak to PeakGPAcross 1.104MHz Bandwidth-0.20.6dB
Stopband AttenuationGSAt 2.65MHz1417-dB
Floor AttenuationGMAt 9.94MHz-58-dB
RECEIVER INPUT (PGA1 AND PGA2)
Input SwingRXISDifferential--12V
PP
Input ImpedanceRXRINPGA11.0-MΩ
PGA21.012-kΩ
Common Mode RejectionRXCMRR 1.1MHz-90-dB
Common Mode RangeRXCMIR-0.25-0.25V
Continuous Input VoltageVSS-0.5VDD +0.5V
RECEIVER OUTPUT (INCLUDING PGA1 OUT)
Differential Output SwingRXOSRX
Differential BalanceRXDBEnd to End (RXIN to RX
(RL = 2000Ω)12.015.8-V
OUT
PGA1
(RL = 2000Ω)12.016.0-V
OUT
)-0.5-%
OUT
PP
PP
PGA1 Output OffsetRXOFFMax Gain Single Ended (Note 4)-20040200mV
PGA2 Output OffsetRXOFFMax Gain Single Ended (Note 4)-20030200mV
Multi-Tone Power RatioRXMTPR RL = 2000Ω-65- dB
Power Supply RejectionPSRRInput Referred - V
Input Referred - V
DD
SS
4569-dB
5584-dB
RECEIVER GAIN STAGE
Absolute Gain ErrorRXPGAny Step (RXIN to RX
)-0.30.010.3dB
OUT
RECEIVER FREQUENCY RESPONSE
Gain Ripple Peak to PeakGPAcross 1.104MHz Bandwidth-0.40.6dB
Stopband AttenuationGSAt 2.65MHz1419.4-dB
Floor AttenuationGMAt 9.94MHz-53-dB
TRANSMITTER AND RECEIVER FILTER CUTOFF FREQUENCY
TX Filter F
RX Filter F
C
C
TX
RX
-0.15dB point1.1041.181.25MHz
FC
-0.15dB point1.1041.1251.16MHz
FC
NOTES:
2. VDD = 5V typical, supply range ±5%.
3. VSS = -5V typical, supply range ±5%.
4. Single ended operation for reference only. Probed to these limits, but not packaged tested.
4
Page 5
HC6094
Definitions
1. Supply currents/power dissipation measured in a quiescent (static) state with RL open.
2. Logic input levels and timing are verified by using them as conditions for testing DAC and filter.
3. Digital input currents are measured at 0V and V
4. DAC resolution and monotonicity guaranteed by ILE and DLE tests.
5. DAC ILE is relative to best fit straight line.
6. Output drive current is the output current at 0V for each output when they are driven to ± Full Scale.
7. Output offset measured with V
= 0V differential for the RX, and the DAC at mid scale for the TX.
IN
8. PSRR is the change in differential input voltage vs. change in supply voltage at DC.
Gain is calculated as 20*Log((TXout
9. T
X
input swing is verified by using this as condition for gain testing.
10. R
X
Input Impedance is calculated as ∆VIN/∆IIN where VIN is the maximum input voltages, with the PGA set to 0dB.
11. R
X
12. RXCMRR is calculated as 20*Log(V
DACFS
OUT/VIN
set to maximum.
.
CC
- TXout
DACZS
)/12V) at DC.
)-PGA Gain. VINis set to 250mV
(CMIR) at 1.1MHz, and PGA gain is
PEAK
13. R
Gain is calculated as 20*Log(dV
X
/dVIN), where VINis set to give a nominal ± Output Swing, or the maximum input
OUT
swing, whichever is smaller. It is tested DC.
14. Filter Gain/Attenuation is relative to low frequency passband gain. T
R
tested by driving PGA2. Wafer probe will use special test points to bypass the DAC for laser trimming.
X
tested by driving the DAC (with sinX/X correction),
X
15. MTPR -(Multi-Tone Power Ratio). A DMT waveform is generated which has a specific crest factoror peak to average ratio
(PAR) with specific carriers missing. The waveformis then passed through the T
or RXchain. The total integrated power
X
of the notch at the location of the missing carriers is measured with respect to the adjacent carriers. Notch depth is measured for severalDMT waveforms with different PARs. The notch depths for each DMT waveform are averaged to give an
MTPR number.
5
Page 6
Shift Register Format
HC6094
Each write operation to a control register involves 16 bits of
data. The CS- signal must be enabled low during any serial
write operation. The data on SDI shall be clocked in during
CS-
SCLK
SDI
FIGURE 1. SERIAL CONTROL
Logic Timing Definitions
CS
SCLK
the rising edge of SCLK. A3-A0 supply the address of the
control register, and D7-D0 supply the data.
0000 A0A1A2A3D0D1D2D3D4D5D6D7
SCLK
SDI
DAC DATA
CLK
t
2
t
t
3
5
t
1
FIGURE 2. SERIAL INTERFACE
tSt
H
FIGURE 3. DAC INTERFACE
t
4
6
Page 7
HC6094
Shift Registers Format
REGISTERA0A1A2A3D0D1D2D3D4D5D6D7
RX Gain10XXPGA1 GainPGA2 Gain
TX Gain00XXPGA0 Gain