Datasheet HC55184, HC55183, HC55182, HC55181, HC55180 Datasheet (Intersil Corporation)

Page 1

HC55180, HC55181, HC55182, HC55183, HC55184

Data Sheet October 1998 File Number 4519.4

Extended Reach Ringing SLIC Family

The RSLIC18 family of ringing subscriber line interface circuits (RSLIC) supports analog Plain Old

TelephoneService (POTS) in short and medium loop length, wireless and wireline applications. Ideally suited for remote subscriber units, this family of products offers ﬂexibility to designers with high ringing voltage and low power consumption system requirements.

The RSLIC18 family operates to 100V which translates directly to the amount of ringing voltage supplied to the end subscriber. With the high operating voltage, subscriber loop lengths can be extended to 500Ω (i.e., 5,000 feet) and beyond.

Other key features across the product family include: low power consumption, ringing using sinusoidal or trapezoidal waveforms, robust auto-detection mechanisms for when subscribers go on or off hook, and minimal external discrete application components. Integrated test access features are also offered on selected products to support loopback testing as well as line measurement tests.

There are ﬁve product offerings in the RSLIC18 family: HC55180, HC55181, HC55182, HC55183 and HC55184. The architecture for this family is based on a voltage feed ampliﬁer design using low ﬁxed loop gains to achieve high analog performance with low susceptibility to system induced noise.

Block Diagram

POL CDC VBHVBL

RINGING

PORT

VRS

ILIM

CONTROL

BATTERY

SWITCH

Features

• Battery Operation to 100V

• Low Standby Power Consumption of 50mW

• Peak Ringing Amplitude 95V, 5 REN

• Sinusoidal or Trapezoidal Ringing Capability

• Integrated CODEC Ringing Interface

• Integrated MTU DC Characteristics

• Low External Component Count

• Pulse Metering and On Hook Transmission

• Tip Open Ground Start Operation

• Thermal Shutdown with Alarm Indicator

• 28 Lead Surface Mount Packaging

• Dielectric Isolated (DI) High Voltage Design

• HC55180

- Silent Polarity Reversal

- 53dB Longitudinal Balance

- Loopback Test Capability

• HC55181

- Integrated Battery Switch

- Silent Polarity Reversal

- 58/53dB Longitudinal Balance

- Loopback and Test Access Capability

• HC55182

- Integrated Battery Switch

- 58/53dB Longitudinal Balance

- Loopback and Test Access Capability

• HC55183

- Integrated Battery Switch

- 45dB Longitudinal Balance

• HC55184

- Integrated Battery Switch

- Silent Polarity Reversal

- 45dB Longitudinal Balance

Applications

TIP

RING

SW+

SW-

2-WIRE

PORT

TEST

ACCESS

TRANSMIT

DETECTOR

RTD RD

SENSING

LOGIC

DET ALM

• Wireless Local Loop (WLL)

• Digital Added Main Line (DAML)/Pairgain

• Integrated Services Digital Network (ISDN)

• Small Ofﬁce Home Ofﬁce (SOHO) PBX

4-WIRE

PORT

VRX VTX

-IN VFB

• Cable/Computer Telephony

CONTROL

LOGIC

BSEL

F2 F1 F0

SWC

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Related Literature

• AN9814, User’s Guide for Development Board

• AN9824, Modeling of the AC Loop

• AN TBD, Interfacing to DSP CODECs

RSLIC18™ is a trademark of Intersil Corporation.

Page 2

HC55180, HC55181, HC55182, HC55183, HC55184

Ordering Information (PLCC Package Only)

LOOP

BATSWPOL

PART NUMBER 100V 85V

REV

FULL TEST

BACK ONLY LB = 53dB LB = 58dB

TEMP.

RANGEoC PACKAGE

PACKAGE

NO.

HC55180CIM HC55180DIM HC55181AIM HC55181BIM HC55181CIM HC55181DIM HC55182AIM HC55182BIM HC55182CIM HC55182DIM HC55183ECM 75V HC55184ECM 75V HC5518XEVAL1 Evaluation board platform, including CODEC.

••••

•• ••

•••• •

••• • •

•••• •

••• • •

•• • •

•

••

Device Operating Modes

-40 to 85 28 Ld PLCC N28.45

-40 to 85 28 Ld PLCC N28.45 45dB 0 to 70 28 Ld PLCC N28.45 45dB 0 to 70 28 Ld PLCC N28.45

OPERATING

MODE F2 F1 F0 E0 = 1 E0 = 0 DESCRIPTION HC55180 HC55181 HC55182 HC55183 HC55184

Low Power Standby

Forward Active 0 0 1 SHD GKD Forward battery loop feed. Unused 0 1 0 n/a n/a This is a reserved internal

Reverse Active 0 1 1 SHD GKD Reverse battery loop feed. Ringing 1 0 0 RTD RTD Balanced ringing mode

Forward Loop Back

Tip Open 1 1 0 SHD GKD Tip amplifier disabled and

Power Denial 1 1 1 n/a n/a Device shutdown.

0 0 0 SHD GKD MTU compliant standby

mode with active loop detector.

test mode.

supporting both sinusoidal, trapezoidal and ringing waveforms with DC offset.

1 0 1 SHD GKD Internal device test mode.

ring amplifier enabled. Intended for PBX type applications.

•••••

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•••••

•••

•••••

Page 3

Pinouts

HC55180, HC55181, HC55182, HC55183, HC55184

HC55180

(PLCC)

TOP VIEW

RING

POL

ILIM

RTD

CDC

VCC

23 22

-IN VFB

VTX

VRX

VRS

NC NC NC

F2 F1 F0 E0

TIP

VBL

VBH

ALM

BGND

AGND

5 6 7

9 10 11

DET

SW+

SW-

SWC

F2 F1 F0 E0

NC NC NC

F2 F1 F0 E0

HC55181

(PLCC)

TOP VIEW

RING

POL

ILIM

RTD

CDC

VCC

23 22

-IN VFB

VTX

VRX

VRS

SW+

SW-

SWC

F2 F1 F0 E0

5 6 7

9 10 11

TIP

VBL

VBH

ALM

BGND

AGND

BSEL

5 6 7

9 10 11

DET

HC55183

(PLCC)

TOP VIEW

RING

ILIM

RTD

CDC

VCC

23 22

-IN VFB

VTX

VRX

VRS

NC NC NC

F2 F1 F0 E0

5 6 7

9 10 11

DET

BGND

AGND

TIP

BSEL

VBL

VBH

5 6 7

9 10 11

DET

ALM

VBH

DET

ALM

HC55182

(PLCC)

TOP VIEW

VBL

ALM

HC55184

(PLCC)

TOP VIEW

BGND

VBL

AGND

BGND

AGND

TIP

BSEL

TIP

BSEL

RING

POL

ILIM

25 24 23 22 21 20 19

VRS

ILIM

25 24 23 22 21 20 19

VRS

RTD CDC VCC

-IN VFB

VTX VRX

RTD CDC VCC

-IN VFB

VTX VRX

Page 4

HC55180, HC55181, HC55182, HC55183, HC55184

Absolute Maximum Ratings T

Maximum Supply Voltages

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V

VCC - V VCC - V

Uncommitted Switch Voltage . . . . . . . . . . . . . . . . . . . . . . . -110V

ESD (Human Body Model). . . . . . . . . . . . . . . . . . . . . . . . . . . . 500V

(180, 181, 182) . . . . . . . . . . . . . . . . . . . . . . . . . 110V

BAT

(183, 184) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85V

BAT

=25oC Thermal Information

Thermal Resistance (Typical, Note 1) θJA(oC/W)

PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

(PLCC - Lead Tips Only)

Operating Conditions

Temperature Range

Industrial (I sufﬁx). . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

Commercial (C sufﬁx). . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC

Positive Power Supply (VCC). . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Negative Power Supply (VBH, VBL) (180, 181, 182) . -16V to -100V

Negative Power Supply (VBH, VBL) (183, 184) . . . . . . -24V to -75V

Uncommitted Switch (loop back or relay driver). . . . . . +5V to -100V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Unless Otherwise Specified, T

VBH= -100V, -85V or -75V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600Ω 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0Ω. These parameters apply generically to each product offering.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

RINGING PARAMETERS (Note 2)

VRS Input Impedance (Note 3) 480 - - kΩ Differential Ringing Gain VRS to 2-wire, R 4-Wire to 2-Wire Ringing Off Isolation Active mode, referenced to VRS input. - 60 - dB 2-Wire to 4-Wire Transmit Isolation Ringing mode referenced to the differential ringing

AC TRANSMISSION PARAMETERS (Notes 5, 6) Receive Input Impedance (Note 3) 160 - - kΩ Transmit Output Impedance (Note 3) --1Ω 4-Wire Port Overload Level THD = 1% 3.1 3.5 - V 2-Wire Port Overload Level THD = 1% 3.1 3.5 - V 2-Wire Return Loss 300Hz ≤ f < 1kHz 30 45 - dB

Longitudinal Current Capability (Per Wire) (Note 3) Test for False Detect 20 - - mA

4-Wire to 2-Wire Insertion Loss -0.20 0.0 +0.30 dB 2-Wire to 4-Wire Insertion Loss -6.22 -6.02 -5.82 dB 4-Wire to 4-Wire Insertion Loss -6.22 -6.02 -5.82 dB Idle Channel Noise 2-Wire C-Message - 16 19 dBrnC

Idle Channel Noise 4-Wire C-Message - 10 13 dBrnC

DC PARAMETERS (Note 6) Loop Current Limit Programming Range (Note 5) Max Low Battery = -52V 15 - 45 mA Loop Current During Low Power Standby Forward polarity only. 18 - 26 mA

= 0oC to 70oC for the HC55183, 184 only, all others -40oC to 85oC, VBL = -24V,

amplitude.

1kHz ≤ f ≤ 3.4kHz 35 45 - dB

Test for False Detect, Low Power Standby 10 - - mA

Psophometric - -73.5 -71 dBmp

Psophometric - -79.5 -77 dBmp

Die Characteristics

Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI

= ∞ (Note 4) 78 80 82 V/V

LOAD

-60- dB

BAT

PK PK

RMS RMS

Page 5

HC55180, HC55181, HC55182, HC55183, HC55184

Electrical Specifications Unless Otherwise Specified, T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

LOOP DETECTORS AND SUPERVISORY FUNCTIONS

Switch Hook Programming Range 5 - 15 mA Switch Hook Programming Accuracy Assumes 1% external programming resistor - 2 10 % Dial Pulse Distortion --1% Ring Trip Comparator Threshold 2.3 2.6 2.9 V Ring Trip Programming Current Accuracy - - 10 % Ground Key Threshold 10 12 13.5 mA Thermal Alarm Output IC junction temperature - 175 -

LOGIC INPUTS (F0, F1, F2, E0, SWC)

Input Low Voltage - - 0.8 V Input High Voltage 2.0 - - V Input Low Current VIL = 0.4V -20 - - µA Input High Current VIH = 2.4V - - 5 µA

LOGIC OUTPUTS (DET, ALM)

Output Low Voltage IOL = 5mA - - 0.4 V Output High Voltage IOH = 100 µA 2.4 - - V

POWER SUPPLY REJECTION RATIO

VCC to 2-Wire f = 300Hz - 40 - dB

VCC to 4-Wire f = 300Hz - 45 - dB

VBL to 2-Wire 300Hz ≤ f ≤ 3.4kHz - 30 - dB VBL to 4-Wire 300Hz ≤ f ≤ 3.4kHz - 35 - dB VBH to 2-Wire 300Hz ≤ f ≤ 3.4kHz - 33 - dB VBH to 4-Wire 300Hz ≤ f ≤ 1kHz - 40 - dB

= 0oC to 70oC for the HC55183, 184 only, all others -40oC to 85oC, VBL = -24V,

f = 1kHz - 35 - dB f = 3.4kHz - 28 - dB

f = 1kHz - 43 - dB f = 3.4kHz - 33 - dB

1kHz < f ≤ 3.4kHz - 45 - dB

NOTES:

2. These parameters are specified at high battery operation. For the HC55180 the external supply is set to high battery voltage, for the HC55181, HC55182, HC55183 and HC55184, BSEL = 1.

3. These parameters are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics.

4. Differential Ringing Gain is measured with VRS = 0.795 V for -75V devices.

5. These parameters are specified at low battery operation. For the HC55180, the external supply is set to low battery voltage, for the HC55181, HC55182, HC55183 and HC55184, BSEL = 0.

6. Forward Active and Reverse Active performance is guaranteed for the HC55180, HC55181 and HC55184 devices only. The HC55182 and HC55183 are specified for Forward Active operation only.

for -100V devices, VRS = 0.663 V

RMS

for -85V devices and VRS = 0.575 V

RMS

Page 6

Electrical Speciﬁcations Unless Otherwise Speciﬁed, T

loop current limit = 25mA. All AC Parameters are speciﬁed at 600W 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0W.

HC55180 (Note 7) HC55181, HC55182 HC55183, HC55184

PARAMETER

RINGING PARAMETERS (Note 2)

Ringing Voltage Open Circuit (Note 8)

Ringing Voltage Load = 1.3K (Notes 8, 10)

Tip Centering Voltage VB = -85V, RL = ∞ - 2.5 - VBH = -85V, RL = ∞ - - 2.5 VBH = -75V, RL = ∞ -- 3V

Ring Centering Voltage VB = -85V, RL = ∞ - 2.5 - VBH = -85V, RL = ∞ - - 2.5 VBH = -75V, RL = ∞ -- 3V

AC TRANSMISSION PARAMETERS (Notes 5, 6) 2-Wire Longitudinal Balance

(Notes 12, 13) 4-Wire Longitudinal Balance (Note 11) - - - Grade A, B - 67 - Grade E - 58 - dB

2-Wire to 4-Wire Level Linearity 4-Wire to 2-Wire Level Linearity Referenced to -10dBm

DC PARAMETERS

Loop Current Accuracy (Notes 5, 6)

Open Circuit Voltage (|Tip - Ring|, Note 6)

Low Power Standby Open Circuit Voltage (Tip - Ring, Note 2)

TEST ACCESS FUNCTIONS

Switch On Voltage (Note 14) - - - IOL = 45mA - 0.30 0.60 (Note 14) - - - V Loopback Max Battery - - 52 - - 52 (Note 15) - - 52 V

THD ≤ 0.5% VB = -85V

THD ≤ 0.5% VB = -100V

THD ≤ 2.5% VB = -85V

THD ≤ 2.0% VB = -100V

VB = -100V, RL = ∞ - 2.0 - VBH = -100V, RL = ∞ - - 2.0 (Note 9) - - - V

(Note 11) - - - Grade A, B 58 62 - Grade E 45 53 - dB Grade C, D - 59 - Grade C, D 53 59 - (Note 11) - - - dB

Grade C, D - 64 - Grade C, D - 64 - (Note 11) - - - dB +3 to -40dBm, 1kHz - 0.025 - +3 to -40dBm, 1kHz - 0.025 - +3 to -40dBm, 1kHz - 0.025 - dB

-40 to -50dBm, 1kHz - 0.050 - -40 to -50dBm, 1kHz - 0.050 - -40 to -50dBm, 1kHz - 0.050 - dB

-50 to -55dBm, 1kHz - 0.100 - -50 to -55dBm, 1kHz - 0.100 - -50 to -55dBm, 1kHz - 0.100 - dB

IL = 25mA - 7 - IL = 25mA - - 7 IL = 25mA - - 10 %

VB = -16V - 7.5 - VBL = -16V 6.5 7.5 9.5 VBL = -16V - 7.5 - V VB = -24V 14 15.5 17 VBL = -24V 14 15.5 17 VBL = -24V 14 15.5 17 V VB = -85V - 50 - BSEL = 1, VBH = -85V - 50 - BSEL = 1, VBH = -75V - 50 - V VB = -100V - 50 - BSEL = 1, VBH= -100V - 50 - (Note 9) - - - V VB = -48V 43 45 47 VBH = -48V 43 45 47 VBH = -48V 43 45 47 V VB = -85V 46 49 52 VBH = -85V 46 49 52 VBH = -75V 46 49 52 V VB = -100V 46 49 52 VBH = -100V 46 49 52 (Note 9) - - - V

= 0oC to 70oC for the HC55183, 184 only, all others -40oC to 85oC, VBL = -24V, VCC = +5V, AGND = BGND = 0V,

-80-THD≤ 0.5% VBH = -85V

-95-THD≤ 0.5% VBH = -100V

-80-THD≤ 2.5% VBH = -85V

-95-THD≤ 2.0% VBH = -100V

80 - - THD ≤ 0.5%

VBH = -75V

95 - - (Note 9) - - - V

80 - - THD ≤ 3.0%

VBH = -75V

95 - - (Note 9) - - - V

70 - - V

UNITSTEST CONDITIONS MIN TYP MAX TEST CONDITIONS MIN TYP MAX TEST CONDITIONS MIN TYP MAX

PEAK

HC55180, HC55181, HC55182, HC55183, HC55184

PEAK

Page 7

Electrical Speciﬁcations Unless Otherwise Speciﬁed, T

= 0oC to 70oC for the HC55183, 184 only, all others -40oC to 85oC, VBL = -24V, VCC = +5V, AGND = BGND = 0V,

loop current limit = 25mA. All AC Parameters are speciﬁed at 600W 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0W. (Continued)

HC55180 (Note 7) HC55181, HC55182 HC55183, HC55184

PARAMETER

SUPPLY CURRENTS (Supply currents not listed are considered negligibleanddo not contribute significantly to total power dissipation.Allmeasurementsmadeunderopen circuit load conditions.)

Low Power Standby (Note 2)

Forward or Reverse

(Note 5) Forward

(Note 2)

2.0 3.7 5.0 I

- 3.7 6.0 mA IB, VB = -100V, -85V - 0.375 0.600 IBH,VBH= -100V, -85V - 0.375 0.600 IBH, VBH = -75V - 0.375 - mA I

IB, VB = -24V - 1.0 2.5 I I

(Note 7) - - - I

2.5 4.0 5.0 I

3.5 5.5 7.0 I

CC BL CC BL

2.5 4.0 5.0 I

- 1.0 2.5 I

3.5 5.5 7.0 I

- 1.3 2.0 I

CC BL CC BL

2.0 4.0 6.0 mA

- 1.0 2.5 mA

2.0 5.5 8.0 mA

- 1.3 2.5 mA IB, VB = -100V, -85V - 3.2 4.5 IBH,VBH= -100V, -85V - 1.7 2.5 IBH, VBH = -75V - 1.4 3.0 mA

Ringing (Note 2)

4.5 7.5 11 I

(Note 7) - - - I

CC BL

4.5 7.5 11 I

- 0.4 7.5 I

CC BL

- 7.5 11 mA

- 0.4 1.5 mA IB, VB = -100V, -85V - 2.3 5.0 IBH,VBH= -100V, -85V - 1.3 2.5 IBH, VBH = -75V - 1.3 2.5 mA

Forward Loopback (Note 5)

Tip Open (Note 5)

Power Denial (Note 5)

- 8.5 10.0 I IB, VB = -24V - 19 23.5 I I

- - 5.5 I IB, VB = -24V - - 1.0 I I

0.5 3.0 5.0 I

IB, VB = -24V - 0.2 0.5 I

CC BL CC BL CC BL

- 8.5 10.0 (Note 15) - - - mA

- 19 23.5 - - - mA

- - 5.5 (Note 16) - - - mA

- - 1.0 - - - mA

0.5 3.0 4.5 I

- 0.2 0.5 I

CC BL

- 3.0 5.0 mA

- 0.2 0.5 mA ON HOOK POWER DISSIPATION (Note 17) Forward or Reverse

VB = -24V - 44 60 VBL = -24V - 44 60 VBL = -24V - 44 60 mW

(Notes 5, 6) Low Power Standby

(Note 2) Ringing

(Note 2)

VB = -85V - 52 - VBH = -85V - 52 65 VBH = -75V - 46 65 mW VB = -100V - 59 - VBH = -100V - 59 75 (Note 9) VB = -85V - 190 - VBH = -85V - 190 275 VBH = -75V - 170 250 mW

VB = -100V - 220 - VBH = -100V - 220 300 (Note 9) OFF HOOK POWER DISSIPATION (Notes 5, 17) Forward or Reverse VB = -24V - 290 - VBL = -24V - 290 310 VBL = -24V - 280 310 mW

NOTES:

7. The HC55180 does not provide battery switch operation. Therefore all battery voltage references will be made to VB.VBis the voltage applied to the common connection of the device VBL and VBH pins. See the HC55180 Basic Application Circuit.

8. Ringing Voltage is measured with VRS = 0.839 V V

for -85V devices and VRS = 0.619 V

RMS

for -100V devices, VRS = 0.707

RMS

for -75V devices.

9. The HC55183 and HC55184 devices are specified with a single high battery voltagegrade.

10. The device represents a low output impedance during ringing. Therefore the voltage across the ringing load is determined by the voltage divider formed by the protection resis-

12. Longitudinal Balance is tested per IEEE455-1985, with 368Ω per Tip and Ring Terminal.

13. These parameters are tested 100% at room temperature. These parameters are guaranteed not tested across temperature via statistical characterization.

14. The HC55180, HC55183 and HC55184 do not support uncommitted switch operation.

15. The HC55183 and HC55184 do not support the Forward Loopback operating mode.

16. The HC55183 and HC55184 do not support the Tip Open operating mode.

17. The power dissipation numbers are actual device measurements and will be less than worse case calculations based on data sheet supply current limits.

tance, loop resistance and ringing load impedance.

11. The HC55180, HC55183 and HC55184 are specified with a single longitudinal balance grade.

UNITSTEST CONDITIONS MIN TYP MAX TEST CONDITIONS MIN TYP MAX TEST CONDITIONS MIN TYP MAX

HC55180, HC55181, HC55182, HC55183, HC55184

Page 8

HC55180, HC55181, HC55182, HC55183, HC55184

Design Equations

Loop Supervision Thresholds

SWITCH HOOK DETECT

The switch hook detect threshold is set by a single e xternal resistor, RSH. Equation 1 is used to calculate the value of RSH.

600 ISH⁄=

The term I

is the desired DC loop current threshold. The

loop current threshold programming range is from 5mA to 15mA.

GROUND KEY DETECT

The ground key detector senses a DC current imbalance between the Tipand Ring terminals when the ring terminal is connected to ground. The ground key detect threshold is not externally programmable and is internally ﬁxed to 12mA regardless of the switch hook threshold.

RING TRIP DETECT

The ring trip detect threshold is set by a single external resistor, R

. IRT should be set between the peak ringing

current and the peak off hook current while still ringing.

1800 IRT⁄=

The capacitor C

, in parallel with RRT, will set the ring trip

response time.

Loop Current Limit

The loop current limit of the device is programmed by the external resistor R

. The value of RIL can be calculated

using Equation 3.

1760

------------ -=

LIM

The term I

is the desired loop current limit. The loop

LIM

current limit programming range is from 15mA to 45mA.

Impedance Matching

The impedance of the device is programmed with the external component R the feedback ampliﬁer that provides impedance matching. If complex impedance matching is required, then a complex network can be substituted for R

RESISTIVE IMPEDANCE SYNTHESIS

The source impedance of the device, Z in Equation 4.

RS400 ZO()=

The required impedance is deﬁned by the terminating impedance and protection resistors as shown in Equation 5.

–=

OZL2RP

. RS is the gain setting resistor for

, can be calculated

(EQ. 1)

(EQ. 2)

(EQ. 3)

(EQ. 4)

(EQ. 5)

4-WIRE TO 2-WIRE GAIN

The 4-wire to 2-wire gain is deﬁned as the receive gain. It is a function of the terminating impedance, synthesized impedance and protection resistors. Equation 6 calculates the receive gain, G



----------------------------------------- -

–=



ZO+2RP+Z



(EQ. 6)

When the device source impedance and protection resistors equals the terminating impedance, the receive gain equals unity.

2-WIRE TO 4-WIRE GAIN

The 2-wire to 4-wire gain (G

) is the gain from tip and ring to

the VTX output. The transmit gain is calculated in Equation 7.



–=





----------------------------------------- -

ZO+2RP+Z

(EQ. 7)

When the protection resistors are set to zero, the transmit gain is -6dB.

TRANSHYBRID GAIN

The transhybrid gain is deﬁned as the 4-wire to 4-wire gain (G





ZO2RPZ



---------------------------------------

–=

(EQ. 8)

When the protection resistors are set to zero, the transhybrid gain is -6dB.

COMPLEX IMPEDANCE SYNTHESIS

Substituting the impedance programming resistor, RS, with a complex programming network provides complex impedance synthesis.

2-WIRE

NETWORK

FIGURE 1. COMPLEX PROGRAMMING NETWORK

PROGRAMMING

NETWORK

The reference designators in the programming network match the evaluation board. The component R different design equation than the R

used for resistive

has a

impedance synthesis. The design equations for each component are provided below.

RS400 R12RP()–()×=

RP400 R2×= C

PC2

400⁄=

(EQ. 9)

(EQ. 10) (EQ. 11)

Page 9

HC55180, HC55181, HC55182, HC55183, HC55184

Low Power Standby

Overview

The low power standby mode (LPS, 000) should be used during idle line conditions.The deviceis designed to operate from the high battery during this mode. Most of the internal circuitry is powered down, resulting in low power dissipation. If the 2-wire (tip/ring) DC voltage requirements are not critical during idle line conditions, the device may be operated from the low battery. Operation from the low battery will decrease the standby power dissipation.

TABLE 1. DEVICE INTERFACES DURING LPS

INTERFACE

Receive x AC transmission, impedance Ringing x Transmit x 2-Wire x Amplifiers disabled. Loop Detect x Switch hook or ground key.

2-Wire Interface

During LPS, the 2-wire interface is maintained with internal switches and voltage references. The Tip and Ring ampliﬁers are turned off to conserve power. The device will provide MTU compliance, loop current and loop supervision. Figure 2 represents the internal circuitry providing the 2-wire interface during low power standby.

ON OFF NOTES

matching and ringing are disabled during this mode.

GND

Ring terminal will be clamped by the internal reference. The same Ring relationships apply when operating from the low battery voltage. For high battery voltages (VBH) less than or equal to the internal MTU reference threshold:

RINGVBH

4+=

(EQ. 12)

Loop Current

During LPS, the device will provide current to a load. The current path is through resistors and switches, and will be function of the off hook loop resistance (R

LOOP

). This includes the off hook phone resistance and copper loop resistance. The current available during LPS is determined by Equation 13.

LOOP

1– 49–()–()600 600 R

++()⁄=

LOOP

(EQ. 13)

Internal current limiting of the standby switches will limit the maximum current to 20mA.

Another loop current related parameter is longitudinal current capability. The longitudinal current capability is reduced to 10mA

per pin. The reduction in longitudinal

RMS

current capability is a result of turning off the Tip and Ring ampliﬁers.

On Hook Power Dissipation

The on hook power dissipation of the device during LPS is determined by theoperating voltages and quiescent currents and is calculated using Equation 14.

LPSVBHIBHQ

× VBLI

× VCCI

BLQ

×++=

CCQ

(EQ. 14)

600Ω

TIP AMP

TIP

RING

RING AMP

600Ω

MTU REF

FIGURE 2. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM

MTU Compliance

Maintenance Termination Unit or MTU compliance places DC voltage requirements on the 2-wire terminals during idle line conditions. The minimum idle voltage is 42.75V. The high side of the MTU range is 56V. The voltage is expressed as the difference between Tip and Ring.

The Tip voltage is held near ground through a 600Ω resistor and switch. The Ring voltage is limited to a maximum of

-49V (by MTU REF) when operating from either the high or low battery. A switch and 600Ω resistor connect the MTU reference to the Ring terminal. When the high battery voltage exceeds the MTU reference of -49V (typically), the

The quiescent current terms are speciﬁed in the electrical tables for each operating mode. Load power dissipation is not a factor since this is an on hook mode. Some applications may specify a standby current. The standby current may be a charging current required for modern telephone electronics.

Standby Current Power dissipation

Any standby line current, I power dissipation term P power contribution is zero when the standby line current is zero.

SLCISLCVBH

49– 1I

If the battery voltage is less than -49V (the MTU clamp is off), the standby line current power contribution reduces to Equation 16.

SLCISLCVBH

Most applications do not specify charging current requirements during standby. When speciﬁed, the typical charging current may be as high as 5mA.

, introduces an additional

SLC

. Equation 15 illustrates the

SLC

x1200++()×=

SLC

x1200++()×=

SLC

(EQ. 15)

(EQ. 16)

Page 10

HC55180, HC55181, HC55182, HC55183, HC55184

Forward Active

Overview

The forward active mode (FA, 001) is the primary AC transmission mode of the device. On hook transmission, DC loop feed and voice transmission are supported during forward active. Loop supervision is provided by either the switch hook detector (E0 = 1) or the ground key detector (E0= 0). The device may be operated from either high or lo w battery for onhook transmission and low battery for loop feed.

On-Hook Transmission

The primary purpose of on hook transmission will be to support caller ID and other advanced signalling features. The transmission overload levelwhile on hook is 3.5V

When operating from the high battery,the DC voltages at Tip and Ring are MTU compliant. The typical Tip voltage is -4V and the Ring voltage is a function of the battery voltage for battery voltages less than -60V as shown in Equation 17.

RINGVBH

4+=

Loop supervision is provided by the switch hook detector at the

DET output. When DET goes low, the low battery should

be selected for DC loop feed and voice transmission.

Feed Architecture

The design implements a voltage feed current sense architecture. The device controls the voltage across Tip and Ring based on the sensing of load current. Resistors are placed in series with Tip and Ring outputs to provide the current sensing. The diagram below illustrates the concept.

OUT

FIGURE 3. VOLTAGE FEED CURRENT SENSE DIAGRAM

By monitoring the current at the ampliﬁer output, a negative feedback mechanism sets the output voltage for a deﬁned load. The ampliﬁer gains are set by resistor ratios (R R

) providing all the performance beneﬁts of matched

resistors. The internal sense resistor, R

, is much smaller

than the gain resistors and is typically 20Ω for this device. The feedback mechanism, K

, represents the ampliﬁer

conﬁguration providing the negative feedback.

DC Loop Feed

The feedback mechanism for monitoring the DC portion of the loop current is the loop detector. A low pass ﬁlter is used in the feedback to block voice band signals from interfering with the loop current limit function. The pole of the low pass ﬁlter is set by the external capacitor C external capacitor should be 4.7µF.

. The value of the

PEAK

(EQ. 17)

, RB,

Most applications will operate the device from low battery while off hook. The DC feed characteristic of the device will drive Tip and Ring towards half battery to regulate the DC loop current. For light loads, Tip will be near -4V and Ring will be near V

+ 4V.The following diagram shows the DC

VBL

feed characteristic.

TR(OC)

, DC (V)

(mA)

FIGURE 4. DC FEED CHARACTERISTIC

LOOP

The point on the y-axis labeled V

m = (∆VTR/∆IL) = 10kΩ

LIM

is the open circuit

TR(OC)

Tip to Ring voltage and is deﬁned by the feed battery voltage.

TR OC()VBL

8–=

(EQ. 18)

The curve of Figure 5 determines the actual loop current for a given set of loop conditions. The loop conditions are determined by the low battery voltage and the DC loop impedance. The DC loop impedance is the sum of the protection resistance, copper resistance (ohms/foot) and the telephone off hook DC resistance.

(Ω)

LOAD CHARACTERISTIC

KNEE

FIGURE 5. I

(mA)

LOOP

LIM

VERSUS R

LOOP

The slope of the feed characteristic and the battery voltage deﬁne the maximum loop current on the shortest possible loop as the short circuit current I

SCILIM

The term I

------------------------------------------------------+=

is the programmed current limit, 1760/RIL.

LIM

The line segment I

–

TR OC()2RPILIM

10e3

represents the constant current region

(EQ. 19)

of the loop current limit function.

IAI

LIM

--------------------------------------------------------------+=

–

TR OC()RLOOPILIM

10e3

(EQ. 20)

The maximum loop impedance for a programmed loop current is deﬁned as R

TR OC()

KNEE

When R

------------------------=

LIM

is exceeded, the device will transition from

KNEE

(EQ. 21)

constant current feed to constant voltage, resistive feed. The line segment I

represents the resistive feed portion of the

load characteristic.

TR OC()

------------------------=

LOOP

(EQ. 22)

Page 11

HC55180, HC55181, HC55182, HC55183, HC55184

Voice Transmission

The feedback mechanism for monitoring the AC portion of the loop current consists of two ampliﬁers, the sense ampliﬁer (SA) and the transmit ampliﬁer (TA). The AC feedback signal is used for impedance synthesis. A detailed model of the AC feed back loop is provided below.

TIP

RING

3R 3R

1:1

0.75R

R/2

FIGURE 6. AC SIGNAL TRANSMISSION MODEL

The gain of the transmit ampliﬁer, set by R programmed impedance of the device. The capacitor C blocks the DC component of the loop current. The ground symbols in the model represent AC grounds, not actual DC potentials.

The sense amp output voltage,V

, as a function of Tip and

Ring voltage and load is calculated using Equation 23.

VTVR–()–

------

The transmit ampliﬁer provides the programmable gain required for impedance synthesis. In addition, the output of this ampliﬁer interfaces to the CODEC transmit input. The output voltage is calculated using Equation 24.



----------

–=

VTX



8e3

Once the impedance matching components have been selected using the design equations, the above equations provide additional insight as to the expected AC node voltages for a speciﬁc Tip and Ring load.

Transhybrid Balance

The ﬁnal step in completing the impedance synthesis design is calculating the necessary gains for transhybrid balance. The AC feed back loop produces an echo at the V of the signal injected at V

. The echo must be cancelled to

maintain voice quality. Most applications will use a summing ampliﬁer in the CODEC front end as shown below to cancel the echo signal.

, determines the

VRX

VTX

-IN C

VFB

(EQ. 23)

(EQ. 24)

output

1:1

HC5518x

VRX

VTX

-IN

+2.4V

RX OUT

TX IN

CODEC

FIGURE 7. TRANSHYBRID BALANCE INTERFACE

The resistor ratio, R the transmit gain, G

, provides the ﬁnal adjustment for

F/RB

. The transmit gain is calculated using

Equation 25.



Most applications set R

G–





------- -

= RB, hence the device 2-wire to

4-wire equals the transmit gain. Typically R

is greater than

(EQ. 25)

20kΩ to prevent loading of the device transmit output. The resistor ratio, RF/RA, is determined by the transhybrid

gain of the device, G transmit gain requirement and R

. RF is previously deﬁned by the

is calculated using

Equation 26.

----------=

(EQ. 26)

Power Dissipation

The power dissipated by the device during on hook transmission is strictly a function of the quiescent currents for each supply voltage during Forward Active operation.

FAQVBH

BHQ

× VCCI

BLQ

×++=

CCQ

I×

VBLI

Off hook power dissipation is increased above the quiescent power dissipation by the DC load. If the loop length is less than or equal to R current, I

, and the power dissipation is calculated using

, the device is providing constant

KNEE

Equation 28.

FA IA()PFA Q()VBLxIA

()R

If the loop length is greater than R

()–+=

KNEE

LOOP

, the device is operating in the constant voltage, resistive feed region. The power dissipated in this region is calculated using Equation 29.

FA IB()PFA Q()VBLxIB

()R

()–+=

LOOP

Since the current relationships are different for constant current versus constant voltage, the region of device operation is critical to valid power dissipation calculations.

(EQ. 27)

(EQ. 28)

(EQ. 29)

Page 12

HC55180, HC55181, HC55182, HC55183, HC55184

Reverse Active

Overview

The reverse active mode (RA, 011) provides the same functionality as the forward active mode. On hook transmission, DC loop feed and voice transmission are supported. Loop supervision is provided by either the switch hook detector (E0 = 1) or the ground key detector (E0 = 0). The device may be operated from either high or low battery.

During reverse active the Tip and Ring DC voltage characteristics exchange roles. That is, Ring is typically 4V below ground and Tip is typically 4V more positive than battery. Otherwise, all feed and voice transmission characteristics are identical to forward active.

Silent Polarity Reversal

Changing from forward active to reverse active or vice versa is referred to as polarity reversal. Many applications require slew rate control of the polarity reversal event. Requirements range from minimizing cross talk to protocol signalling.

The deviceuses an external low voltage capacitor, C set the reversal time. Once programmed, the reversal time will remain nearly constant over various load conditions. In addition, the reversaltiming capacitor is isolated from the AC loop, therefore loop stability is not impacted.

The internal circuitry used to set the polarity reversal time is shown below.

POL

75kΩ

POL

,to

Ringing

Overview

The ringing mode (RNG, 100) provides linear ampliﬁcation to support a variety of ringing waveforms. A programmable ring trip function provides loop supervision and auto disconnect upon ring trip. The device is designed to operate from the high battery during this mode.

Architecture

The device provides linear ampliﬁcation to the signal applied to the ringing input, V device is 80V/V. The circuit model for the ringing path is shown in the following ﬁgure.

TIP

RING

FIGURE 9. LINEAR RINGING MODEL

The voltage gain from the VRS input to the Tip output is 40V/V. The resistor ratio provides a gain of 8 and the current mirror provides a gain of 5. The voltage gain from the VRS input to the Ring output is -40V/V. The equations for the Tip and Ring outputs during ringing are provided below.

----------- 40 VRS×()+=

----------- 40 VRS×()–=

. The differential ringing gain of the

R/8

5:1

800K

VRS

(EQ. 31)

(EQ. 32)

FIGURE 8. REVERSAL TIMING CONTROL

During forward active, the current from sourceI1 charges the external timing capacitor C

and the switch is open. The

POL

internal resistor provides a clamping function for voltageson the POL node. During reverse active, the switch closes and I2 (roughly twice I1) pulls current from I1 and the timing capacitor. The current at the POL node provides the drive to a differential pair which controls the reversal time of the Tip and Ring DC voltages.

POL

∆time

----------------=

75000

(EQ. 30)

Where ∆time is the required reversal time. Polarized capacitors may be used for C

. The low voltage at the

POL

POL pin and minimal voltage excursion ±0.75V, are well suited to polarized capacitors.

Power Dissipation

The power dissipation equations for forward active operation also apply to the reverse active mode.

When the input signal at VRS is zero, the Tip and Ring ampliﬁer outputs are centered at half battery. The device provides auto centering for easy implementation of sinusoidal ringing waveforms.Both AC and DC control of the Tip and Ring outputs is available during ringing. This feature allows for DC offsets as part of the ringing waveform.

Ringing Input

The ringing input, VRS, is a high impedance input. The high impedance allows the use of low value capacitors for AC coupling the ring signal. The V during the ringing mode, therefore a free running oscillator may be connected to VRS at all times.

When operating from a battery of -100V, each ampliﬁer, Tip and Ring, will swing a maximum of 95V maximum signal swing at VRS to achieve full scale ringing is approximately 2.4V

. The low signal levels are compatible

P-P

with the output voltage range of the CODEC. The digital nature of the CODEC ideally suits it for the function of programmable ringing generator. See Applications.

input is enabled only

. Hence, the

P-P

Page 13

HC55180, HC55181, HC55182, HC55183, HC55184

Logic Control

Ringing patterns consist of silent intervals. The ringing to silent pattern is called the ringing cadence. During the silent portion of ringing, the device can be programmed to any other operating mode. The most likely candidates are low power standby or forward active. Depending on system requirements, the low or high battery may be selected.

Loop supervision is provided with thering trip detector.The ring trip detector senses the change in loop current when the phone is taken off hook. The loop detector full wav e rectifies the ringing current, which is then filtered with external components R

and CRT. The resistor RRT sets the trip threshold and the

capacitorC

setsthe trip responsetime.Most applications will

require a trip response time less than 150ms. Three very distinct actions occur when the devices detects a

ring trip. First, the

DET output is latched low. The latching mechanism eliminates the need for software ﬁltering of the detector output. The latch is cleared when the operating mode is changed externally. Second, the VRS input is disabled, removing the ring signal from the line. Third, the device is internally forced to the forward active mode.

Power Dissipation

The power dissipation during ringing is dictated by the load driving requirements andthe ringingwaveform.The keyto valid power calculations is the correct definition of average and RMS currents. The average current defines the high battery supply current. The RMS current defines the load current.

The cadence provides a time averaging reduction in the peak power. The total power dissipation consists of ringing power, P

RNGPr

The terms t interval is t ratio t

The quiescent power of the device in the ringing mode is deﬁned in Equation 34.

rQ()VBHIBHQ

The total power during the ringing interval is the sum of the quiescent power and loading power:

rPrQ()VBHIAVG

For sinusoidal waveforms, the average current, I deﬁned in Equation 36.

AVG

The silent interval power dissipation will be determined by the quiescent power of the selected operating mode.

, and the silent interval power, Ps.

--------------

× P

trts+

and tS represent the cadence. The ringing

and the silent interval is tS. The typical cadence

is 1:2.

R:tS

× VBLI

RMS



-- -

------------------------------------------



RENRLOOP

--------------

×+=

trts+

× VCCI

BLQ

------------------------------------------–+=

RENRLOOP

2×

2 RMS

×++=

CCQ

AVG

(EQ. 33)

(EQ. 34)

(EQ. 35)

, is

(EQ. 36)

Forward Loop Back

Overview

The forward loop back mode (FLB, 101) provides test capability for the device. An internal signal path is enabled allowing for both DC and AC veriﬁcation. The internal 600Ω terminating resistor has a tolerance of ±20%. The device is intended to operate from only the low battery during this mode.

Architecture

When the forward loop back mode is initiated internal switches connect a 600Ω load across the outputs of the Tip and Ring ampliﬁers.

TIP

TIP AMP

600Ω

RING AMP

RING

FIGURE 10. FORWARD LOOP BACK INTERNAL TERMINATION

DC Veriﬁcation

When the internal signal path is provided, DC current will ﬂow from Tip to Ring. The DC current will force indicating the presence of loop current. In addition, the output will also go low. This does not indicate a thermal alarm condition. Rather, proper logic operation is veriﬁed in the event of a thermal shutdown. In addition to verifying device functionality, toggling the logic outputs veriﬁes the interface to the system controller.

AC Veriﬁcation

The entire AC loop of the device is active during the forward loop back mode. Therefore a 4-wire to 4-wire level test capability is provided. Depending on the transhybrid balance implementation, test coverage is provided by a one or two step process.

System architectures which cannot disable the transhybrid function would require a two step process. The ﬁrst step would be to send a test tone to the devicewhile on hook and not in forward loop back mode. The return signal would be the test level times the gain R ampliﬁer. Since the device would not be terminated, cancellation would not occur. The second step would be to program the device to FLB and resend the test tone. The return signal would be much lower in amplitude than the ﬁrst step, indicating the device was active and the internal termination attenuated the return signal.

System architectures which disable the transhybrid function would achieve test coverage with a signal step. Once the transhybrid function is disable, program the device for FLB and send the test tone. The return signal level is determined by the 4-wire to 4-wire gain of the device.

of the transhybrid

F/RA

DET low,

ALM

Page 14

HC55180, HC55181, HC55182, HC55183, HC55184

Tip Open

Overview

The tip open mode (110) is intended for compatibility for PBX type interfaces. Used during idle line conditions, the device does not provide transmission. Loop supervision is provided by either the switch hook detector (E0 = 1) or the ground key detector (E0 = 0). The ground key detector will be used in most applications. The device may be operated from either high or low battery.

Functionality

During tip open operation, the Tip ampliﬁer is disabled and the Ring ampliﬁer is enabled. The minimum Tip impedance is 30kΩ. The only active path through the device will be the Ring ampliﬁer.

In keeping with the MTU characteristics of the device, Ring will not exceed -56.5V when operating from the high battery. Though MTU does not apply to tip open, safety requirements are satisﬁed.

On Hook Power Dissipation

The on hook power dissipation of the device during tip open is determined by the operating voltages and quiescent currents and is calculated using Equation 37.

TOVBHIBHQ

The quiescent current terms are speciﬁed in the electrical tables for each operating mode. Load power dissipation is not a factor since this is an on hook mode.

× VBLI

× VCCI

BLQ

×++=

CCQ

(EQ. 37)

Battery Switching

Overview

The integrated battery switch selects between the high battery and low battery. The battery switch is controlled with the logic input BSEL. When BSEL is a logic high, the high battery is selected and when a logic low, the low battery is selected. All operating modes of the device will operate from high or low battery except forward loop back.

Functionality

The logic control is independent of the operating mode decode. Independent logic control provides the most flexibility and will support all application configurations.

When changing device operating states, battery switching should occur simultaneously with or prior to changing the operating mode. In most cases, this will minimize overall power dissipation and prevent glitches on the

The only external component required to support the battery switch is a diode in series with the VBH supply lead. In the event that high battery is removed, the diode allows the device to transition to low battery operation.

Low Battery Operation

All off hook operating conditions should use the low batter y. The prime benefit will be reduced power dissipation. The typical low battery for the device is -24V. However this may be increased to support longer loop lengths or high loop current requirements. Standby conditions may also operate from the low battery if MTU compliance is not required, further reducing standby power dissipation.

DET output.

Power Denial

Overview

The power denial mode (111) will shutdown the entire device except for the logic interface. Loop supervision is not provided. This mode may be used as a sleep mode or to shut down in the presence of a persistent thermal alarm. Switching between high and low battery will have no effect during power denial.

Functionality

During power denial, both the Tip and Ring ampliﬁers are disabled, representing high impedances. The voltages at both outputs are near ground.

Thermal Shutdown

In the event the safe die temperature is exceeded, the ALM output will go low and automatically shut down. When the device cools, go high and fault persists, down. Programming power denial will permanently shutdown the device and stop the self cooling cycling.

DET will reflect the loop status. If the thermal

ALM will go low again and the part will shut

DET will go high and the part will

ALM will

High Battery Operation

Other than ringing, the high battery should be used for standby conditions which must provide MTU compliance. During standby operation the power consumption is typically 50mW with -100V battery. If ringing requirements do not require full 100V operation, then a lower battery will result in lower standby power.

High Voltage Decoupling

The 100V rating of the device will require a capacitor of higher voltage rating for decoupling. Suggested decoupling values for all device pins are 0.1µF. Standard surface mount ceramic capacitors are rated at 100V. For applications driven at low cost and small size, the decoupling scheme shown below could be implemented.

0.22µ 0.22µ

VBH VBL

HC5518X

FIGURE 11. ALTERNATE DECOUPLING SCHEME

As with all decoupling schemes, the capacitors should be as close to the device pins as physically possible.

Page 15

HC55180, HC55181, HC55182, HC55183, HC55184

Uncommitted Switch

Overview

The uncommitted switch is a three terminal device designed for ﬂexibility. The independent logic control input, allows switch operation regardless of device operating mode. The switch is activated by a logic low. The positive and negative terminals of the device are labeled SW+ and SW- respectively.

Relay Driver

The uncommitted switch may be used as a relay driver by connecting SW+ to the relay coil and SW- to ground. The switch is designed to have a maximum on voltage of 0.6V with a load current of 45mA.

+5V

RELAY

SW+

SW-

FIGURE 12. EXTERNAL RELAY SWITCHING

Since the device provides the ringing waveform, the relay functions which may be supported include subscriber disconnect, test access or line interface bypass. An external snubber diode is not required when using the uncommitted switch as a relay driver.

SWC,

SWC

Test Load

The switch may be used to connect test loads across Tip and Ring. The test loads can provide external test termination for the device. Proper connection of the uncommitted switch to Tip and Ring is shown below.

TIP

RING

TEST

LOAD

SW+

SW-

FIGURE 13. TEST LOAD SWITCHING

The diode in series with the test load blocks current from ﬂowing through the uncommitted switch when the polarity of the Tip and Ring terminals are reversed. In addition to the reverseactivestate, the polarity of Tipand Ring are reversed for half of the ringing cycle. With independent logic control and the blocking diode, the uncommitted switch may be continuously connected to the Tip and Ring terminals.

SWC

Page 16

HC55180, HC55181, HC55182, HC55183, HC55184

Basic Application Circuits

PS1

PS3

VCC

VBL

VBH

TIP

HC55180

RING

RTD

VRX

VRS

VTX

-IN

VFB

ILIM

POL

CDC

POL

E0 F0 F1 F2

DET

ALM

BGNDAGND

FIGURE 14. HC55180 BASIC APPLICATION CIRCUIT

TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST

COMPONENT VALUE TOLERANCE RATING

U1 - Ringing SLIC HC5518x N/A N/A R

, CRS, CTX, CRT, C

PS1

, C

PS2

PS3

, R

POL

, C

20kΩ 1% 0.1W

49.9kΩ 1% 0.1W

71.5kΩ 1% 0.1W 210kΩ 1% 0.1W

0.47µF 20% 10V

4.7µF 20% 10V

0.1µF 20% >100V

0.1µF 20% 100V 1N400X type with breakdown > 100V. Protection resistor values are application dependent and will be determined by protection re-

quirements. Standard applications will use ≥ 35Ω per side.

Design Parameters: Ring Trip Threshold = 90mA

, Switch Hook Threshold = 12mA, Loop Current Limit = 24.6mA, Synthesize Device Im-

PEAK

pedance = 210kΩ/400 = 525Ω, with 39Ω protection resistors, impedance across Tip and Ring terminals = 603Ω. Where applicable, these component values apply to the Basic Application Circuits for the HC55180, HC55181, HC55182, HC55183 and HC55184. Pins not shown in the Basic Application Circuit are no connect (NC) pins.

Page 17

HC55180, HC55181, HC55182, HC55183, HC55184

PS1

PS2

PS3

VCC VBL

TIP

RING

HC55181

SW+

SW-

RTD

ILIM

CDC

POL

VBH

VRX

VRS

VTX

-IN C

VFB

SWC

BSEL

F0 F1

DET

ALM

BGNDAGND

PS1

PS2

PS3

VCC VBL

TIP

HC55182

RING

SW+

SW-

RTD

ILIM

CDC

VBH

VRX

VRS

VTX

-IN C

VFB

SWC

BSEL

E0 F0 F1 F2

DET

ALM

BGNDAGND

FIGURE 15. HC55181 BASIC APPLICATION CIRCUIT

PS1

PS2

PS3

VCC VBL

TIP

RING

RTD

HC55183

ILIM

CDC

VBH

VRX

VRS

VTX

-IN C

VFB

BSEL

F0 F1 F2

DET

ALM

BGNDAGND

FIGURE 17. HC55182 BASIC APPLICATION CIRCUIT

PS1

PS2

PS3

VCC VBL

TIP

RING

RTD

HC55184

ILIM

CDC

POL

VBH

VRX

VRS

VTX

-IN C

VFB

BSEL

E0 F0 F1 F2

DET

ALM

BGNDAGND

FIGURE 16. HC55183 BASIC APPLICATION CIRCUIT

FIGURE 18. HC55184 BASIC APPLICATION CIRCUIT

Page 18

HC55180, HC55181, HC55182, HC55183, HC55184

Additional Application Diagrams

Reducing Overhead Voltages

The transmission overhead v oltage of the de vice is internally set to 4V per side. The overhead v oltage ma y be reduced b y injecting a negative DC voltage on the receive input using a voltage divider (Fig. 19). Accordingly, the 2-wire port overload level will decrease the same amount as the injected offset.

VBL

, to the Tip and Ring

FROM CODEC

. The sum of

(EQ. 38)

160 kΩ

VRX

1:1

HC5518X

FIGURE 19. EXTERNAL OVERHEAD CONTROL

The divider shunt resistance is the parallel combination of the internal 160kΩ resistor and the external R R

and R2 should be greater than 500kΩ to minimize the

additional power dissipation of the divider. The DC gain relationship from the divider voltage,V outputs is shown below.

VBL82V

TR–

×()––=

will not match the 200Ω teletax impedance. The gain set by R

cancels the impedance matching feedback with respect

to the teletax injection point. Therefore the device appears as a low impedance source for teletax. The resistor R

calculated using the following equation.

-------------------------------------------------------------------

200 2 RP× RS400⁄()++

200

×=

(EQ. 39)

The signal levelacross a 200Ω load will be twice the injected teletax signal level.As the teletax levelat VTX will equal the injection level, set R

for cancellation. The value of R

C=RB

is based on the voice band transhybrid balance requirements. The connection of the teletax source to the transhybrid ampliﬁer should be AC coupled to allow proper biasing of the transhybrid ampliﬁer input

CFB

-INVFB VTX

TELETAX

SOURCE

FIGURE 21. TELETAX SIGNALLING

+2.4V

TX IN

CODEC

With a low battery voltage -24V and a divider voltage of

-0.5V, the Tip to Ring voltage is 17V. As a result, the overhead voltage is reduced from 8V to 7V and the overload level will decrease from 3.5V

PEAK

to 3.0V

PEAK

CODEC Ringing Generation

Maximum ringing amplitudes of the device are achievedwith signal levels approximately 2.4V

. Therefore the low pass

P-P

receive output of the CODEC may serve as the low levelring generator. The ringing input impedance of 480kΩ minimum should not interfere with CODEC drive capability. A single external capacitor is required to AC coupled the ringing signal from the CODEC. The circuit diagram for CODEC ringing is shown below.

160 kΩ

VRX

RX OUT

1:1

HC5518X

FIGURE 20. CODEC RINGING INTERFACE

480K

VRS

CODEC

Implementing Teletax Signalling

A resistor, RT, is required at the -IN input of the device for injecting the teletax signal (Figure 20). For most applications the synthesized deviceimpedance (i.e., 600Ω)

Ringing With DC Offsets

The balanced ringing waveform consists of zero DC offset between the Tip and Ring terminals. However, the linear ampliﬁer architecture provides control of the DC offset during ringing. The DC gain is the same as the AC gain, 40V/V per ampliﬁer. Positive DC offsets applied directly to the ringing input will shift both Tip and Ring away from half battery towards ground and battery respectively. A voltage divider on the ringing input may be used to generate the offset (Figure 22). The reference voltage, V either the CODEC 2.4V reference voltage or the 5V supply.

REF

VRS

480K

HC5518X

FIGURE 22. EXTERNAL OVERHEAD CONTROL

An offset during ringing of 30V, would require a DC shift of 15V at Tip and 15V at Ring. The DC offset would be created by a +0.375V (V

) at the VRS input. The divider resistors

should be selected to minimize the value of the AC coupling capacitor C

and the loading of the ring generator and

voltage reference. The ringing input impedance should also be accounted for in divider resistor calculations.

REF

, can be

FROM RING GEN.

Page 19

HC55180, HC55181, HC55182, HC55183, HC55184

Pin Descriptions

PLCC SYMBOL DESCRIPTION

1 TIP TIP power amplifier output. 2 BGND Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground. Inter-

nally separate from AGND but it is recommended that it is connected to the same potential as AGND. 3 VBL Low battery supply connection. 4 VBH High battery supply connection for the most negative battery. 5 SW+ Uncommitted switch positive terminal. This pin is a no connect (NC) on the HC55180, HC55183 and HC55184. 6 SW- Uncommitted switch negative terminal. This pin is a no connect (NC) on the HC55180, HC55183 and HC55184. 7 SWC Switch control input. This TTL compatible input controls the uncommitted switch, with a logic “0” enabling the switch and

logic “1” disabling the switch. This pin is a no connect (NC) on the HC55180, HC55183 and HC55184. 8 F2 Mode control input - MSB. F2-F0 for the TTL compatible parallel control interface for controlling the various modes of

operation of the device. 9 F1 Mode control input.

10 F0 Mode control input. 11 E0 Detector Output Selection Input. This TTL input controls the multiplexing of the SHD (E0 = 1) and GKD (E0 = 0)

comparator outputs to the DET output based upon the state at the F2-F0 pins (see the Device Operating Modes table

shown on page 2).

12 DET Detector Output - This TTL outputprovideson-hook/off-hook status of the loop based upon the selected operating mode.

The detected output will either be switch hook, ground key or ring trip (see the Device Operating Modes table shown on

page 2).

13 ALM Thermal Shutdown Alarm. This pin signals the internal die temperature has exceeded safe operating temperature

(approximately 175oC) and the device has been powered down automatically.

14 AGND Analog ground reference. This pin should be externally connected to BGND. 15 BSEL Selects between high and low battery, with a logic “1” selecting the high battery and logic “0” the low battery. This pin is

a no connect (NC) on the HC55180.

16 NC This pin is a no connect (NC) for all the devices. 17 POL External capacitor on this pin sets the polarity reversal time. This pin is a no connect on the HC55182 and HC55183. 18 VRS Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode. 19 VRX Analog Receive Voltage - 4-wire analog audio input voltage. AC couples to CODEC. 20 VTX Transmit output voltage - Output of impedance matching amplifier, AC couples to CODEC. 21 VFB Feedback voltage for impedance matching. This voltage is scaled to accomplish impedance matching. 22 -IN Impedance matching amplifier summing node. 23 VCC Positive voltage power supply, usually +5V. 24 CDC DC Biasing Filter Capacitor - Connects between this pin and VCC. 25 RTD Ring trip filter network. 26 ILIM Loop Current Limit programming resistor. 27 RD Switch hook detection threshold programming resistor. 28 RING RING power amplifier output.

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