Datasheet HC5517B Datasheet (Intersil Corporation)

HC5517B

Data Sheet July 1998 File Number

Low Cost 3 REN Ringing SLIC for ISDN
Modem/TA and WL

The HC5517B low cost, 3 REN ringing SLIC is designed to
accommodate a wide variety of short loop applications and
provides the same degree of flexibility as the high
performance HC5517. The flexible features include open
circuit tip to ring DC voltages, user defined ringing
waveforms, ring trip detection thresholds, and loop current
limits that can be tailored for many applications. Additional
features of the HC5517B are complex impedance matching,
pulse metering, and transhybrid balance. The HC5517B is
designed for use in short loop, low cost systems where
traditional ring generation is not economically feasible.

The device is manufactured in a high voltage Dielectric
Isolation (DI) process. The DI process provides substrate
latch up immunity, resulting in a robust system design. A
thermal shutdown with an alarm output and line fault
protection are also included for operation in harsh
environments.

4404.2

Features

• Load Drive Capability. . . . . . . . . . . . . . . . . . . . . . . 3REN

• Trapezoidal, Square or Sine Wave Capability

• Ringing from -80V Battery . . . . . . . . . . . . . . . . . . .75V

• Ringing from -75V Battery . . . . . . . . . . . . . . . . . . .70V

P-P
P-P

• Ringing Current Independent of Loop Current Setting

• Ringing Crest Factor Independent of REN Loading

• Latchup Immune to Inductive Kick Back and Hot Plug

• Fax, Answering Machine and MTU Compatible

• Resistive and Complex Impedance Matching

• Programmable Loop Current Limit

• Switch Hook, Ring Trip and Ground Key Detection

• Single Low Voltage +5V Supply

Applications

Ordering Information

PART

NUMBER

HC5517BCM 0 to 75 28 Ld PLCC N28.45
HC5517BCB 0 to 75 28 SOIC M28.3

TEMP.RANGE

(oC) PACKAGE PKG. NO.

Block Diagram

TIP FEED

TIP SENSE

RING FEED
RING SENSE 1
RING SENSE 2

V

REF

RTI

V

BAT

V

CC

AGND
BGND

2-WIRE

INTERFACE

BIAS

LOOP CURRENT

DETECTOR

CURRENT

RING TRIP

DETECTOR

IIL LOGIC INTERFACE

DETECTOR

FAULT

LIMIT

• Solid State Line Interface Circuit for Hybrid Fiber Coax, Set
Top Box, Voice/Data Modems

• Related Literature

- AN9607, Impedance Matching Design Equations

- AN9628, AC Voltage Gain

- AN9636, Implementing an Analog Port for ISDN

- AN549, The HC-5502/4X Telephone SLIC

V

4-WIRE

INTERFACE

-

+

RELAY

DRIVER

RX

V

TX

V

RING

- IN 1

OUT 1

SHD
ALM

I

LIMIT

RTD
RDO

61

F1 F0 RS

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

TST RDI

http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999

HC5517B

Absolute Maximum Ratings T

Maximum Supply Voltages

(VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7V

(VCC)-(V

Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +15V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90V

BAT

Operating Conditions

Temperature Range

HC5517BCM, HC5517BCB . . . . . . . . . . . . . . . . . . . .0oC to 75oC

Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V to +12V

Positive Power Supply (VCC). . . . . . . . . . . . . . . . . . . . . . . +5V ±5%

Negative Power Supply (V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied

NOTES:

1. θJAis measured with the component mounted on an evaluation board PC board in free air.

2. All grounds (AGND, BGND) must be applied before VCCor V
to run separate grounds off a line card, the AGND must be applied first.

) . . . . . . . . . . . . . . . . . . .-16V to -80V

BAT

Electrical Specifications Unless Otherwise Specified, Typical Parameters are at T

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

RINGING TRANSMISSION PARAMETERS

Input Impedance (Note 3) 5.4 kΩ

V

RING

4-Wire to 2-Wire Gain V

AC TRANSMISSION PARAMETERS

RX Input Impedance 300Hz to 3.4kHz (Note 3) 108 kΩ
TX Output Impedance 300Hz to 3.4kHz (Note 3) 20 Ω
4-Wire Input Overload Level 300Hz to 3.4kHz R

2-Wire Return Loss Matched for 600Ω (Note 3)

SRL LO 26 35 dB
ERL 30 40 dB
SRL HI 30 40 dB

2-Wire Longitudinal to Metallic Balance
Off Hook

4-Wire Longitudinal Balance Off Hook 300Hz to 3400Hz (Note 3) 40 dB
Low Frequency Longitudinal Balance I
Longitudinal Current Capability I
Insertion Loss 0dBm at 1kHz, Referenced 600Ω

2-Wire/4-Wire (Includes External Transhybrid
Amplifier with a Gain of 2.4)

4-Wire/2-Wire ±0.05 ±0.2 dB
4-Wire/4-Wire (Includes External Transhybrid

Amplifier with a Gain of 2.4)

=25oC Thermal Information

A

Thermal Resistance (Typical, Note 1) θJA(oC/W)

PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Maximum Junction Temperature, Plastic Packages. . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(SOIC, PLCC - Lead Tips Only)

Die Characteristics

Transistor Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224

Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 x 120

Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Bipolar-DI

ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V

. Failure to do so may result in premature failure of the part. If a user wishes

BAT

Operating TemperatureRange, V
at 600Ω 2-Wire Terminating Impedance

to Vt-r (Note 3) 40 V/V

RING

(Note 3)

Per ANSI/IEEE STD 455-1976 (Note 3) 300Hz to
3400Hz

= 40mA TA = 25oC (Note 3) 10 23 dBrnc

LINE

= 40mA TA = 25oC (Note 3) 40 mA

LINE

= -24V,VCC= +5V,AGND = BGND = 0V.All AC Parameters are specified

BAT

= 1200Ω, 600Ω Reference

L

= 25oC, Min-Max Parameters are over

A

+1.0 V

40 dB

±0.05 ±0.2 dB

BAT

PEAK

RMS

±0.35 dB

62

HC5517B

Electrical Specifications Unless Otherwise Specified, Typical Parameters are at T

Operating TemperatureRange, V

= -24V,VCC= +5V,AGND = BGND = 0V.All AC Parameters are specified

BAT

= 25oC, Min-Max Parameters are over

A

at 600Ω 2-Wire Terminating Impedance (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Frequency Response 300Hz to 3400Hz (Note 3) Referenced to Absolute

- ±0.02 ±0.06 dB

Level at 1kHz, 0dBm Referenced 600Ω

Level Linearity Referenced to -10dBm (Note 3)

2-Wire to 4-Wire and 4-Wire to 2-Wire +3 to -40dBm - - ±0.08 dB

-40 to -50dBm - - ±0.12 dB

-50 to -55dBm - - ±0.3 dB

Absolute Delay (Note 3)

2-Wire/4-Wire 300Hz to 3400Hz - - 1.0 µs
4-Wire/2-Wire 300Hz to 3400Hz - - 1.0 µs

4-Wire/4-Wire 300Hz to 3400Hz - 0.95 1.5 µs
Transhybrid Loss V
Total Harmonic Distortion

2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire
Idle Channel Noise

2-Wire and 4-Wire

= 1V

IN

Reference Level 0dBm at 600Ω
300Hz to 3400Hz (Note 3)

(Note 3)
C-Message

at 1kHz (Note 3,4) 30 40 - dB

P-P

- - -50 dB

- 3 - dBrnC

Psophometric (Note 3) - -87 - dBmp

Power Supply Rejection Ratio (Note 3)

to 2-Wire 20 40 - dB

V

CC

V

to 4-Wire 20 40 - dB

CC

to 2-Wire 20 40 - dB

V

BAT

to 4-Wire 20 50 - dB

V

BAT

V

to 2-Wire (Note 3)

CC

to 4-Wire 20 28 - dB

V

CC

to 2-Wire 20 50 - dB

V

BAT

V

to 4-Wire 20 50 - dB

BAT

30Hz to 200Hz, RL = 600Ω

30 40 - dB

200Hz to 16kHz, RL = 600Ω

DC PARAMETERS

Loop Current Programming

Limit Range 20(Note

-60mA

5)

Accuracy 15 - - %
Loop Current During Power Denial R

= 200Ω - ±4 ±7mA

L

Fault Currents

TIP to Ground (Note 3) -30-mA

RING to Ground - 120 - mA

TIP and RING to Ground (Note 3) - 150 - mA
Switch Hook Detection Threshold -1215mA
Ring Trip Comparator Voltage Threshold -0.28 -0.24 -0.22 V
Thermal

ALARM Output (Note 3) Safe Operating Die Temperature Exceeded 140 - 160

o

C

Dial Pulse Distortion (Note 3) - 0.1 0.5 ms

63

HC5517B

Electrical Specifications Unless Otherwise Specified, Typical Parameters are at T

Operating TemperatureRange, V

= -24V,VCC= +5V,AGND = BGND = 0V.All AC Parameters are specified

BAT

= 25oC, Min-Max Parameters are over

A

at 600Ω 2-Wire Terminating Impedance (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Uncommitted Relay Driver

On Voltage V

OL

IOL (RDO) = 30mA - 0.2 0.5 V

Off Leakage Current - ±10 ±100 µA
TTL/CMOS Logic Inputs (F0, F1, RS, TST, RDI)

Logic ‘0’ V

Logic ‘1’ V

IL
IH

Input Current (F0, F1, RS,
Input Current (F0, F1, RS,

TST, RDI) IIH, 0V ≤ VIN≤ 5V - - -1 µA
TST, RDI) IIL, 0V ≤ VIN≤ 5V - - -100 µA

0 - 0.8 V

2.0 - 5.5 V

Logic Outputs

Logic ‘0’ V

Logic ‘1’ V

OL
OH

Power Dissipation On Hook V

Power Dissipation Off Hook V

I

= 800µA - 0.3 0.6 V

LOAD

I

= 40µA 2.7 - - V

LOAD

CC

V

CC
CC

= +5V, V
= +5V, V
= +5V, V

= -80V, R

BAT

= -48V, R

BAT

= -24V, R

BAT

= ∞ - 300 - mW

LOOP

= ∞ - 150 - mW

LOOP
LOOP

= 600Ω,

- 280 - mW

IL = 25mA

I

CC

I

BAT

VCC = +5V, V

= +5V, V

V

CC

V

= +5V, V

CC

VCC = +5V, VB- = -80V, R

= +5V, VB- = -48V, R

V

CC

V

= +5V, VB- = -24V, R

CC

= -80V, R

BAT

= -48V, R

BAT

= -24V, R

BAT

= ∞ -36mA

LOOP

= ∞ -25mA

LOOP

= ∞ - 1.9 4 mA

LOOP

= ∞ - 3.6 7 mA

LOOP

= ∞ - 2.6 6 mA

LOOP

= ∞ - 1.8 4 mA

LOOP

UNCOMMITTED OP AMP PARAMETERS

Input Offset Voltage - ±5-mV
Input Offset Current - ±10 - nA
Differential Input Resistance (Note 3) - 1 - MΩ
Output Voltage Swing (Note 3) R

= 10kΩ - ±3-V

L

P-P

Small Signal GBW (Note 3) - 1 - MHz

NOTES:

3. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial
design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification com­pliance.

4. For transhybrid circuit as shown in Figure 3.

5. Application limitation based on maximum switch hook detect limit and metallic currents. Not a part limitation.

64

HC5517B

TF

TIP

SENSE

RING

SENSE 1

RING

SENSE 2

RF

R

2R

-

+

2R

25K

-

+

25K

R
R

R/2

R/20

TA

RA

90K

TF

25

14

15

16

26

-

+

100K
100K
100K

100K

R
R
R
R

4.5K

4.5K

RF

90K
90K

-

+

V

RX

17 12

+2V

OUT 1

VB/2

REF

SHD

RTD

V

RING

13 24 19 2

FAULT

DET

GM

-

+

-

+

-IN 1

OP AMP

V

TX

THERM

LTD

RF2

V

CC

BIAS

NETWORK

SH

TSD

GK

RFC

AGND

IIL LOGIC INTERFACE

1

22

BGND

27

V

BAT

4

F1

5

F0

6

RS

9

TST

7

SHD

8

RTD

10

ALM

21

RDO

R = 108kΩ

3

V

REF

18

NU

HC5517B DEVICE TRUTH TABLE

F1 F0 STATE

0 0 Loop power Denial Active
0 1 Power Down Latch RESET, Power on

RESET
10RD Active (unbalanced ringing)
1 1 Normal Loop feed

The truth table for the internallogic of the HC5517B is provided
in the above table. This family of ringing SLICs can be config­ured to support traditional unbalanced ringing and through
SLIC balanced ringing. The device operating states used by
through SLIC ringing applications are loop power denial and
normal feed. During loop power denial, the tip and ring amplifi­ers are disabled (high impedance) and the DC voltage of each
amplifier approaches ground. The SLIC will not provide current
to the subscriber loop during this mode and will not detect loop
closure. Voice transmission occurs during the normalloop feed
mode. During normal loop feed the SLIC is completely opera­tional and performs all transmission and supervisory functions.

20

RDIRTI

I

LIMIT

11

28

Power Dissipation

Careful thermal design is required to guarantee that the
maximum junction temperature of 150

o

C of the device is not
exceeded. The junction temperature of the SLIC can be
calculated using:

TJTAθJAICCV

Where T

is maximum ambient temperature and θJAis

A

CCIBATVBATILOOP

()2R

•()–+()+=

LOOP

(EQ. 1)

junction to air thermal resistance (and is package depen­dent). The entire term in parentheses yields the SLIC power
dissipation. The power dissipation of the subscriber loop
does not contribute to device junction temperature and is
subtracted from the power dissipation term. Operating at

o

85

C, the maximum PLCC SLIC power dissipation is 1.18W.

Likewise, the maximum SOIC SLIC power dissipation is

0.92W.

65

HC5517B

Circuit Operation and Design Information

SLIC DESIGN EQUATIONS

FUNCTION EQUATION DEFINITION OF TERMS

2-Wire to 4-Wire Gain V

4-Wire To 2-wire Gain V2W = Voltage Across 2-Wire Load

4-Wire To 4-wire Gain V

Loop Current Limit Programming I

Impedance Matching Z2W = 2-Wire Impedance

V

------------------- 2–

OUT1

V

RX

V

OUT1

-------------------

V

V

2W

------------ 2–
V

RX

I

LIMIT

R

ZO

–

2W



⋅=




Z



---------------------------------- -

⋅⋅⋅=



Z2WZ



0.6()R

------------------------------------------------- -=

()

KZ2W100–()⋅=

R

K 200 2⋅⋅=

RF

Through SLIC Ringing

The HC5517B uses linear amplification to produce the ringing
signal. As a result the ringing SLIC can produce sinusoid,
trapezoid or square wave ringing signals. Regardless of the
wave shape, the ringing signal is balanced. The balanced
waveform is another way of saying that the tip and ring DC
potentials are the same during ringing.

R

200



---------- -



Z

---------------------------------- -

Z2WZ

2W

+

200xR

ZO

----------- -

⋅=

R

2w

RF

Z

2W

+

SLIC

200

----------- -

Z

SLIC

IL1RIL2

2W

+()

IL2

R

ZO

----------- -

R

RF

Crest Factor Programming

As previously mentioned, a single resistor is required to set
the crest factor of the trapezoidal waveform. The only design
variable in determining the crest factor is the battery voltage.
The battery voltage limits the peak signal swing and there­fore directly determines the crest factor.

A set of tables will be provided to allow selection of the crest

= SLIC 4-wire Output

OUT1

V2w = Voltage across 2-wire load
Z2W = 2-Wire Impedance

VRX = SLIC 4-Wire Input
Z2W = 2-Wire Impedance
Z

= SLIC Synthesized Impedance

SLIC

= SLIC 4-Wire Output

OUT1

VRX = SLIC 4-Wire Input
Z2W = 2-Wire Impedance
Z

= SLIC Synthesized Impedance

SLIC

= Programmed Loop Current Limit

LIMIT

R

= Programming Resistor

IL1

R

= Programming Resistor

IL2

K = 100

factor setting resistor. The tables will include crest factors

Trapezoidal Ringing

The trapezoidal ringing waveform provides a larger RMS

below the Bellcore minimum of 1.2 since many ringing SLIC
applications are not constrained by Bellcore requirements.

voltage to the handset. Larger RMS voltages to the handset
provide more power for ringing and also increase the loop
length supported by the ringing SLIC.

One set of component values will satisfy the entire ringing
loop range of the SLIC. A single resistor sets the open circuit
RMS ringing voltage, which will set the crest factor of the ring­ing waveform. The crest factor of the HC5517B ringing wave­form is independent of the ringing load (REN) and the loop
length. Another robust feature of the HC5517B ringingSLIC is

TABLE 1. CREST FACTOR PROGRAMMING RESISTOR FOR

V

= -80V

BAT

RTRAP CF RMS RTRAP CF RMS

0Ω 1.10 65.0 825Ω 1.25 57.6
389Ω 1.15 62.6 964Ω 1.30 55.4
640Ω 1.20 60.0 1095Ω 1.35 53.3

the ring trip detector circuit. The suggested values for the ring
trip detector circuit cover quite a large range of applications.

The RMS voltage listed in the table is the open circuit RMS
voltage generated by the SLIC.

The assumptions used to design the trapezoidal ringing
application circuit are listed below:

• Loop current limit set to 25mA.

• Impedance matching is set to 600Ω resistive.

• 2-wire surge protection is not required.

• System able to monitor

RTD and SHD.

Logic ringing signal is used to drive RC trapezoid network.

TABLE 2. CREST FACTOR PROGRAMMING RESISTOR FOR

V

= -75V

BAT

RTRAP CF RMS RTRAP CF RMS

0Ω 1.10 60.9 1010Ω 1.25 53.7
500Ω 1.15 58.3 1190Ω 1.30 51.6
791Ω 1.20 55.9 1334Ω 1.35 49.7

66

HC5517B

TABLE 3. CREST FACTOR PROGRAMMING RESISTOR FOR

V

= -65V

BAT

RTRAP CF RMS RTRAP CF RMS

0Ω 1.10 52.5 1330Ω 1.25 45.9

660Ω 1.15 49.8 1600Ω 1.30 44.1

1040Ω 1.20 47.8 1800Ω 1.35 42.5

TABLE 4. CREST FACTOR PROGRAMMING RESISTOR FOR

V

= -60V

BAT

RTRAP CF RMS RTRAP CF RMS

0Ω 1.10 48.2 1460Ω 1.25 42.0

740Ω 1.15 45.6 1760Ω 1.30 40.4

1129Ω 1.20 43.7 2030Ω 1.35 38.8

The voltages listed in the tables are driven from a logic
source that will not drive the ringing input negative. If the
ringing input is driven negative by 200mV, the peak-to-peak
ringing amplitudes can be increased.

Ringing Voltage Limiting Factors

As the load impedance decreases (increasing REN), the
source impedance of the SLIC during ringing slightly
attenuates the ringing signal.

If additional surge protection resistance must be used with
the trapezoidal circuit, the loop length performance of the
circuit will decrease proportionally to the added resistance
in the Tip and Ring leads. For example if 30Ω protection
resistors is used in each of the Tip and Ring leads, the ring­ing loop length will decrease by a total of 60Ω.

Low Level Ringing Interface

The trapezoidal application circuit only requires a cadenced
logic signal applied to the wave shaping RC network to
achieve ringing. When not ringing, the logic signal should be
held low. When the logic signal is low, Tip will be near
ground and Ring will be near battery. When the logic signal
is high, Tip will be near battery and Ring will be near ground.

Loop Detector Interface

The

RTD output should be monitored for off hook detection

during the ringing period. At all other times, the

SHD should
be monitored for off hook detection. The application circuit
can be modified to redirect the ring trip information through
the

SHD interface. The change can be made by rewiring the
application circuit, adding a pullup resistor to pin 23 and set­ting F0 low for the entire duration of the ringing period. The
modifications to the application circuit for the single detector
interface are shown in Figure 1.

SLIC Operating State During Ringing

HC5517B

NU 23

RDI 20

RDO 21

V

RING

24

ADDITIONAL PULL UP RESISTOR

V

CC

R

TRAP

V

D

TRAP

C

TRAP

RING

FIGURE 1. APPLICATIONCIRCUIT WIRING FOR SINGLE

LOOP DETECTOR INTERFACE

(DUAL DETECTOR INTERFACE)

MODE

F1

F0

V

RING

VALID DET

MODE

F1

F0

V

RING

VALID DET

ACTIVE

(LOGIC HI)

(LOGIC HI)

SHD

(SINGLE DETECTOR INTERFACE)

ACTIVE

(LOGIC HI)

(LOGIC HI)

SHD

RINGING

RTD

RINGING

SHD

ACTIVE

SHD

ACTIVE

SHD

FIGURE 2. DETECTOR LOGIC INTERFACES

Additional Application Information

Transhybrid Balance

Since the receive signal and its echo are 180 degrees out of
phase, the summing node of an operational amplifier can be
used to cancel the echo. Nearly all CODECs have an inter­nal amplifier for echo cancellation. The circuit in Figure 3
shows the cancellation amplifier circuit.

R

F

-

+

VO

V

V

RX

OUT1

R

A

R

B

The SLIC control pin F1 should always be a logic high during
ringing. The control pin F0 will either be a constant logic high
(two detector interface) or a logic low (single detector
interface). Figure 2 shows the control interface for the dual
detector interface and the single detector interface.

67

FIGURE 3. TRANSHYBRID AMPLIFIER CIRCUIT

HC5517B

When the SLIC is matched to a 600Ω load and only the sense
resistors are used, the 4-wire to 4-wire gain is equal to 5/12 as
predicted by the design equations. Therefore, by configuring
the transhybrid amplifier with a gain of 2.4 in the echo path,
cancellation can be achieved. The f ollo wing equations:

R





V

–=



O



V

RX

F

------- -

+



R



A

V

Substituting the fact that V

R





V

–=



O



V

RX

F

------- -

–



R



A

V

R



------- -



OUT1

R



OUT1

5





------

–

RX





12

F
B

is -5/12 of V

R



F

------- -



R



B

(EQ. 2)

RX

(EQ. 3)

Since cancellation implies that under these conditions, the
output V
solve for R

R

B

should be zero, set Equation 2 equal to zero and

O

.

B

R

A

------- -=

2.4

(EQ. 4)

Another outcome of the transhybrid gain selection is the
2-wire to 4-wire gain of the SLIC as seen by the CODEC.
The 5/12 voltage gain in the transmit path is relevant to the
receive input as well as any signals from the 2-wire side.
Therefore by setting the V

gain to 2.4 in the previous

OUT1

analysis, the 2-wire to 4-wire gain was set to unity.

Single Supply CODEC Interface

The majority of CODECs that interface to the ringing SLIC
operate from a single +5V supply and ground. Figure 4
shows the circuitry required to properly interface the ringing
SLIC to the single supply CODEC.

The CODEC signal names may vary from different manufac­turers, but the function provided will be the same. The DC
reference from the CODEC is used to bias the analog sig­nals between +5V and ground. The capacitors are required
so that the DC gain is unity for proper biasing from the
CODEC reference. Also, the capacitors block DC signals
that may interfere with SLIC or CODEC operation.

Layout Guidelines and Considerations

The printed circuit board trace length to all high impedance
nodes should be kept as shortas possible. Minimizing length
will reduce the risk of noise or other unwanted signal pickup.
The short lead length also applies to all high gain inputs. The
set of circuit nodes that can be categorized as such are:

•V

pin 27, the 4-wire voice input (low gain input).

RX

• -IN1 pin 13, the inverting input of the internal amplifier.

•V

•V
For multi layer boards, the traces connected to tip should not

cross the traces connected to ring. Since they will be carry­ing high voltages, and could be subject to lightning or surge
depending on the application, using a larger than minimum
trace width is advised.

The 4-wire transmit and receive signal paths should not
cross. The receive path is any trace associated with the V
input and the transmit path is any trace associated with V
output. The physical distance between the two signal paths
should be maximized to reduce crosstalk, or separated by a
ground trace.

The operating mode control signals and detector outputs
should be routed away from the analog circuitry. Though
the digital signals are nearly static, care should be taken to
minimize coupling of the sharp digital edges to the analog
signals.

pin 3, the noninverting input to ring feed amplifier.

REF

pin 24, the 20V/V input for the ringing signal.

RING

RX

TX

V

RX

V

OUT1

HC5517B

FIGURE 4. SINGLE SUPPLY CODEC INTERFACE

R

A

R

R

F

B

-

+

68

CODEC

+2.5V

RX OUT

TX IN

+

-

The part has two ground pins, one is labeled AGND and the
other BGND. Both pins should be connected together as
close as possible to the SLIC. If a ground plane is available,
then both AGND and BGND should be connected directly to
the ground plane.

A ground plane that provides a low impedance return path
for the supply currents should be used. A ground plane
provides isolation between analog and digital signals. If the
layout density does not accommodate a ground plane, a
single point grounding scheme should be used.

HC5517B

Pin Descriptions

PLCC SYMBOL DESCRIPTION

1 AGND Analog Ground - Serves as a reference for the transmit output and receive input terminals.
2VCCPositive Voltage Source - normally +5V DC.
3V
4 F1 Power Denial - An active low TTL compatible logic control input. When enabled, the output of the ring amplifier will

5 F0 TTL compatible logic control input that controls multiplexing of the detector outputs.
6 RS TTL compatible logic control input that must be tied high for proper SLIC operation.
7 SHD Switch Hook Detection - An active low TTL compatible logic output. Indicates an off-hook condition.
8 RTD Ring Trip Detection - An active low TTL compatible logic output. Indicates an off-hook condition when the phone is

9 TST A TTL logic input. A low on this pin will keep the SLIC in a power down mode. The TST pin, in conjunction with the

10 ALM A TTL compatible active low output which responds to the thermal detector circuit when a safe operating die

11 I
12 OUT1 The 4-wire output of the SLIC.
13 -IN1 The inverting input of the impedance matching amplifier. The non-inverting input is internally connected to AGND.
14 TIP SENSE An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor. Functions

15 RING SENSE 1 An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor.Functions

REF

LIMIT

An external voltage connected to this pin will override the internal V

ramp close to the output voltage of the tip amplifier.

ringing. May be used to indicate ring trip or ground key detection.

ALM pin, can provide thermal shutdown protection for the SLIC. Thermal shutdown is implemented by a system
controller that monitors the ALM pin. When the ALM pin is active (low), the system controller issues a command to
the TST pin (low) to power down the SLIC. The timing of the thermal recovery is controlled by the system controller.

temperature has been exceeded.
Loop Current Limit - used with VTX to set the short loop current limiting conditions.

with the RING terminal to receive voice signals and for loop monitoring purpose.

with the TIP terminal to receive voice signals and for loop monitoring purposes.

/2 reference.

BAT

16 RING SENSE 2 This is an internal sense mode that must be tied to RING SENSE 1 for proper SLIC operation. Also used during

unbalanced ringing.

17 V

18 NU Not used in this application. This pin should be left floating.
19 V

20 RDI TTL compatible input to drive the ring relay driver during unbalanced ringing.
21 RDO Open collector relay driver used during unbalanced ringing.
22 BGND Battery Ground - All loop current and some quiescent current flows from this terminal.
23 NU Not used in this application. This pin should be either grounded or left floating.
24 V
25 TF Output of the tip line feed amplifier.
26 RF Output of the ring line feed amplifier.
27 V
28 RTI Ring Trip Input - This pin is connected to the external negative peak detector output for ring trip detection.

RX

TX

RING

BAT

Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearingat this input drive the Tip Feed
and Ring Feed amplifiers differentially.

A low impedance analog voltage output which is proportional to the subscriber loop current. Since the DC level of
this output varies with loop current, capacitive coupling to IN1- is necessary.

Low level ringing signal input.

The negative battery source, all loop current flows into this terminal.

69

HC5517B

Pinouts

HC5517B (PLCC)

TOP VIEW

RS

SHD

RTD

TST

ALM

I

LIMIT

F0

REF

V

3

VCCAGND

12

F1

4

5
6
7

8

9
10
11

12

13

14

15

-IN 1

OUT 1

TIP SENSE

RING SENSE 1

BAT

RTI

V

27

28

17

16

RX

V

RING SENSE 2

RF

26

TF

25

V

24

RING

NU

23
22

BGND

RDO

21

RDI

20

V

19

TX

18

NU

Trapezoidal Ringing Application Circuit

AGND

V

CC

V

REF

RS
SHD
RTD

TST

ALM

I

LIMIT

OUT 1

-IN 1

TIP SENSE

F1
F0

1

1
2

2
3

3
4

4
5

5
6

6
7

7
8

8
9

9

10

10
11

11
12

12
13

13
14

14

HC5517B (SOIC)

TOP VIEW

28

28

RTI

27

27

V

BAT

26

26

RF

25

25

TF

24

24

V

RING

NU

23

23

BGND

22

22

RDO

21

21
20

20

RDI
V

19

19

TX

NU

18

18
17

17

V

RX

16

16

RING SENSE 2

15

15

RING SENSE 1

TIP

RING

V

CC

V

BAT

TST

F1
F0

U1

14

S1

TIP SENSE

25

TF

26

RF

16

RING SENSE 2

15

RING SENSE 1

2

V

CC

15

AGND

22

BGND

27

V

BAT

4

F1

5

F0

6

RS

9

20

RDI

R

R

S2

C

PS1

C

PS2

V

CC

I

LIMIT

OUT1

V

RING

V

SHD
RTD
ALMTST

V

RX

V

-IN1

RTI

REF

TX

17

R

RT3

IL2

R

IL1

C

AC

R

RF

R

ZO

R

RT2

11

19

13

12

28

R

24

D

TRAP

C

IL

3

7
8

10

HC5517B

C

RX

V-REC

V-XMIT

R

RT1

D

RT

R

C

RT

TRAP

TRAP

V

RING

C

SHD
RTD

ALM

70

FIGURE 5. TRAPEZOIDAL RINGING APPLICATION CIRCUIT

HC5517B

HC5517B Trapezoidal Ringing Application Circuit Parts List

COMPONENT VALUE TOLERANCE RATING COMPONENT VALUE TOLERANCE RATING

U1 - Ringing SLIC HC5517B N/A N/A R

RS1, R

RZO, R

R

RT1

R

RT2

R

RT3

R

RF

S2

IL1

49.9Ω 1%

56.2kΩ 1%

49.9kΩ 1%

1.5MΩ 1%

51.1kΩ 1%

45.3kΩ 1%

1

/2WR

1

/8WC

1

/8WCIL, CRT, CAC, C

1

/8WC

1

/8WDRT, D

1

/8W

IL2

TRAP

PS1

TRAP

, C

PS2

TRAP

7.68kΩ 1%

User-Defined 1%

0.1µF 10% 100V

0.47µF 10% 50V

RX

4.7µF 10% 10V

1N914 Generic Rectifier Diode

1

1

/8W

/8W

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by descriptiononly.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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