Datasheet HC5503PRC Datasheet (Intersil Corporation)

HC5503PRC

Data Sheet December 1999

Low Cost SLIC For Large Telecom
Switches

The HC5503PRC is a low cost SLIC optimized for large
Telecom switches. It combines a flexible voltage feed
architecture with the Intersil latch-free DI bonded wafer
process, to provide a low component count, carrier class
solution at very low cost. The re-configurable design permits
simple, economical solutions for campus-wide call center
and PBX applications. External components can be used in
conjunction with the high battery voltage capability to meet
the complex impedance and long loop drive requirements of
Central Office switches, worldwide.

Ordering Information

TEMP.

PART NUMBER

HC5503PRCM 0 to 70 28 Ld PLCC N28.45
HC5503PRCB 0 to 70 24 Ld SOIC M24.3

RANGE (oC) PACKAGE

PKG.

NO.

File Number 4806

Features

• Wide Operating Battery Range (-40V to -58V)

• Single Additional +5V Supply

• 30mA Short Loop Current Limit

• Ring Relay Driver

• Switch Hook and Ring Trip Detect

• Low On-Hook Power Consumption

• On-Hook Transmission

• ITU-T Longitudinal Balance Performance

• Loop Power Denial Function

• Thermal Protection

• Supports Tip, Ring or Balanced Ringing Schemes

• Low Profile SO and PLCC Surface Mount Packaging

Applications

Block Diagram

AGND
BGND

DGND

RD

RFS

C

TIP

TF

RING

RF

V

BAT

V

CC

• Central Office, PBX, Call Centers

• Related Literature

- AN571, Using Ring Sync with HC-5502A and HC-5504
SLICs

RING RELAY

DRIVER

RING TRIP

BIAS

DETECTOR

2-WIRE

INTERFACE

LOOP CURRENT

DETECTOR

THERMAL LIMIT

2

4-WIRE

INTERFACE
VF SIGNAL

PATH

LOGIC

INTERFACE

TX

RX

SHD

RS
RC

PD

C1
OUT

+

-

+IN

-IN

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

| Copyright © Intersil Corporation 1999

HC5503PRC

Absolute Maximum Ratings (Note 1) Thermal Information

Maximum Continuous Supply Voltages

(VB-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5V

(VB+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7V

(VB+ - VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V

Relay Drive Voltage (VRD). . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V

Operating Conditions

Operating Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 70oC

Relay Driver Voltage (VRD) . . . . . . . . . . . . . . . . . . . . . . . .5V to 12V

Positive Supply Voltage (VB+) . . . . . . . . . . . . . . . . . . 4.75V to 5.25V

Negative Supply Voltage (VB-). . . . . . . . . . . . . . . . . . . .-40V to -58V

High Level Logic Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V

Low Level Logic Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V

Subscriber Loop Resistance . . . . . . . . . . . . . . . . . . . 200Ω - 1800Ω

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied.

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 2) θJA (oC/W)

24 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

28 Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

(PLCC and SOIC - Lead Tips Only)

Die Characteristics

Transistor Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185

Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 x 102

Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected

Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Bipolar-DI

Electrical Specifications Unless Otherwise Specified, V

- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP= 50Ω, RS = 100Ω, Typical

B

Parameters. TA = 25oC. Min-Max Parameters are Over Operating Temperature Range

PARAMETER CONDITIONS MIN TYP MAX UNITS

On Hook Power Dissipation I
Off Hook Power Dissipation RL = 600Ω, I
On Hook IB+R
Off Hook IB+R
On Hook IB-R
Off Hook IB-R
Off Hook Loop Current RL = 1800Ω (I
Off Hook Loop Current RL = 200Ω, I

= 0 (Note 4) - 113 - mW

LONG

= 0 (Notes 3, 4) - 750 - mW

LONG

= ∞, I

L

= 600Ω, I

L

= ∞, I

L

= 600Ω, I

L

= 0 - 1.4 - mA

LONG

= 0 - 2.8 - mA

LONG

= 0 - 2.2 - mA

LONG

= 0 - 31 - mA

LONG

= 0) 18 - - mA

LOOP

= 0 (Note 3) 25 30 35 mA

LONG

Fault Currents

TIP to Ground -27-mA
RING to Ground -55-mA
TIP to RING -30-mA
TIP and RING to Ground -69-mA

Ring Relay Drive V

OL

IOL = 62mA - 0.2 0.5 V
Ring Relay Driver Off Leakage VRD = 12V, RC = 1 = HIGH, TA = 25oC - - 100 µA
DC Ring Trip Threshold 8.1 10.8 13.5 mA
Switch Hook Detection Threshold 5.0 7.5 10 mA
Loop Current During Power Denial RL = 200Ω - 3.2 - mA
Dial Pulse Distortion (Note 4) 0 - 0.5 ms
Receive Input Impedance (Note 4) - 110 - kΩ
Transmit Output Impedance (Note 4) - 10 20 Ω

2

HC5503PRC

Electrical Specifications Unless Otherwise Specified, V

- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP= 50Ω, RS = 100Ω, Typical

B

Parameters. TA = 25oC. Min-Max Parameters are Over Operating Temperature Range (Continued)

PARAMETER CONDITIONS MIN TYP MAX UNITS

2-Wire Return Loss (Referenced to 600Ω + 2.16µF), RP= RS = 150Ω

SRL LO - 15.5 - dB
ER

L

(Note 4)

-24-dB

SRL HI -31-dB

Longitudinal Balance 1V

2-Wire Off Hook (Note 4) 53 58 - dB

200Hz - 3400Hz, (Note 4) IEEE Method

RMS

0oC ≤ TA≤ 75oC, RP= RS = 150Ω

2-Wire On Hook (Note 4) 53 58 - dB
4-Wire Off Hook 50 58 - dB

Insertion Loss At 1kHz, 0dBm Input Level, Referenced 600Ω,

2-Wire to 4-Wire, 4-Wire to 2-Wire - ±0.05 ±0.2 dB

Frequency Response 200-3400HzReferencedtoAbsoluteLossat1kHzand

RP=RS= 150Ω

- ±0.02 ±0.05 dB

0dBm Signal Level, RP= RS = 150Ω (Note 4)
Idle Channel Noise RP= RS = 150Ω (Note 4)

2-Wire to 4-Wire, 4-Wire to 2-Wire - 1 5 dBrnC

- -89 -85 dBm0p

Absolute Delay RP= RS = 150Ω (Note 4)

2-Wire to 4-Wire, 4-Wire to 2-Wire --2µs

Trans Hybrid Loss BalanceNetworkSet Up for 600Ω Termination at 1kHz,

30 40 - dB

RP= RS = 150Ω (Note 4)
Overload Level VB+ = +5V, RP= RS = 150Ω (Note 4)

2-Wire to 4-Wire, 4-Wire to 2-Wire 1.5 - - V

Level Linearity
2-Wire to 4-Wire, 4-Wire to 2-Wire (Note 4)

At 1kHz, (Note 4) Referenced to 0dBm Level,

RP= RS = 150Ω

PEAK

+3 to -40dBm - - ±0.05 dB

-40 to -50dBm - - ±0.1 dB

-50 to -55dBm - - ±0.3 dB

Power Supply Rejection Ratio RP= RS = 150Ω (Note 4)

VB+ to 2-Wire 15 - - dB

30 - 60Hz, RL = 600Ω

VB+ to Transmit 15 - - dB
VB- to 2-Wire 15 - - dB
VB- to Transmit 15 - - dB
VB+ to 2-Wire 200 - 16kHz, RL = 600Ω, RP= RS = 150Ω 30 - - dB
VB+ to Transmit 30 - - dB
VB- to 2-Wire 30 - - dB

VB- to Transmit 30 - - dB
Logic Input Current (RS, RC, PD) 0V ≤ VIN≤ 5V - - ±100 µA
Logic Inputs

Logic ‘0’ V

Logic ‘1’ V

IL
IH

- - 0.8 V

2.0 - 5.5 V

Logic Outputs

Logic ‘0’ V

Logic ‘1’ V

OL
OH

I

800µA, VB+ = 5V - 0.1 0.5 V

LOAD

I

40µA, VB+ = 5V 2.7 - 5.0 V

LOAD

3

HC5503PRC

Electrical Specifications Unless Otherwise Specified, V

Parameters. TA = 25oC. Min-Max Parameters are Over Operating Temperature Range (Continued)

PARAMETER CONDITIONS MIN TYP MAX UNITS

UNCOMMITTED OP AMP SPECIFICATIONS

Input Offset Voltage - ±5-mV
Input Offset Current - ±10 - nA
Input Bias Current -20-nA
Differential Input Resistance (Note 4) - 1 - MΩ
Output Voltage Swing RL = 10K, VB+ = 5V - ±3-V
Output Resistance A
Small Signal GBW (Note 4) - 1 - MHz

NOTES:

3. I

4. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial

= Longitudinal Current

LONG

design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification
compliance.

= 1 (Note 4) - 10 - Ω

VCL

- = -48V, VB+ = 5V, AG = BG = DG = 0V, RP= 50Ω, RS = 100Ω, Typical

B

PEAK

Pin Descriptions

28 PIN

PLCC

2 1 TIP An analog input connected to the TIP (more positive) side of the subscriber loop through a sense resistor

3 2 RING Ananalog input connected to the RING (more negative) side of the subscriber loop through a sense resistor

4 3 RFS Senses ring side of loop for ground key and ring trip detection. During ringing, the ring signal is inserted into

54V
65C

7 6 DG DigitalGround - To beconnected to zero potential and serves as a reference for alldigital inputs and outputs

9 7 RS Ring Synchronization Input - A TTL - compatible clock input. The clock should be arranged such that a

10 8
11 9 TF Tip Feed - A low impedance analog output connected to the TIP terminal through a sense resistor (R

12 10 RF Ring Feed - A low impedance analog output connected to the RING terminal through a sense resistor (R

13 11 V

14 12 BG Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into

16 13

17 14 NC Used during production test. Leave disconnected.

24 PIN

DIP/SOIC SYMBOL DESCRIPTION

) and a ring relay contact. Functions with the Ring terminal to receive voice signals from the telephone

(R

S

and for loop monitoring purposes.

) and a ring relay contact. Functions withthe Tip terminal toreceive voice signals from the telephone and

(R

S

for loop monitoring purposes.

the line at this node and RF is isolated from RFS via a relay.

+ Positive Voltage Source - Most positive supply. VB+ is typically.

B

Capacitor #1 - An external capacitor to be connected between this terminal and analog ground. Required

1

for proper operation of the loop current limiting function, and for filtering VB-. Typical value is 0.3µF, 30V.

on the SLIC microcircuit.

positive pulse transition occurs on the zero crossing of the ring voltage source, as it appears at the RFS
terminal. For Tip side injected systems, the RS pulse should occur on the negative going zero crossing and
for Ring injected systems, on the positive going zero crossing. This ensures that the ring relay activates and
deactivates when the instantaneous ring voltage is near zero. If synchronization is not required, the pin
should be tied to 5V.

RD Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized.

Functions with the RF terminal to provide loop current, feed voice signals to the telephone set, and sink
longitudinal current.

Functions with the TF terminal to provide loop current, feed voice signals to the telephone set, and sink
longitudinal current.

- Negative Voltage Source - Most negative supply. VB- is typically -48V with an operational range of -42V to

B

-58V. Frequently referred to as “battery”.

this ground terminal.

SHD Switch Hook Detection - A low active LS TTL - compatible logic output. This output is enabled for loop

currents exceeding the switch hook threshold.

).

S

).

S

4

HC5503PRC

Pin Descriptions (Continued)

28 PIN

PLCC

18 15 PD Power Denial - A low active TTL - Compatible logic input. When enabled, the ring feed voltage collapses to

19 16

20 17 NC Leave disconnected.
21 18 OUT The analog output of the spare operational amplifier.
23 19 -IN The inverting analog input of the spare operational amplifier.
24 20 +IN The non-inverting analog input of the spare operational amplifier.
25 21 RX Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive

26 22 C

27 23 AG Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX)

28 24 TX Transmit Output, Four Wire Side - A low impedance analog output proportional to the loop current.

1, 8, 15, 22 NC No internal connection.

NOTE: Allgrounds (AG,BG, and DG) mustbe applied before V
to run separate grounds off a line card, the AG must be applied first.

24 PIN

DIP/SOIC SYMBOL DESCRIPTION

the tip feed voltage (~4V). The DC feed is disabled, but the AC transmission is maintained. The switch hook
detect (SHD) is not necessarily valid, and the relay driver (RD) output is disabled.

RC Ring Command - Alow active TTL -Compatible logic input. Whenenabled, the relay driver (RD) output goes

low on the next high level of the ring sync (RS) input, as long as the SLIC is not in the power denial state
(PD = 0) or the subscriber is not already off- hook (SHD = 0).

coupling to this input is required. AC signals appearing at this input differentially drive the Tip feed and Ring
feed terminals.

Capacitor #2 - An external capacitor to be connected between this terminal and analog ground. This

2

capacitor is required for the proper operation of ring trip detection. Recommended value 0.82µF ±10% 10V
non-polarized.

and receive input (RX) terminals.

Transhybrid balancing must be performed beyond this output to completely implement two to four wire
conversion. This output is unbalanced and referenced to analog ground. Since the DC level of this output
varies with loop current, capacitive coupling to the next stage is essential.

+orVB-. Failureto do somayresult in prematurefailure of the part. If a user wishes

B

Functional Diagram

1/2 RING

TIP

2-WIRE

LOOP

RING

RING

VOLTAGE

RS: SENSE RESISTOR

: PROTECTION RESISTOR

R

P

RELAY

PROTECTION

VB-

VB-

RING SYNC

RING COMMAND

R

P

SECONDARY

1/2 RING

RELAY

R

P

POWER DENIAL

RFS

R

S

R

S

RING

TIP

V

PD

RS
RC
RD

BG

RF

TF

RING
TRIP

RING

CONTROL

-

B

BATTERY

FEED

LOOP

CURRENT

LIMITER

SLIC MICROCIRCUIT

MONITORING

+1

LINE

DRIVERS

-1

LOOP

DIFF
AMP

+

OP
AMP

SHD

SWITCH HOOK
DETECTION

TX

TRANSMIT
OUTPUT

OUT

+IN

+

-IN

RX

RECEIVE
INPUT

5

HC5503PRC

SLIC FUNCTIONAL SCHEMATIC

SOIC PIN NUMBERS SHOWN

TF

9

TIP

1

RING
FEED

SENSE

3

RING

2

RF

10

VB+

V

BAT

R

R
R
R

R

R

R
R
R

R

R

RING FEED

V

BAT

TIP FEED

I

B4

7

8

10
9

22

3

4

1

2

16

15

A-300

AMP

I

B5

21 22 11 12 23 6 4

BAT ANA DIG

BAT

GND GND GND

VOLTAGE AND CURRENT

BIAS NETWORK

A-400

RX C2

R

17

+

V

B2

V

IB1IB2IB3IB4IB5IB6IB7I

AMP

-

R

12

A-200
LONG’L
I/V AMP

I

B7

R

5

A-100
TRANSV’L
I/V AMP

V

I

B6

REFERENCE

VB+

VB+

BAT

R

R

20

V

BAT

R

6

14

R

18

R

19

V
R

VB+

BAT
23

-

+

QD3Q

VB+

R

-

D36

+

R

11

V

BAT

+

-

V

BAT/2

V

B2

21

VB+

VB+

B8

BAT

B10IB11

IB9I

V

RING TRIP DETECTOR

5V

V

+

I

SWITCH HOOK

DETECTOR

BAT

B8

V

VB+

+

I

Q

D27

LOAD CURRENT
LIMITING

B6

-

Q

D28

I

B2

V

-

+

B4

V

B1

B5

20 19 18

+ -

VB+

V

B1

V
V
V
V
5V

B2
B3
B4
B5

A-500
OP AMP

V

I

B3

5V

GK

GND SHORTS

CURRENT

LIMITING

I

B1

- +

V

B3

AND LOGIC

V

THERMAL

LIMITING

V

B5

BAT

INTERFA CE

SH

RFC

V

BAT

I

B10

STTL

BAT

OUT

VB+

NC

14

NC

17

SHD

13

RC

16

PD

15

R

13

V

BAT

V

BAT

TXC1 RS RD

87245

6

HC5503PRC

LOGIC GATE SCHEMATIC

GK

SH

TO

R

10

TTL

TO

STTL

21

LOGIC BIAS

5

11 14

6

A

B

C

SCHOTTKY LOGIC

8

97

DELAY

RELAY

DRIVER

3

12

13

STTL

C
B
A

TO

TTL

SHDRDPDRCRS

2

1

4

16

15

TTL

TO

STTL

TTL

TO

STTL

Surge Protection

The SLIC device, in conjunction with an external protection
bridge, will withstand high voltage lightning surges and
power line crosses.

The voltage withstand capability of pins ‘Tip’, ‘Ring’ and
‘RFs’ is ±450V with respect to ground, as shown in Table 1.

This device is intended for use with an appropriate
secondary protection circuit scheme.

The SLIC will withstand longitudinal currents up to a
maximum or 30mA
performance degradation.

RMS

, 15mA

per leg, without any

RMS

TABLE 1.

TEST

PARAMETER

Longitudinal
Surge

CONDITION

10µs Rise/
1000µs Fall

Metallic Surge 10µs Rise/

1000µs Fall

T/GND
R/GND

50/60Hz Current
T/GND
R/GND

10µs Rise/
1000µs Fall

11 Cycles
Limited to
10A

RMS

PERFORMANCE

(MAX) UNITS

±450 (Plastic) V

±450 (Plastic) V

±450 (Plastic) V

315 (Plastic) V

PEAK

PEAK

PEAK

RMS

7

HC5503PRC

Plastic Leaded Chip Carrier Packages (PLCC)

0.042 (1.07)

0.048 (1.22)
PIN (1) IDENTIFIER

0.020 (0.51) MAX
3 PLCS

C

L

D1

D

0.026 (0.66)

0.032 (0.81)

0.045 (1.14)
MIN

0.050 (1.27) TP

0.042 (1.07)

0.056 (1.42)

EE1

VIEW “A” TYP.

C

L

A1

A

0.013 (0.33)

0.021 (0.53)

0.025 (0.64)
MIN

0.004 (0.10) C

0.025 (0.64)

0.045 (1.14)

D2/E2

D2/E2

VIEW “A”

0.020 (0.51)
MIN

SEATING

-C-

PLANE

NOTES:

1. Controlling dimension: INCH. Converted millimeter dimensions are

not necessarily exact.

2. Dimensions and tolerancing per ANSI Y14.5M-1982.

3. Dimensions D1 and E1 do not include mold protrusions. Allowable

mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.

4. To be measured at seating plane contact point.

-C-

5. Centerline to be determined where center leads exit plastic body.

6. “N” is the number of terminal positions.

N28.45 (JEDEC MS-018AB ISSUE A)

28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

R

SYMBOL

A 0.165 0.180 4.20 4.57 -

A1 0.090 0.120 2.29 3.04 -

D 0.485 0.495 12.32 12.57 ­D1 0.450 0.456 11.43 11.58 3
D2 0.191 0.219 4.86 5.56 4, 5

E 0.485 0.495 12.32 12.57 -

E1 0.450 0.456 11.43 11.58 3
E2 0.191 0.219 4.86 5.56 4, 5

N28 286

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

Rev. 2 11/97

8

Small Outline Plastic Packages (SOIC)

HC5503PRC

N

INDEX
AREA

123

-A-

E

-B-

SEATING PLANE

D

A

-C-

0.25(0.010) BM M

H

L

h x 45

o

α

e

B

0.25(0.010) C AM BS

M

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension“D” does not includemold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter­lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.

5. Thechamfer on the body is optional. If it isnot present, avisual index
feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controllingdimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.

A1

C

0.10(0.004)

M24.3 (JEDEC MS-013-AD ISSUE C)

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A 0.0926 0.1043 2.35 2.65 -

A1 0.0040 0.0118 0.10 0.30 -

B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 ­D 0.5985 0.6141 15.20 15.60 3

E 0.2914 0.2992 7.40 7.60 4

e 0.05 BSC 1.27 BSC ­H 0.394 0.419 10.00 10.65 -

h 0.010 0.029 0.25 0.75 5

L 0.016 0.050 0.40 1.27 6
N24 247

o

α

0

o

8

o

0

o

8

Rev. 0 12/93

NOTESMIN MAX MIN MAX

-

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only.Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However,no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

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9

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