Page 1
Features
l Phase-Locked Loop Clock Distribution for
Synchronous DRAM Applications
l Supports PC-100 and Meets “PC100 SDRAM
registered DIMM Specification Rev. 1.2”
l Distributes One Clock Input to One Bank of Ten
Outputs
l No External RC Network Required
l External Feedback (FBIN) Pin is Used to
Synchronize the Outputs to the Clock Input
l Separate Output Enable for Each Output Bank
l Operates at 3.3 V Vcc
l 125 MHz Maximum Frequency
l On-chip Series Damping Resistors
l Support Spread Spectrum Clock(SSC)
Synthesizers
l ESD Protection Exceeds 3000 V per MIL-STD-
883, Method 3015 ; Exceeds 350 V Using
Machine Model ( C = 200 pF, R = 0 )
l Latch-Up Performance Exceeds 400 mA per
JESD 17
l Packaged in Plastic 24-Pin Thin Shrink Small-
Outline Package
Pin Configuration
TSSOP 24 PACKAGE
(TOP VIEW)
AGND
Vcc
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
Vcc
G
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK
AVcc
Vcc
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
Vcc
FBIN
HC2510C
HC2510C
General Description
The HC2510C is a low-skew, low jitter, phase-
locked loop(PLL) clock driver, distributing high
frequency clock signals for SDRAM.
The HC2510C operates at 3.3V Vcc and provides
integrated series-damping resistors that make it ideal
for driving point-to-point loads. The propagation delay
from the CLK input to any clock output is nearly zero.
Ten outputs provide low-skew and low-jitter clocks.
All outputs can be enabled or disabled via the control
input(G). Output signal duty cycles are adjusted to 50
percent, independent of the duty cycle at CLK.
The HC2510C is specially designed to interface with
high speed SDRAM applications in the range of
25MHz to 125MHz and includes an internal RC
network which provides excellent jitter characteristics
and eliminates the needs for external components.
For the test purpose, the PLL can be bypassed by
strapping AVcc to ground.
The HC2510C is characterized for operation from 0°C
to 85°C.
Function Table
INPUTS OUTPUTS
1Y
(0:9)
FBOUT
G CLK
X L L L
L H L H
H H H H
1
Page 2
Functional Block Diagram
11
G
HC2510C
3
4
5
8
9
15
16
17
1Y0
1Y1
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
CLK
FBIN
AV
20
1Y8
24
21
PLL
1Y9
13
12
FBOUT
2 3
CC
2
Page 3
Table 1. Pin Description
Pin Name
CLK 24 I
FBIN 13 I
G 11 I
FBOUT 12 O
1Y(0:9)
AVcc 23 Power
AGND 1
Vcc 2,10,14,22 Power Power Supply
GND 6,7,18,19
Table 2. Absolute Maximum Ratings Over Operating Free-air
Symbols
Pin No. Type
3,4,5,8,9
15,16,17,20,2
1
O
Ground Analog Ground. AGND provides the ground reference for the
Groun
d
Temperature Range
Parameter Value Unit Conditions
Functional Description
Clock Input. CLK provides the reference signal to the internal
PLL.
Feedback Input. FBIN provides the feedback signal to the
internal PLL.
Output Bank Enable. When G is high, all outputs 1Y(0:9) are
enabled.
When G is low, Outputs 1Y(0:9) are disable to a logic-low
state.
Feedback Output. FBOUT completes the feedback loop of the
PLL by being wired to FBIN.
Clock Outputs. These outputs provide low-skew copies of
CLKIN. Each output has an embedded series-damping
resistor.
Analog Power Supply. AVcc provides the power reference for
the analog circuitry. AVcc can be also used to bypass the PLL
for the test purpose. When AVcc is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
analog circuitry.
Ground
HC2510C
Vcc Supply Voltage Range -0.5 to 4.6 V
VI Input Voltage Range -0.5 to 6.5 V
Vo
IIK Input Clamp Current ±50 mA VI <0 or V I >Vcc
IOK Output Clamp Current ±50 mA Vo<0 or Vo >Vcc
Io Continuous Output Current ±50 mA Vo =0 to Vcc
P
MAX
T
stg
Voltage Range applied to any
input in the high or low state
Maximum Power Dissipaiton
Storage Temperature Range
-0.5 to Vcc+0.5
0.7 W
- 65 to 150 °C
V
3
Page 4
Table 3. Recommended Operating Conditions
HC2510C
Value
Min Max
Unit Condition
Symbol
Parameter
AVCC Supply Voltage 3 3.6 V
VIH High-level Input Voltage 2 V
VIL Low-level Input Voltage 0.8 V
VI Input Voltage 0 V
V
CC
IOH High-level Output Current -12 mA
IOL Low-level Output Current 12 mA
TA Operating Free-air Temperature
0 85 °C
Table 4. Electrical Characteristics Over Recommended Operating Free-air
Temperature Range
Symbol
Min Typ Max
VIK -1.2 V 3 I
VOH
VOL
Vcc-0.2
2.1 3 IOH = -12 mA
2.4
0.2 Min to Max
0.8 3 IOL = 12 mA
0.55
II ±5 µA 3.6 V
ICC 10 µA 3.6
∆
I
500 µA 3.3 to 3.6
CC
Ci 4 pF 3.3 V
Co 6 pF 3.3 V
Value
Min to Max
Unit AVCC (V)
V
V
Test Conditions
= -18mA
I
IOH = -100µA
3 IOH = -6 mA
I
=100 mA
OL
3 IOL = 6 mA
=VCC or GND
I
VI =VCC or GND, IO = 0,
Ouputs: low or high
One input at VCC - 0.6V,
Other Inputs at VCC or GND
= VCC or GND
I
= VCC or GND
O
Table 5.Timing Requirements Over Recommended Ranges of Supply Voltage
and Operating free-air Temperature
Symbol
f
Clock Frequency 25 125 MHz
clock
Parameter
Min Max
Value
Input Clock Duty Cycle 40 60 %
Stabilization Time♣ 1 ms
♣ Time to obtain phase lock of its feedback signal to its reference signal.
Unit
4
Page 5
Voltage Waveforms
Table 6. Switching Characteristics Over Recommended Ranges of Supply
Voltage and Operating Free-air Temperature. (CL=30pF) =
VCC = 3.3V
From(Input) TO(Output)
tphase error ♣
tsk Any Y of FBOUT
Jitter(pk-pk)
Duty
Cycle
tr
tf
=These parameters are not production tested.
♣ Phase error does not include jitter.
66MHz < CLKIN↑<
100MHz
CLKIN↑ = 100MHz
CLKIN > 66MHz
CLKIN > 66MHz
FBIN↑ 150
FBIN↑ -50
Any Y or
FBOUT
Any Y or
FBOUT
Any Y or
FBOUT
Any Y or
FBOUT
Any Y or
FBOUT
Figure 1. Load Circuit and Voltage Waveforms
±0.165V
Min Typ Max Min Typ Max
150 ps
50
200 ps
-100 100 ps
45
1.3 1.9 0.8 2.1 ns
1.7 2.5 1.2 2.7 ns
HC2510C
VCC =
3.3V±0.3V Parameter
ps
55 %
Unit
50% V
From Output Under Test
30pF 500
Input
§Ù
Output
tpd
0.4V 0.4V
tr tf
CC
2V 2V
50% V
CC
Load Circuit For Outputs
Propagation Delay Times
Notes: 1. All input pulses are supplied by generators having
the following characteristics: PRR ≤ 100MHz, Zo
=50Ω, tr =1.2ns, tf=1.2ns
2.The outputs are measured one at a time with one
transition per measurement.
5
3V
0V
V
V
OH
OL
Page 6
Figure 2. Phase Error and Skew Calculation
CLKIN
FBIN
t
phase error
FBOUT
tSK
tSK
HC2510C
6
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