Datasheet HAF70009 Datasheet (Intersil Corporation)

HAF70009

Data Sheet August 1999

56A, 100V, 0.025 Ohm, N-Channel
UltraFET Power MOSFET

This N-Channel power MOSFET is
manufactured using the innovative
UltraFET™process. This advanced

process technology achieves the
lowest possible on-resistance per silicon area, resulting in
outstanding performance. This device is capable of
withstanding high energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was designed for use in applications where power
efficiency is important, such as switching regulators,
switching converters, motor drivers, relay drivers, low­voltage bus switches, and power management in portable
and battery-operated products.

Formerly developmental type TA75639.

Ordering Information

PART NUMBER PACKAGE TEMP. RANGE (oC)

HAF70009 TO-220AB -55 to 175

File Number

Features

• 56A, 100V

• Simulation Models

- Temperature Compensated PSPICE

® and SABER

Electrical Models

- Spice and Saber Thermal Impedance Models

- www.intersil.com

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

4770

©

Packaging

JEDEC TO-220AB

SOURCE

DRAIN

GATE

DRAIN

(FLANGE)

Absolute Maximum Ratings T

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain Current

Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, T

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Tech Brief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. TJ = 25oC to 150oC.

= 25oC, Unless Otherwise Specified

C

DSS

DGR

GS

DM

AS

STG

pkg

HAF70009 UNITS

100 V
100 V
±20 V

D

D

L

56

Figure 4

Figures 6, 14, 15

200

1.35

-55 to 175

300
260

A

W

W/oC

o

C

o

C

o

C

4-1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

http://www.intersil.comor 407-727-9207 | Copyright© Intersil Corporation 1999. SABERis a Copyright of Analogy,Inc.

UltraFET™ is a trademark of Intersil Corporation. PSPICE® is a registered trademark of MicroSim Corporation.

HAF70009

Electrical Specifications T

= 25oC, Unless Otherwise Specified

C

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain to Source Breakdown Voltage BV
Zero Gate Voltage Drain Current I

Gate to Source Leakage Current I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

THERMAL SPECIFICATIONS

Thermal Resistance Junction to Case R
Thermal Resistance Junction to Ambient R
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charge Q
Gate Charge at 10V Q
Threshold Gate Charge Q
Gate to Source Gate Charge Q
Reverse Transfer Capacitance Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

DSSID

DSS

VDS = 90V, VGS = 0V - - 1 µA
VDS = 80V, VGS = 0V, TC = 150oC - - 250 µA

GSS

GS(TH)VGS

DS(ON)ID

θJC
θJA

ON

VGS = ±20V - - ±100 nA

(Figure 3) - - 0.74
TO-220 - - 62

VDD = 50V, ID≅ 56A,
RL = 0.89Ω, VGS= 10V,

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(10)

g(TH)

ISS

RGS = 5.1Ω
(Figures 18,19)

r

f

VGS = 0V to 10V - 57 75 nC
VGS = 0V to 2V - 3.7 4.5 nC

gs

gd

VDS = 25V, VGS = 0V,
f = 1MHz

OSS

RSS

(Figure 12)

= 250µA, VGS = 0V (Figure 11) 100 - - V

= VDS, ID = 250µA (Figure 10) 2 - 4 V

= 56A, VGS = 10V (Figure 9) - 0.021 0.025 Ω

o

C/W

o

C/W

- - 110 ns

-15- ns

-60- ns

-20- ns

-25- ns

- - 70 ns

= 0V to 20V VDD = 50V,

- 110 130 nC
ID≅ 56A,
RL = 0.89Ω
I

= 1.0mA

g(REF)

(Figures 13, 16, 17)

- 9.8 - nC

-24-nC

- 2000 - pF

- 500 - pF

-65-pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Voltage V
Reverse Recovery Time t
Reverse Recovered Charge Q

4-2

SD

rr

RR

ISD = 56A - - 1.25 V
ISD = 56A, dISD/dt = 100A/µs - - 110 ns
ISD = 56A, dISD/dt = 100A/µs - - 320 nC

Typical Performance Curves

HAF70009

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

125 175

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWERDISSIPATION vs CASE

TEMPERATURE

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

60

50

40

30

20

, DRAIN CURRENT (A)

D

I

10

0

25 50 75 100 125 150 175

T

, CASE TEMPERATURE (oC)

C

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

0.1

, NORMALIZED

θJC

Z

THERMAL IMPEDANCE

0.01

-5

10

1000

100

, PEAK CURRENT (A)

DM

I

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

10

-5

10

SINGLE PULSE

-4

10

-3

10

-2

10

t, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

TC = 25oC

VGS = 10V

-4

10

-3

10

t, PULSE WIDTH (s)

-2

10

10

NOTES:
DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z

-1

10

FOR TEMPERATURES
ABOVE 25
CURRENT AS FOLLOWS:

-1

I = I

P

DM

θJC

0

10

o

C DERATE PEAK

25

0

10

2

x R

175 - T

150

θJC

t

1

t

2

+ T

C

1

10

C

1

10

4-3

FIGURE 4. PEAK CURRENT CAPABILITY

HAF70009

Typical Performance Curves

1000

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE
LIMITED BY r

1

1 10 100 200

DS(ON)

VDS, DRAIN TO SOURCE VOLTAGE (V)

V

DSS(MAX)

(Continued)

TJ = MAX RATED

T

= 100V

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

100

80

60

= 20V

V

GS

V

= 20V

GS

VGS = 10V

VGS = 10V

= 7V

V

= 7V

V

GS

GS

= 25oC

C

100µs

1ms

10ms

VGS = 6V

300

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

100

STARTING T

, AVALANCHE CURRENT (A)

AS

I

10

0.001 0.01 0.1 1

= 150oC

J

tAV, TIME IN AVALANCHE (ms)

- VDD)

DSS

- VDD) +1]

DSS

STARTING TJ = 25oC

NOTE: Refer to Intersil Application Notes AN9321 and AN9322.

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY

100

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

80

60

= 15V

V

DD

175oC

40

, DRAIN CURRENT (A)

D

I

20

0

01234567

VDS, DRAIN TO SOURCE VOLTAGE (V)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

T

= 25oC

C

VGS = 5V

40

, DRAIN CURRENT (A)

D

I

20

25oC

0

0 1.5 3.0 4.5 6.0 7.5

VGS, GATE TO SOURCE VOLTAGE (V)

FIGURE 7. SATURATION CHARACTERISTICS FIGURE 8. TRANSFER CHARACTERISTICS

3.0

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

2.5

VGS = 10V, ID = 56A

2.0

1.5

1.0

ON RESISTANCE

0.5

NORMALIZED DRAIN TO SOURCE

0

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

1.2

1.0

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.6

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

-55oC

VGS = VDS, ID = 250µA

FIGURE 9. NORMALIZED DRAIN TOSOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

4-4

FIGURE 10. NORMALIZED GATETHRESHOLD VOLTAGEvs

JUNCTION TEMPERATURE

HAF70009

Typical Performance Curves

1.2
ID = 250µA

1.1

1.0

BREAKDOWN VOLTAGE

NORMALIZED DRAIN TO SOURCE

0.9

-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)

(Continued)

FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

10

8

6

3000

2500

2000

1500

1000

C, CAPACITANCE (pF)

500

0

0 102030405060

VDS, DRAIN TO SOURCE VOLTAGE (V)

C

C

C

ISS

OSS

RSS

VGS= 0V, f = 1MHz

= CGS + C

C

ISS

C

= C

RSS

C

≈ C

OSS

GD

DS

GD

+ C

GD

FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

4

WAVEFORMS IN
DESCENDING ORDER:

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

0

0 102030405060

VDD = 50V

Qg, GATE CHARGE (nC)

ID = 56A

= 37A

I

D

I

= 18A

D

NOTE: Refer to Intersil Application Notes AN7254 and AN7260.

FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT

4-5

HAF70009

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS

V

I

G(REF)

DS

R

L

V

GS

+

V

DD

-

DUT

V

DD

VGS= 2V

0

I

g(REF)

0

V

GS

Q

g(TH)

Q

gs

t

P

I

AS

t

AV

Q

g(TOT)

V

DS

Q

g(10)

VGS = 10V

Q

gd

V

DS

V

DD

VGS= 20V

FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM

V

DS

R

L

V

GS

+

V

DD

-

V

DS

0

DUT

R

GS

V

GS

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

t

10%

r

PULSE WIDTH

FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. RESISTIVE SWITCHING WAVEFORMS

4-6

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

HAF70009

PSPICE Electrical Model

SUBCKT HUF75639 2 1 3 ; rev Oct. 98

CA 12 8 2.8e-9
CB 15 14 2.65e-9
CIN 6 8 1.9e-9

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 110
EDS 14 8 5 8 1

DPLCAP

10

RSLC2

EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

IT 8 17 1
LDRAIN 2 5 2e-9

LGATE 1 9 1e-9
LSOURCE 3 7 0.47e-9

RLGATE 1 9 10

GATE

1

LGATE

RLGATE

RGATE

9

20

ESG

EVTEMP
+

18
22

-

6
8

EVTHRES

+

+

6

-

RLDRAIN 2 5 20
RLSOURCE 3 7 4.69

MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.3e-2
RGATE 9 20 0.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 4.5e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

CA

S1A

12

13

8

S1B

EGS EDS

S2A

14
13

S2B

13

+

+

6
8

-

-

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*115),4))}
.MODEL DBODYMOD D (IS = 1.4e-12 RS = 3.3e-3 XTI = 4.7 TRS1 = 2e-3 TRS2 = 0.1e-5 CJO = 3.3e-9 TT = 6.1e-8 M = 0.7)

.MODEL DBREAKMOD D (RS = 3.5e-1 TRS1 = 1e-3 TRS2 = 1e-6)
.MODEL DPLCAPMOD D (CJO = 2.2e-9 IS = 1e-30 N = 10 M = 0.95 vj = 1.0)
.MODEL MMEDMOD NMOS (VTO = 3.5 KP = 4.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u Rg = 0.7)
.MODEL MSTROMOD NMOS (VTO = 3.97 KP = 56.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO =3.11 KP = 0.085 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 7 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 0.8e-3 TC2 = 1e-6)
.MODEL RDRAINMOD RES (TC1 = 1e-2 TC2 = 1.75e-5)
.MODEL RSLCMOD RES (TC1 = 2.8e-3 TC2 = 14e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -2.0e-3 TC2 = -1.75e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.75e-3 TC2 = 0.05e-9)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.0 VOFF = -3.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.5 VOFF = -6.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF = 4.95)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 4.95 VOFF = -2.5)

.ENDS

5

RSLC1

51

+

5

ESLC

51

-

50

RDRAIN

16

21

-

19

8

MSTRO

CIN

15

CB

8

14

+

5
8

-

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

11

+

17
18

-

7

RLSOURCE

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

DBODY

LSOURCE

VBAT

DRAIN

2

SOURCE

3

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

4-7

HAF70009

SABER Electrical Model

nom temp=25 deg c 100v Ultrafet

REV Oct. 98
template huf75639 n2,n1,n3

electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is=1.4e-12, xti=4.7, cjo=33e-10,tt=6.1e-8, m=0.7)
d..model dbreakmod = ()
d..model dplcapmod = (cjo=22e-10,is=1e-30,n=10,m=0.95, vj=1.0)
m..model mmedmod = (type=_n,vto=3.5,kp=4.8,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=3.97,kp=56.5,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=3.11,kp=0.085,is=1e-30, tox=1)
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6.0,voff=-3.5)
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-6.0)
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2.5,voff=4.95)
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=4.95,voff=-2.5)

c.ca n12 n8 = 28.5e-10
c.cb n15 n14 = 26.5e-10
c.cin n6 n8 = 19e-10

GATE

d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbreakmod
d.dplcap n10 n5 = model=dplcapmod

LGATE

1

RLGATE

9

RGATE

EVTEMP
+

20

i.it n8 n17 = 1
l.ldrain n2 n5 = 2.0e-9

l.lgate n1 n9 = 1e-9
l.lsource n3 n7 = 4.69e-10

S1A

12

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=0.8e-3,tc2=-1e-6

S1B

CA

res.rdbody n71 n5 = 3.3e-3, tc1=2.0e-3, tc2=0.1e-5
res.rdbreak n72 n5 = 3.5e-1, tc1=1e-3, tc2=1e-6
res.rdrain n50 n16 = 13e-3, tc1=1e-2,tc2=1.75e-5
res.rgate n9 n20 = 0.7
res.rldrain n2 n5 = 20
res.rlgate n1 n9 = 10
res.rlsource n3 n7 = 4.69
res.rslc1 n5 n51 = 1e-6, tc1=2.8e-3,tc2=14e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 4.5e-3, tc1=0,tc2=0
res.rvtemp n18 n19 = 1, tc1=-2.75e-3,tc2=0.05e-9
res.rvthres n22 n8 = 1, tc1=-2e-3,tc2=-1.75e-5

spe.ebreak n11 n7 n17 n18 = 110
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1
equations {

i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/115))** 4))
}
}

10

RSLC2

-

6

ESG

8

+

6

-

18
22

S2A

13

14

8

13

S2B

13

+

+

6

EGS EDS

8

-

-

DPLCAP

EVTHRES

+

19

8

15

CB

CIN

-

+

5
8

-

5

RSLC1

51

50
RDRAIN

21

MSTRO

14

ISCL

16

8

MMED

RDBREAK

72

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

LDRAIN

RLDRAIN

RDBODY

71

DBODY

+

17
18

-

LSOURCE

7

RLSOURCE

RVTEMP
19

DRAIN

2

SOURCE

3

-

VBAT

+

22

4-8

Spice Thermal Model

HAF70009

REV APRIL 1998

HUF75639

CTHERM1 TH 6 5.0e-3
CTHERM2 6 5 1.9e-2
CTHERM3 5 4 7.95e-3
CTHERM4 4 3 9.0e-3
CTHERM5 3 2 2.95e-2
CTHERM6 2 TL 12.55

RTHERM1 TH 6 5.04e-3
RTHERM2 6 5 1.25e-2
RTHERM3 5 4 3.54e-2
RTHERM4 4 3 1.98e-1
RTHERM5 3 2 2.99e-1
RTHERM6 2 TL 3.97e-2

Saber Thermal Model

Saber thermal model HUF75639
template thermal_model th tl

thermal_c th, tl
{
ctherm.ctherm1 th 6 = 5.0e-3
ctherm.ctherm2 6 5 = 1.9e-2
ctherm.ctherm3 5 4 = 7.95e-3
ctherm.ctherm4 4 3 = 9.0e-3
ctherm.ctherm5 3 2 = 2.95e-2
ctherm.ctherm6 2 tl = 12.55

RTHERM1

RTHERM2

RTHERM3

RTHERM4

TH

JUNCTION

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

rtherm.rtherm1 th 6 = 5.04e-3
rtherm.rtherm2 6 5 = 1.25e-2
rtherm.rtherm3 5 4 = 3.54e-2
rtherm.rtherm4 4 3 = 1.98e-1
rtherm.rtherm5 3 2 = 2.99e-1
rtherm.rtherm6 2 tl = 3.97e-2
}

RTHERM5

RTHERM6

TL

CTHERM5

2

CTHERM6

CASE

4-9

TO-220AB

3 LEAD JEDEC TO-220AB PLASTIC PACKAGE

HAF70009

ØP

Q

D

E

1

L

1

E

H

1

D

1

b

1

A

A

1

SYMBOL

A 0.170 0.180 4.32 4.57 -

A

1

TERM. 4

o

45

b 0.030 0.034 0.77 0.86 3, 4

b

1

c 0.014 0.019 0.36 0.48 2, 3, 4

D 0.590 0.610 14.99 15.49 -

D

1

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

0.048 0.052 1.22 1.32 -

0.045 0.055 1.15 1.39 2, 3

- 0.160 - 4.06 -

E 0.395 0.410 10.04 10.41 -

L

o

60

1

e

1

b

c

E

1

- 0.030 - 0.76 -

e 0.100 TYP 2.54 TYP 5

3

2

e

J

1

e

1

H

1

J

1

0.200 BSC 5.08 BSC 5

0.235 0.255 5.97 6.47 -

0.100 0.110 2.54 2.79 6

L 0.530 0.550 13.47 13.97 -

L

1

0.130 0.150 3.31 3.81 2

ØP 0.149 0.153 3.79 3.88 -

Q 0.102 0.112 2.60 2.84 -

NOTES:

1. These dimensions are within allowable dimensions of Rev.J of
JEDEC TO-220AB outline dated 3-24-87.

2. Lead dimension and finish uncontrolled in L1.

3. Lead dimension (without solder).

4. Add typically 0.002 inches (0.05mm) for solder coating.

5. Position of lead to be measured 0.250 inches (6.35mm) from bot­tom of dimension D.

6. Position of lead to be measured 0.100 inches (2.54mm) from bot­tom of dimension D.

7. Controlling dimension: Inch.

8. Revision 2 dated 7-97.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with­out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rightsof third parties which may result
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