Page 1
FEATURES
• operation beyond 622Mb/s
• accepts SMPTE and PECL input levels
• fully differential signal path
• on-chip PECL current loads eliminate need for
external pull-down resistors
• capable of driving 100Ω differential loads
• very low 500mW power consumption
• additional expansion port input for construction of
larger matrices
• auxiliary monitoring output
• easy to configure
• double latched address inputs with separate load and
configure
• TTL/CMOS compatible control logic inputs
• single 5V power supply
APPLICATIONS
Serial digital video switching; datacom or telecom
switching.
™
GX9533
GENLINX
II
Serial Digital 8x9 Crosspoint
DATA SHEET
DESCRIPTION
The GX9533 is a high speed 8x9 serial digital crosspoint.
An expansion input port eases the design of larger
switching matrices by reducing PCB layers and eliminating
the need for cascaded secondary switching. Decode logic
and double level latching to configure the matrix are
included on chip. Separate LOAD and CONFIGURE inputs
allow for asynchronous configuration and synchronous
switching. These latches can also be made transparent for
asynchronous switching by pulling the LOAD and
CONFIGURE pins high.
In the power saving (PS) mode, the GX9533 has a very low
power consumption of 500mW. This is accomplished by
driving a 400mV output swing into the on-chip 200Ω
differential load termination in the expansion port of the next
GX9533. This architecture provides a significant power
savings and the elimination of external load resistors or
impedance matching resistors. In applications where
standard PECL levels are necessary, the GX9533 can be
configured in "PECL Mode", to drive 800mV p-p into a 100Ω
differential load. The power consumption in this mode
increases to 860mW.
GX9533
AUX IN
EXP0..7
IN0 .. 7
CONFIG
LOAD
LOAD A
OA0..2
IA0..3
ORDERING INFORMATION
PART NUMBER PACKAGE TEMPERATURE
GX9533-CQY 100 pin MQFP Tray 0°C to 70°C
GX9533-CTY 100 pin MQFP Tape 0°C to 70°C
STD/PECL2
STD/PECL1
2
16
16
INPUT
BUFFER
3
4
SWITCHING
MATRIX
CONFIG
LATCH
LOAD
LATCH
DECODE
LOGIC
2
16
OUTPUT
BUFFER
V
CCO
16
OUT 0..7
2
AUX
V
EE
V
CC
BLOCK DIAGRAM
Revision Date: August 1999 Document No. 521 - 41 - 03
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Page 2
ABSOLUTE MAXIMUM RATINGS
PARAMETER VALUE
Supply Voltage (V
= VCC-VEE)5.5V
S
Input Voltage Range (any input) -0.3 to (V
Power Dissipation 975mW
Operating Temperature Range 0°C to 70°C
Storage Temperature Range -65°C to +150°C
GX9533
Lead Temperature Range (soldering, 10 sec) 260°C
DC ELECTRICAL CHARACTERISTICS
VCC = 5V, VEE = 0V, TA = 0 to 70°C unless otherwise shown.
PARAMETER CONDITION MIN TYP MAX UNITS
Supply Voltage 4.75 5.0 5.25 V
ECL Input Voltage Swing 200 800 1200 mV p-p
ECL Common Mode Input Voltage Range with 1200mV input signal swing 2500 - V
Logic Input Voltage High 2.0 - V
Low 0 - 0.8 V
POWER SAVE 1 MODE
R
= 4k
Ω
SET
PARAMETER CONDITION MIN TYP MAX UNITS
CC
+0.3)V
-600 mV
CC
CC
V
Supply Current R
Output Common Mode Voltage V
= 100
L
Ω
- 115 150 mA
-1200 - VCC-800 mV
CC
Output Voltage Swing 300 450 600 mV
Output Voltage High V
Low V
-950 - VCC-600 mV
CC
-1400 - VCC-1000 mV
CC
POWER SAVE 2 MODE
R
= 6k
Ω
SET
PARAMETER CONDITION MIN TYP MAX UNITS
Supply Current R
Output Common Mode Voltage V
Output Voltage Swing 300 450 600 mV
Output Voltage High V
Low V
= 200
L
Ω
- 100 130 mA
-1200 - VCC-800 mV
CC
-950 - VCC-600 mV
CC
-1400 - VCC-1000 mV
CC
521 - 41 - 03
2
Page 3
PECL MODE
R
= 2k
Ω
SET
PARAMETER CONDITION MIN TYP MAX UNITS
Supply Current R
Output Common Mode Voltage V
= 100
L
Ω
- 170 185 mA
-1450 - VCC-1050 mV
CC
Output Voltage Swing 700 800 900 mV
Output Voltage High V
Low V
-1200 - VCC-650 mV
CC
-1850 - VCC-1450 mV
CC
AC ELECTRICAL CHARACTERISTICS
VCC = 5.0V, VEE = 0V, TA = 0 to 70°C unless otherwise shown.
PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS
Maximum Input Data Rate For 90% eye opening - 850 - Mb/s
Additive Jitter Standard
Input
Expansion
Input
Data In to Data Out
Delay
Standard
Input
Expansion
Input
Propagation Delay
Match
Standard
Input
t
DLY
143 to 622 Mb/s, all hostile
- 80 - ps p-p
crosstalk
- 70 - ps p-p
Average of all channels - 1.7 - ns
-1.1- ns
- 350 - ps
GX9533
Expansion
- 250 - ps
Input
CONFIGURE to Data
Main Out t
CD
-10-ns
Out Delay
AUX Out - 11 - ns
LOAD/LOADA Pulse Width t
CONFIGURE Pulse Width t
IA
to LOAD/LOADA High Setup Time t
N
LOAD/LOADA to IA
to LOAD High Setup Time t
OA
N
LOAD to OA
Low Hold Time t
N
Low Hold Time t
N
LOAD High to CONFIGURE High t
LP
CP
ILS
ILH
OLS
OLH
LC
20 - - ns
20 - - ns
30 - - ns
0--ns
30 - - ns
0--ns
0--ns
Output Rise/Fall Time - 700 - ps
NOTE
1. Use RMS addition to calculate additive jitter through cascaded devices.
3
521 - 41 - 03
Page 4
PIN CONNECTIONS
EXP0
EXP0
EXP1
EXP1
EXP2
EXP2
V
CC
IN0
IN0
V
GX9533
EE
IN1
IN1
V
EE
IN2
IN2
V
EE
IN3
IN3
V
EE
IN4
IN4
V
EE
IN5
IN5
V
EE
IN6
IN6
V
EE
IN7
IN7
V
EE
V
EE
V
CC
V
EE
OUT0
OUT0
EXP3
CC
EXP3
V
GX9533
TOP VIEW
EXP4
EXP4
EXP5
EXP5
EXP6
EXP6
EXP7
EXP7
AUX_IN
AUX_IN
STD/PECL2
STD/PECL1
NC
NC
LOAD
NC
NC
LOADA
NC
NC
CNFG
NC
NC
IA0
NC
NC
IA1
NC
NC
IA2
NC
NC
IA3
NC
NC
OA0
OA1
OA2
V
EE
AUX_OUT
AUX_OUT
OUT1
OUT1
CCO
V
OUT2
OUT2
CCO
V
OUT3
OUT3
CCO
V
OUT4
OUT4
CCO
V
OUT5
OUT5
CCO
V
OUT6
OUT6
CCO
V
OUT7
OUT7
PIN DESCRIPTIONS
SYMBOL TYPE DESCRIPTION
IN0 to IN7, IN0
OUT0 to OUT7, OUT0
AUX_OUT, AUX_OUT
AUX_IN, AUX_IN
to IN7 I Differential data inputs.
to OUT7 O Differential data outputs.
O Auxiliary port output.
I Auxiliary port input.
OA0 to OA2 I Output address select.
IA0 to IA3 I Input address select.
LOAD I Loads input & output address.
LOADA I Loads auxiliary input address.
STD/ECL1, STD/ECL2 Resistor connection for Power Save mode or PECL mode. Refer to Table 3.
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521 - 41 - 03
Page 5
PIN DESCRIPTIONS
SYMBOL TYPE DESCRIPTION
CNFG I Switch configuration.
EXP0 to EXP7, EXP0
V
CC
V
CCO
V
EE
Standard
Inputs
to EXP7 I Expansion port inputs.
Positive power supply.
Positive power supply (PECL outputs).
Negative power supply.
0
1
2
3
4
5
6
7
INPUT BUFFERS
0
1
2
3
4
5
6
7
4x1
Switch
4x1
Switch
Expansion
Inputs
1
0
3
2
3x1
Switch
7
6
5
4
8
Auxilliary
Input
GX9533
7
6
5
4x1
4
Switch
3
2
1
4x1
0
Switch
3x1
Switch
Auxilliary
Output
7
6
5
4
Main
3
Outputs
2
1
0
Fig. 1 Data Flow Diagram
100
90
80
70
% OPENING
60
50
700 800 900 1000 1100
BIT RATE (Mb/s)
Fig. 2 Typical Eye Opening vs. Bit Rate
5
521 - 41 - 03
Page 6
DETAILED DESCRIPTION
DIFFERENTIAL INPUTS
The inputs to the GX9533 will accept both SMPTE 259M as
well as PECL input levels. The fully differential data path
provides low jitter data rates of up to 700Mb/s.
The main inputs (IN0..7) and expansion inputs (EXP0..7) are
normally connected to a biased differential data source.
The GX9533 inputs are not self biased, so unused inputs
should be connected as shown in Figure 3 or Figure 4.
GX9533
V
CC
IN
x
GX9533
IN
x
1k
Fig. 3 Preferred Termination Of Unused Inputs
V
CC
IN
X
GX9533
NC
IN
X
TABLE 1: Output Address Selection
OA2 0A1 0A0 OUTPUT PORT
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
TABLE 2: Input Source Address Selection
IA3 IA2 IA1 IA0
00000
00011
00102
00113
INPUT
PORT
Fig. 4 Alternate Termination of Unused Inputs
Terminating the inputs as shown in Figure 3 will provide the
highest noise immunity, since there is no possibility of noise
coupling into the unconnected input pin.
I/O ADDRESS SELECTION
The GX9533 has a versatile LOAD/CONFIGURE
architecture which simplifies IN/OUT switch configuration.
An output is normally connected to an input by a two stage
process:
Stage One: Loading The Configuration Into Latches
1. The output address is selected on the OA pins as
shown in Table 1.
2. The input address is selected on the IA pins as shown in
Tab le 2 .
3. A LOAD pulse then transfers the output and input
addresses into the GX9533 LOAD latch.
The above three steps can be repeated up to eight times in
order to configure the latch for all eight outputs.
During step 3 above, if the LOADA pulse is also strobed,
the latch is configured to connect the selected input to the
ninth, auxiliary output.
01004
01015
01106
01117
10XXEXP
1 1 X X Quiet
Mode
Note that a QUIET mode is available as shown in Table 2. In
QUIET mode, the outputs are latched in a DC state with
OUT
= 1 and OUTX = 0.
X
Stage Two: Configuring The Matrix
A CONFIGURE strobe is applied to transfer the contents of
the LOAD latch into the CONFIG latch. This action will
cause the data flow through the GX9533 to be switched to
the new configuration. Refer to Figure 6 for detailed timing
information.
Note that any single output can be asynchronously
switched by having LOAD (or LOADA if desired) held high
while CONFIG is strobed.
521 - 41 - 03
6
Page 7
OUTPUT LEVEL SELECT
A single resistor, R
, is used to set the amplitude of all
SET
differential outputs. Table 3 shows the value of R
output drive capability.
SET
vs
USING THE GX9533 TO EXPAND LARGER MATRICES
The GX9533 pin-out and architecture provides a number of
advantages over other crosspoint switches in the area of
switching matrix board layout.
TA B L E 3 : R
R
SET
SET
vs V
OUT
V
(mV) OUTPUT R
OUT
L
2k 800 100 PECL
4k 450 100 Power Save 1
6k 450 200 Power Save 2
IN0 to IN7
IN0 to IN7
t
DLY
OUT0 to OUT7
OUT0 to OUT7
Fig. 5 GX9533 Data Latency
OA
, IA
N
N
t
LP
LOAD/LOADA
CONFIGURE
t
t
OLS
ILS
t
ILH
t
OCH
t
CP
t
LC
MODE
GX9533
INPUTS 8-15
GX9533
INPUTS 0-7
OUTPUTS 0-7
GX9533
GX9533
OUTPUTS 8-15
Fig. 9 Crosspoint Matrix Expansion - 16x16 Crosspoint Matrix
BUS THROUGH™ PIN CONNECTIONS
To easily facilitate a switching matrix design where inputs
can be bussed across a matrix of crosspoint devices,
Gennum's crosspoint device has "NC" pins opposite the
input pins as shown by the dotted lines in the pin-out
diagram above. This design allows bussing of inputs
without having to use "vias" to get below the top layer of the
printed circuit board.
GX9533
Fig. 6 LOAD/LOADA and Configure Timing
CONFIGURE
t
CD
OUT 0 TO OUT 7
OUT 0 TO OUT 7
Fig. 7 Configure to Data Out Delay
R
SET
STD/ECL2
GX9533
Fig. 8 GX9533 R
STD/ECL1
Connection
SET
EXPANSION PORT INPUT
The expansion inputs provide the following benefits:
• by not having to run traces from the outputs of the
crosspoint switch to a common output bus, crosstalk
between output channels can be greatly reduced.
• fewer circuit board layers are required because the
outputs of each device simply line up
• there are no transmission line effects caused by
connecting High-Z outputs to an output bus
• because the output signal is being routed from the top
of the switching matrix to the bottom through the
devices, inputs can be simply bussed across the board
without having to worry about input/output crosstalk.
7
521 - 41 - 03
Page 8
PACKAGE DIMENSIONS
GX9533
18.85
0.65 BSC
23.90
20.0
±0.25
±0.10
REF
0.30
±0.08
12.35
2.80
REF
±0.25
14.0
±0.10
3.30 MAX
17.90
±0.25
12˚ TYP
0.13 MIN.
RADIUS
1.95
REF
100 pin MQFP
Dimensions in millimeters
0.75 MIN
0˚-7˚
0.80
0.30 MAX RADIUS
0˚- 7˚
±0.10
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make
changes at any time to improve reliability, function or design, in order to
provide the best product possible.
GENNUM CORPORATION
MAILING ADDRESS:
P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
SHIPPING ADDRESS:
970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement.
521 - 41 - 03
REVISION NOTES:
Changes to document format.
GENNUM JAPAN CORPORATION
C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku
Tokyo 168-0081, Japan
Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839
GENNUM UK LIMITED
Centaur House, Ancells Bus. Park, Ancells Rd, Fleet, Hants, England GU13 8UJ
Tel. +44 (0)1252 761 039 Fax +44 (0)1252 761 114
© Copyright April 1995 Gennum Corporation. All rights reserved. Printed in Canada.
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