Datasheet GTLP6C816APMTCX, GTLP6C816APMTC, GTLP6C816AMTCX, GTLP6C816AMTC Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS500179 www.fairchildsemi.com

August 1998
Revised August 1999

GTLP6C816A LVTTL-to-GTLP Clock Driver

GTLP6C816A
LVTTL-to-GTLP Clock Driver

General Description

The GTLP6C816A is a clo ck driv er th at pro vide s LVTTL to
GTLP signal level translation (and vice versa). T he device
provides a high speed interface between cards operating at
LVTTL logic levels and a backplane opera ting at GTL(P)
logic levels. High speed backplane operation is a direct
result of GTL(P)’s reduced output swing (<1V), reduced
input threshold levels and outp ut edge rate control. The
edge rate control minimiz es bus settling time. GTLP is a
Fairchild Semiconducto r derivative of the Gunning Trans­ceiver logic (GTL) JEDEC standard JESD8-3.

Fairchild’s GTL(P) has internal edge-rate control and is
process, voltage, and temperature (PVT) compensated. Its
function is similar to BTL and GT L but with different outp ut
levels and receiver threshold. GTLP output LOW level is
typically less than 0. 5V, the output level HIGH is 1.5V and
the receiver threshold is 1.0V.

Features

■ Interface between LVTTL and GTLP logic levels

■ Edge Rate Control to minimize noise on the GTLP port

■ Power up/down high impedance for live insertion

■ 1:6 fanout clock driver for LVTTL port

■ 1:2 fanout clock driver for GTLP port

■ LVTTL compatible driver and control inputs

■ Flow through pinout optimizes PCB layout

■ Open drain on GTLP to support wired-or connection

■ A Port source/sink −24/+24 mA

■ B Port sink 50 mA

■ −40°C to +85°C temperature capability

■ Low voltage version of GTLP6C816

Ordering Code:

Pin Descriptions Connection Diagram

Order Number Package Number Package Description

GTLP6C816AMTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

TTLIN, GTLPIN Clock Inputs

(LVTTL and GTLP respectively)

OEB

Output Enable (Active LOW)
GTLP Port (LVTTL Levels)

OEA

Output Enable (Active LOW)
TTL Port (LVTTL Levels)

V

CCT

.GNDT TTL Output Supplies

V

CC

Internal Circuitry V

CC

GNDG OBn GTLP Output Grounds
V

REF

Voltage Reference Input

OA0–OA5 TTL Buffered Clock Outputs
OB0–OB1 GTLP Buffered Clock Outputs

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GTLP6C816A

Functional Description

The GTLP6C816A is a clock driver providing LVTTL-to-GTLP clock translation, and GTLP-to-LVTTL clock translation in the
same package. The LVTTL-to-GTLP di rection is a 1: 2 clock driv er path wi th a single E nable pin (OE B

). For the GTLP-to-

LVTTL direction the clock receiver path is a 1:6 buffer with a single Enable control (OEA

). Data polarity is inverting for both

directions.

Truth Tables

Logic Diagram

Inputs Outputs

TTLIN OEB

OBn

HL L
LL H
X H High Z

Inputs Outputs

GTLPIN OEA

OAn

HL L
LL H
X H High Z

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GTLP6C816A

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

(Note 3)

Note 1: Absolute Maximum continuous ratings are those values beyond
which damage t o the device ma y occur. Exposure to t hese condition s or
conditions beyon d those indicated m ay adversely affect dev ice reliability.
Functional operation under absolute maximum rated conditions is not
implied.

Note 2: I

o

Absolute Maximum Rating must be observed.

Note 3: Unused inputs must be held High or Low.

Supply Voltage (VCC) −0.5V to +4.6V
DC Input Voltage (V

I

) −0.5V to +4.6V

DC Output Voltage (V

O

)
Outputs 3-STATE −0.5V to +4.6V
Outputs Active (Note 2) −0.5V to +4.6V

DC Output Sink Current into

OA-Port I

OL

48 mA

DC Output Source Current

from OA-Port I

OH

−48 mA

DC Output Sink Current into

OB-Port in the LOW State I

OL

100 mA

DC Input Diode Current (I

IK

)

V

I

< 0V −50 mA

DC Output Diode Current (I

OK

)

V

O

< 0V −50 mA

V

O

> V

CC

+50 mA
ESD Rating > 2000V
Storage Temperature (T

STG

) −65°C to +150°C

Supply Voltage V

CC

3.15V to 3.45V

Bus Termination Voltage (V

TT

)
GTLP 1.47V to 1.53V
GTL 1.14V to 1.26V
V

REF

0.98V to 1.02V

Input Voltage (V

I

) on INA-Port

and Control Pins 0.0V to 3.45V

HIGH Level Output Current (I

OH

)

OA-Port −24 mA

LOW Level Output Current (I

OL

)
OA-Port +24 mA
OB-Port +50 mA

Operating Temperature (T

A

) −40°C to +85°C

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GTLP6C816A

DC Electrical Characteristics

Over Recommended Operating Free-Air Temperature Range, V

REF

= 1.0V (unless otherwise noted).

Note 4: All typical va lues are at VCC = 3.3V and TA = 25°C.
Note 5: GTLP V

REF

and VTT are specified to 2% tolera nce sinc e sign al inte grity an d no ise ma rgin can be sign ificant ly de grade d if th ese sup pli es are noisy.

In addition, V

TT

and R

TERM

can be adjus t ed to accommo date backplane im pedances other t han 50Ω, within the boun da ries of no t exce edi ng the DC Abs o-

lute I

OL

ratings. Similarly V

REF

can be adjusted to com pensate for changes in VTT.

Symbol Test Conditions Min

Typ

(Note 4)

Max Units

V

IH

GTLPIN V

REF

+0.05 V

TT

V

Others 2.0 V

V

IL

GTLPIN 0.0 V

REF

−0.05 V

Others 0.8 V

V

REF

(Note 5) GTLP 1.0 V
VTT (Note 5) GTLP 1.5 V
V

IK

VCC = 3.15V II = −18 mA −1.2 V

V

OH

OAn-Port VCC = 3.15V IOH = −100 µAV

CC

−0.2
VIOH = −18 mA 2.4

I

OH

= −24 mA 2.2

V

OL

OAn-Port VCC = 3.15V IOL = 100 µA0.2

VIOL = 18 mA 0.4

I

OL

= 24 mA 0.5

V

OL

OBn-Port VCC = 3.15V IOL = 100 µA0.2

VIOL = 40 mA 0.4

IOL = 50 mA 0.55

I

I

TTLIN/ VCC = 3.45V VI = 3.45V 5

µA

Control Pins VI = 0V −5
GTLPIN VCC = 3.45V VI = V

TT

5

µA

VI = 0 −5

I

OFF

TTLIN VCC = 0V

I

or VO = 0V to 3.45V 30 µA

GTLPIN VCC = 0V

I

or VO = 0V to V

TT

30 µA

I

PU/PD

OAn or OBn Ports VCC = 0 to 1.5V

OE = Don’t Care

30 µA

I

OZH

OAn-Port VCC = 3.45V VO =3.45V 5

µA

OBn-Port VO = 1.5V 5

I

OZL

OAn-Port VCC = 3.45V VO = 0 −5 µA

I

CC

OAn or VCC = 3.45V Outputs HIGH 5.5 10
OBn Ports Outputs LOW 5 10 mA

VI = VCC or GND Outputs Disabled 5.5 10

∆I

CC

TTLIN VCC = 3.45V VI = VCC−0.6 2 mA

C

I

Control Pins/GTLPIN/TTLIN VI = VCC or 0 4.5

pFC

O

OAn-Port VI = VCC or 0 6.0
OBn-Port VI = VCC or 0 8.0

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GTLP6C816A

AC Electrical Characteristics

Over recommended range of supply voltage and operating free air temperature. V

REF

= 1.0V (unless otherwise noted).

CL = 30 pF for OBn-Port and CL = 50 pF for OAn-Port.

Note 6: All typical value s are at VCC = 3.3 V and TA = 25°C.

Extended Electrical Characteristi cs

Over recommended ranges of supply voltage and operating free-air temperature V

REF

= 1.0V (unless otherwise noted).

CL = 30 pF for B Port and CL = 50 pF for A Port

Note 7: All typical value s are at VCC = 3.3 V and TA = 25°C.
Note 8: t

OSHL/tOSLH

and t

OST

– Output-to-Output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs

within the same packaged device. T he specifications a re given for specif ic w orst case V

CC

and temperature and apply to any outputs switching in the same

direction dither HIGH -to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

) or in opposite direct ions both HL and LH (t

OST

). This parameter is guaranteed by desi gn and

statistical process dis tributio n. Actua l skew v alues be tween t he GTLP outputs could vary on the backplan e due to t he loadin g and imp edanc e seen by t he
device.

Note 9: t

PS

– Pin or Transition skew is defined as the difference between the LOW-to-HIGH transition and the HIGH-to-LOW tra ns it ion on the same pin. The

parameter is me as ured across all the outputs of the s ame chip is spec if ied for a specific w orst case V

CC

and temperature. This paramet er is guaranteed by

design and statistical pro cess distribu tion. Actu al skew values between the GTL P outputs coul d vary on the bac kplane due to the loading and imp edance
seen by the device.

Note 10: t

PV

– Part-to-Part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device-to-device.

The parameter is specified for a specific worst case V

CC

and temperature. This parameter is guaranteed by design and statistical process distribution. Actual
skew values between the GTLP output cou ld v ary on the backplane du e t o th e loading and impeda nc e s een by the device.
Note 11: Due to the open drain structure on GTLP outputs t

OST

and t

PV(LH)

in the A-to-B direction are not specified. Skew on these paths is dependent on the

V

TT

and RT values on the backplane.

Symbol From (Input) To (Output) Min

Typ

(Note 6)

Max Units

f

TOGGLE

TTLIN OBn 175

MHz

GTLPIN OAn 175

t

PLH

TTLIN OBn 1.3 2.3 4.0 ns

t

PHL

0.9 2.6 4.3

t

PLH

OEB OBn 1.5 2.6 4.1 ns

t

PHL

1.2 2.5 4.1

t

RISE

Transition Time, OB Outputs (20% to 80%) 1.3 ns

t

FALL

Transition Time, OB outputs (20% to 80%) 1.3

t

RISE

Transition Time, OA outputs (10% to 90%) 1.2 ns

t

FALL

Transition Time, OA outputs (10% to 90%) 2.0

t

PZH

, t

PZL

OEA OAn 0.5 2.9 4.8 ns

t

PLZ

, t

PHZ

0.5 2.4 4.4

t

PLH

GTLPIN OAn 1.9 3.6 5.7 ns

t

PHL

2.1 3.5 5.3

Symbol

From To

Min

Typ

Max Unit

(Input) (Output) (Note 7)

t

OSLH

(Note 8) A B 0.1 0.2

ns

t

OSHL

(Note 8) A B 0.1 0.6
tPS (Note 9) A B 0.3 1.0 ns
t

PV(HL)

(Note 10)(Note 11) A B 1.3 ns

t

OSLH

(Note 8) B A 0.1 0.7

ns

t

OSHL

(Note 8) B A 0.1 0.4
t

OST

(Note 8) B A 0.2 1.1 ns

t

PS

(Note 9) B A 0.1 1.0 ns

t

PV

(Note 10) B A 2.4 ns

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GTLP6C816A

Test Circuit and Timing Waveforms

Test Circuit for A Outputs

Note A: CL includes probes and jig capacitance.

Test Circuit for B Outputs

Note A: CL includes probes and jig capacitance.
Note B: For B-Port C

L

= 30 pF is used for worst case.

Voltage Waveform - Propagation Delay Times Voltage Waveform - Enable and Disable Times

Output Waveform 1 is for an out put with intern al conditio ns such that the
output is LOW excep t when disabled by the control output
Output Waveforms 2 is for an out put wit h inte rnal condition s such that the
output is HIGH excep t wh en disabled by the cont rol output

Input and Measure Conditions

All input pulses have the following characteristics: Frequency = 10MHz, t

RISE

= t

FALL

= 2 ns, ZO = 50Ω.

The outputs are meas ured one at a time with on e t ransition per measurement.

A or LVTTL

Pins

B or GTLP

Pins

V

inHIGH

3.0 1.5

V

inLOW

0.0 0.0

V

M

1.5 1.0

V

X

VOL + 0.3V N/A

V

Y

VOH + 0.3V N/A

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GTLP6C816A LVTTL-to-GTLP Clock Driver

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC24

Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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