Datasheet GTLP36T612 Datasheet (Fairchild Semiconductor)

September 2001
Revised July 2002

GTLP36T612
36-Bit LVTTL/GTLP Universal Bus Transceiver

GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver

General Description

The GTLP36T612 is an 36-bit universal bus transceiver
which provides LVTTL to GTLP sign al level translation. It
allows for transparent, latched and clocked modes of data
transfer. The device provides a high speed interface for
cards operating at LVTTL logic levels and a backplane
operating at GTLP logic levels. High speed backplane
operation is a direct re sult o f GT LP’s redu ced out put s wing
(

< 1V), reduced input threshold levels and output edge rate

control. The edge rate c ontrol mi nimizes b us settl ing time.
GTLP is a Fairchild Semicon ductor derivative of the Gun­ning Transistor logic (GTL) JEDEC standard JESD8-3.

Fairchild’s GTLP has internal edge-ra te control and is Pro­cess, Voltage, and Temperature (PVT) comp ensated. Its
function is similar to BTL or GT L but with different output
levels and receiver thresholds. GTLP output LOW le vel is
less than 0.5V, the output HIGH is 1 .5V and the receiver
threshold is 1.0V.

Features

■ Bidirectional interface between GTLP and LVTTL logic
levels

■ Designed with edge ra te control circuitry to r educe out­put noise on the GTLP port

■ Partitioned as two 18-Bit transceivers with individual
latch timing and output control

■ V

pin provides extern al supply re ference volta ge for

REF

receiver threshold adjustibility

■ Special PVT compensation circui try to provide consis­tent performance over var iatio ns of pr ocess, supply volt­age and temperature

■ TTL compatible driver and control inputs

■ Designed using Fairchild advanced BiCMOS technology

■ Bushold data inputs on A port to e liminate the need for

external pull-up resistors for unused inputs

■ Power up/down and power off high impedance for live
insertion

■ Open drain on GTLP to support wired-or connection

■ Flow through pinout optimizes PCB layout

■ D-type flip-flop, latch and transparent data paths

■ A Port source/sink

■ B Port sink

■ For more information see AN-5026,

Using BGA Packages

−24mA/+24mA

+50mA

Ordering Code:

Order Number Package Number Package Description

GTLP36T612G
(Note 1)(Note 2)

Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

BGA114A 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

© 2002 Fairchild Semiconductor Corporation DS500590 www.fairchildsemi.com

Truth Table

(Note 3)

Inputs Output Mode

OEAB LEAB CLKAB A B

CEAB

GTLP36T612

X H X X X Z Latched
LLLHXB
LLL LXB
X L H X L L Transparent
XLHXHH
LLL

↑ L L Clocked

LLL ↑ H H storage

HLL XXB

Note 3: A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA

, LEBA, CLKBA, and CEBA.

Note 4: Output level before the indicated steady state input conditions were
established, provided that CLKAB w as H I GH before LEAB went LOW.

Note 5: Output level befor e the indicated steady-state input conditions
were established.

(Note 4) storage

0

(Note 5) of A data

0

(Note 5) Clock inhibit

0

of A data

Pin Descriptions

Pin Names Description

OEAB

OEBA

CEAB

CEBA

LEAB A-to-B Latch Enable

LEBA B-to-A Latch Enable

V

REF

CLKAB A-to-B Clock (LVTTL Level)
CLKBA B-to-A Clock (LVTTL Level)
A

1–A18

B

1–B18

A-to-B Output Enable
(Active LOW) (LVTTL Level)

B-to-A Output Enable
(Active LOW) (LVTTL Level)

A-to-B Clock/LE Enable
(Active LOW) (LVTTL Level)

B-to-A Clock/LE Enable
(Active LOW) (LVTTL Level)

(Transparent HIGH) (LVTTL Level)

(Transparent HIGH) (LVTTL Level)
GTLP Input Threshold

Reference Voltage

A-to-B Data Inputs or
B-to-A 3-STATE Outputs

B-to-A Data Inputs or
A-to-B Open Drain Outputs

Connection Diagram

Pin Assignment for FBGA

(Top Thru View)

FBGA Pin Assignments

Number in front of each pin indicate s word.

12 3 4 56

A 1A
B 1A41A31LEAB 1CEAB 1B41B
C 1A61A5V
D 1A81A7GND GND 1B81B
E 1A101A9GND GND 1B101B
F 1A121A11GND GND 1B121B

G 1A141A13V

H 1A161A151OEBA 1CEBA 1B161B
J 1A181A171LEBA 1CLKBA 1B181B
K
L 2A

M 2A42A32LEAB 2CEAB 2B42B

N 2A62A5V
P 2A82A7GND GND 2B82B
R 2A102A9GND GND 2B102B
T 2A122A11GND GND 2B122B
U 2A142A13V
V 2A162A152OEBA 2CEBA 2B162B

W 2A182A172LEBA 2CLKBA 2B182B

1A11OEAB 1 CLKAB 1B21B

2

V

CC

CC

CCVREF

2A12OEAB 2 CLKAB 2B22B

2

V

CC

CC

CCVREF

1B61B

1B141B

2B62B

2B142B

1
3
5
7

9
11
13
15
17

1

3

5

7

9
11
13
15
17

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Functional Description

The GTLP36T612 is an 36-bit re giste red tran sceiver con tain ing D-type fl ip-fl op, latch and trans parent modes of op eration
for the data path. Data flow in each d irection is con trolled by the clock enables (CEAB
and LEBA), clock (CLKAB and CLKBA) and output en ables (OEAB
the output enables (OEAB

For A-to-B data flow, when CEAB
and on the HIGH-to-LOW transi tion of LEAB for the latch path. That is , if CEAB
latched regardless as to the state of CLKAB (HIGH or LOW) and if LEAB is HIGH the device is in transparent mode. When

is LOW the outputs are active. W hen OEAB is HIGH the outp uts are HIGH imped ance. The dat a flow of B-to-A is

OEAB
similar except that CEBA

and OEBA) control the 18 bits of data for the A-to-B and B-to-A directions respectively.

is LOW, the device operates on the LOW-to-HIGH transition of CLKAB for the flip-flop

, OEBA, LEBA, and CLKBA are used.

and OEBA). The clock enables (CEAB and CEBA) and

and CEBA), latch enables ( LEAB

is LOW and LEAB is LOW the A data is

Logic Diagram

GTLP36T612

3 www.fairchildsemi.com

Absolute Maximum Ratings(Note 6) Recommended Operating

Supply Voltage (VCC) −0.5V to +4.6V
DC Input Voltage (V
DC Output Voltage (V

Outputs 3-STATE

GTLP36T612

Outputs Active (Note 7)

) −0.5V to +4.6V

I

)

O

−0.5V to +4.6V

−0.5V to V

DC Output Sink Current into

A Port I

OL

DC Output Source Current from

A Port I

OH

DC Output Sink Current into

B Port in the LOW State, I

DC Input Diode Current (I

< 0V −50 mA

V

I

DC Output Diode Current (I

V

< 0V −50 mA

O

> V

V

O

CC

OL

)

IK

)

OK

ESD Perfo rmance
Storage Temperature (T

) −65°C to +150°C

STG

+ 0.5V

CC

48 mA

−48 mA

100 mA

+50 mA
>2000V

Conditions

Supply Voltage V
Bus Termination Voltage (V

GTLP 1.47V to 1.53V
V

REF

Input Voltage (V

on A Port and Control Pins 0.0V to 3.45V
on B Port 0.0V to 3.45V

HIGH Level Output Current (I

A Port

LOW Level Output Current (I

A Port
B Port

Operating Temperature (T

Note 6: Absolute Maximum continuous ratings are those values beyond
which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability.
Functional operation under absolute maximum rated conditions in not
implied.

Absolute Maximum Rating must be observed.

Note 7: I

O

Note 8: Unused inputs must be held HIGH or LOW.

(Note 8)

CC/VCCQ

)

I

)

TT

)

OH

)

OL

) −40°C to +85°C

A

DC Electrical Characteristics

Over Recommended Operating Free-Air Temperature Range, V

Symbol Test Conditions

V

IH

V

IL

V

REF

V

IK

V

OH

V

OL

I

I

I

OFF

I

I(hold)

I

OZH

I

OZL

ICC A or B Ports VCC = 3.45V Outputs HIGH 60 80

B Port V
Others 2.0
B Port 0.0 V
Others 0.8
GTLP (Note 10) 1.0 V

A Port VCC, V

A Port VCC, V

B Port VCC = 3.15V IOL = 40 mA 0.40

Control Pins VCC = Min to Max (Note 11) VI = 3.45V or 0V ±5 µA
A Port VCC = 3.45V VI = 0V −10

B Port VCC = 3.45V VI = V

A Port and Control Pins VCC = 0V
A Port VCC = 3.15V VI = 0.8V 75

A Port VCC = 3.45V VO = 3.45 10
B Port VO = 3.45V 5
A Port VCC = 3.45V VO = 0V −10
B Port VO = 0V −5

)I

CCQ

VCC = 3.15V II = −18 mA −1.2 V

= Min to Max (Note 11) IOH = −100 µAVCC –0.2

CCQ

= 3.15V IOH = −8 mA 2.4

CC

= Min to Max (Note 11) IOL = 100 µA0.2

CCQ

= 3.15V IOL = 24mA 0.5

V

CC

= 0 Outputs LOW 60 80

O

VI = VCC or GND Outputs Disabled 60 90

= 1.0V (unless otherwise noted).

REF

IOH = -24mA 2.0

IOL = 50 mA 0.55

VI = 3.45 10

CC

VI = 0 −5

or VO = 0 to 3.45V 30 µA

I

VI = 2.0V −75

Min Typ Max

+0.05 V

REF

(Note 9)

3.15V to 3.45V

0.98V to 1.02V

−24 mA

+24 mA
+50 mA

TT

− 0.05

REF

5

Units

V

V

VV

V

V

µA

µA

µA

µA

µA

mA(VCC/V

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DC Electrical Characteristics (Continued)

GTLP36T612

Symbol Test Conditions

∆I

CC

A Port and VCC = 3.45V,
(Note 12) Control Pins A or Control Inputs at VCC or GND
C

i

Control Pins VI = VCC or 0 6

A Port V

One Input at 2.7V 2 mA

= VCC or 0 7 .5 pF

I

Min Typ Max

B Port VI = VCC or 0 9.0

Note 9: All typical values are at VCC = 3.3V , V
Note 10: GTLP V

In addition, V
must remain within the boundaries of the DC Absolute Maximum ratings. Similarly V

Note 11: For conditions shown as Min or Max, us e t he appropriate valu e s pecified under recommended operatin g c onditions.
Note 12: This is the increase in supply curre nt fo r each input that is at the specified TTL voltage lev el rather than V

and V

REF

and Rterm can b e adjusted beyond t he recomm ended op erating c onditions t o accomm odate bac kplane imp edances other than 50Ω, b ut

TT

are specified to 2% to lerance since signal in t egrity and noise marg in c an be significantly deg raded if these suppli es are noisy.

TT

= 3.3V, and TA = 25°C.

CCQ

can be adjusted to optimize noise margin.

REF

or GND.

CC

AC Operating Requirements

Over recommended ranges of supply voltage and operating free-air temperature, V

Symbol Test Conditions Min Max Unit

f

MAX

t

WIDTH

Maximum Clock Frequency 175 MHz
Pulse Duration LEAB or LEBA HIGH 3.0

CLKAB or CLKBA HIGH or LOW 3.0

t

SU

Setup Time A before CLKAB↑ 1.1

B before CLKBA↑ 3.0
A before LEAB 1.1
B before LEBA 2.7

CEAB before CLKAB↑ 1.2
CEBA before CLKBA↑ 1.4

t

HOLD

Hold Time A after CLKAB↑ 0.0

B after CLKBA↑ 0.0
A after LEAB 0.8
B after LEBA 0.0

CEAB after CLKAB↑ 1.0
CEBA after CLKBA↑ 1.9

= 1.0V (unless otherwise noted).

REF

(Note 9)

Units

ns

ns

ns

5 www.fairchildsemi.com

AC Electrical Characteristics

Over recommended range of supply voltage and operating free-air temperature, V

C

= 30 pF for B Port and C

L

Symbol

t

GTLP36T612

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

RISE

t

FALL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

, t

t

PZH

PZL

t

, t

PHZ

PLZ

Note 13: All typical values are at VCC = 3.3V, and TA = 25°C.

= 50 pF for A Port.

L

From To Min Typ Max

(Input) (Output) (Note 13)

AB2.14.16.3

LEAB B 2.2 4.2 6.3

CLKAB B 2.2 4.4 6.5

OEAB B 2.0 3.8 5.6

Transition Time, B Outputs (20% to 80%) 3.1
Transition Time, B Outputs (20% to 80%) 2.1

BA1.83.85.8

LEBA A 0.3 2.2 4.6

CLKBA A 0.5 2.4 4.6

OEBA A 0.3 2.7 5.2

= 1.0V (unless otherwise noted).

REF

1.0 2.7 4.4

1.0 2.4 4.2

1.0 2.5 4.4

1.0 2.6 4.3

1.8 3.8 5.8

0.4 2.4 4.6

0.6 2.6 4.6

0.3 2.5 5.2

Unit

ns

ns

ns

ns

ns

ns

ns

ns

ns

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Test Circuits and Timing Waveforms

GTLP36T612

Tes t Circuit for A Outputs

Test Circuit for B Outputs

Test S

t

PLH/tPHL

t

PLZ/tPZL

t

Note A: CL includes probes and Jig capacitance.

PHZ/tPZH

Open
6V
GND

Note B: For B Port, CL = 30 pF is used for worst case.

Voltage Waveform - Propagation Delay Times Voltage Waveform - Setup and Hold Times

Voltage Waveform - Pulse Width Voltage Waveform - Enable and Disable times

Output Waveform 1 is for an output with internal conditions such that the
output is LOW except when disabled by the control output.
Output Waveform 2 is for an output with internal conditions such that the
output is HIGH except when disabled by the control output.

Input and Measure Conditions

A or L VTTL
Pins

V

inHIGH

V

inLOW

V

M

V

X

V

All input pulses have the following characteristics: Frequency = 10MHz, t
The outputs are measured one at a ti me wi t h one transition per measurement.

Y

3.0 1.5

0.0 0.0

1.5 1.0
VOL + 0.3V N/A
VOH − 0.3V N/A

B or GTLP
Pins

RISE

7 www.fairchildsemi.com

= t

= 2 ns (10% to 90%), ZO = 50Ω.

FALL

Physical Dimensions inches (millimeters) unless otherwise noted

GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver

114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied a nd
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life supp or t de vices o r syste ms a re device s or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

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Package Number BGA114A

2. A cri tical compon ent in any com ponen t of a life su pport
device or system whose failu re to perform can be rea­sonably expected to cause the failure of the li fe su pp ort
device or system, or to affect its safety or effectiveness.

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