Datasheet GTLP2T152 Datasheet (Fairchild Semiconductor)

GTLP2T152
2-Bit LVTTL/GTLP Transceiver

GTLP2T152 2-Bit LVTTL/GTLP Transceiver

June 2001
Revised February 2002

General Description

The GTLP2T152 is a 2-bit transceiver that provides LVTTL­to-GTLP signal level translation. Data directional control is
handled with a transmit/re ceive pin . High- speed ba ckpla ne
operation is a direct result of GTLP’s reduced outp ut swi ng
(

<1V), r edu ced input threshold levels an d ou tpu t edg e rate

control. The edge rate con trol minimizes bus -settling tim e.
GTLP is a Fairchild Semicon ductor derivative of the Gun­ning Transistor logic (GTL) JEDEC standard JESD8-3.

Fairchild’s GTLP has intern al edge -rate cont rol and i s pro­cess, voltage and tem perature compensated. GTLP ’s I/O
structure is similar to GTL and BTL but offers different out­put levels and receiver threshold. Typical GTLP output volt­age levels are: V

= 0.5V, VOH = 1.5V, and V

OL

REF

= 1V.

Features

■ Bidirectional interface between GTLP and LVTTL logic
levels

■ Designed with edge ra te control circuitry to r educe out­put noise on the GTLP port

pin provides extern al supply re ference volta ge for

■ V

REF

receiver threshold adjustibility

■ Special PVT compensation circui try to provide consis­tent performance over var iatio ns of pr ocess, supply volt­age and temperature

■ TTL compatible driver and control inputs

■ Designed using Fairchild advanced BiCMOS technology

■ Bushold data inputs on A port to e liminate the need for

external pull-up resistors for unused inputs

■ Power up/down and power off high impedance for live
insertion

■ Open drain on GTLP to support wired-or connection

■ Flow through pinout optimizes PCB layout

■ A Port source/sink

■ B Port sink

−24mA/+24mA

+50mA

Ordering Code:

Order Number Package Number Package Description

GTLP2T152M M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

GTLP2T152MX M08A 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

GTLP2T152K8X MAB08A

(Preliminary)

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8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

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Pin Descriptions Connection Diagrams

Pin Names Description

T/R

, GND, V

V

CC

A
B

© 2002 Fairchild Semiconductor Corporation DS500486 www.fairchildsemi.com

LVTTL Direction Control
(Receive Direction is Active LOW)

Device Supplies

REF

A Port LVTTL Input/Output

n

B Port GTLP Input/Output

n

US8

SOIC

Functional Description

The GTLP2T152 is a 2-bit tra nsceiver that supports GTLP and LVTTL signal levels. Data pola rity is non-inv erting and the
the GTLP/LVTTL outputs are controlled by the T/R

Functional Table

GTLP2T152

Inputs

T/R

HBus A
LBus B

pin.

Outputs Description

Data to Bus B

n

Data to Bus A

n

Bn Output Data Enabled

n

An Output Data Enabled

n

Logic Diagram

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Absolute Maximum Ratings(Note 1) Recommended Operating

Supply Voltage (VCC) −0.5V to +4.6V
DC Input Voltage (V
DC Output Voltage (V

Outputs 3-STATE
Outputs Active (Note 2)

) −0.5V to +4.6V

I

)

O

−0.5V to +4.6V

−0.5V to +4.6V

DC Output Sink Current into

A Port I

OL

48 mA

DC Output Source Current from

A Port I

OH

−48 mA

DC Output Sink Current into

B Port in the LOW State, I

DC Input Diode Current (I

< 0V −50 mA

V

I

DC Output Diode Current (I

V

< 0V −50 mA

O

OL

)

IK

)

OK

ESD Rating

Storage Temperature (T

) −65°C to +150°C

STG

100 mA

>2000V

Conditions

Supply Voltage V
Bus Termination Voltage (V

GTLP 1.47V to 1.53V
V

REF

Input Voltage (V

on A Port and Control Pins 0.0V to V

HIGH Level Output Current (IOH)

A Port

LOW Level Output Current (I

A Port
B Port

Operating Temperature (T

Note 1: Absolute Maximum Ratings are those values beyond which the
safety of the device can not be gu arant eed. The de vice sh ould no t be oper-

ated at these limits. The parametric values defined in the “Electrical Char­acteristics” table are not guarant eed at the ab solute max imum ratin g. The
“Recommended Operating Con ditions” table will define the conditions for
actual device opera tion.

Absolute Maximum Rating must be observed.

Note 2: I

O

CC

)

I

)

TT

)

OL

) −40°C to +85°C

A

DC Electrical Characteristics

Over Recommended Operating Free-Air Temperature Range, V

Symbol Test Conditio ns

V

V

V
V
V
V

V

I

I

IH

IL

REF
TT
IK
OH

OL

I

OFF

B Port V
Others 2.0
B Port 0.0 V
Others 0.8
B Port 0.7V 1.0 1.3V V
B Port V

A Port VCC = Min to Max (Note 4) IOH = −100 µAV

A Port VCC = Min to Max (Note 4) IOL = 100 µA0.2

B Port VCC = 3.15V IOL = 40 mA 0.4

Control Pins VCC = 3.45V VI = 3.45V 5

A Port VCC = 3.45V VI = 3.45V 10

B Port VCC = 3.45V VI = 3.45V 5

A Port, VCC = 0V
Control Pins
B Port VCC = 0V

VCC = 3.15V II = −18 mA −1.2 V

= 3.15V IOH = −8 mA 2.4

CC

= 3.15V IOL = 24 mA 0.5

V

CC

= 1.0V (unless otherwise noted).

REF

= -24 mA 2.2

I

OH

IOL = 50 mA 0.55

VI = 0V −5

VI = 0V −10

VI = 0 −5

or VO = 0 to 3.45V 30 µA

I

or VO = 0 to 3.45V 30 µA

I

Min Typ Max

+ 0.05 V

REF

+ 50 mV 1.5 V

REF

- 0.2

CC

(Note 3)

REF

3.15V to 3.45V

0.98V to 1.02V

−24 mA

+24 mA
+50 mA

TT

− 0.05

CC

GTLP2T152

CC

Units

V

V

V

VV

VVCC = 3.15V IOL = 8 mA 0.4

V

µA

µA

µA

I

I (HOLD)

I

OZH

A Port VCC = 3.15V VI = 0.8V 75

VI = 2.0V −75
A Port VCC = 3.45V VO = 3.45V 10
B Port VO = 3.45V 5

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µA

µA

DC Electrical Characteristics (Continued)

Symbol Test Conditions

I

OZL

GTLP2T152

I

PU/PD

I

CC

A Port VCC = 3.45V VO = 0V −10
B Port V

= 0V −5

O

All Ports VCC = 0 to 1.5V VI = 0 to 3.45V 30 µA

A Port VCC = 3.45V Outputs HIGH 11

= 0 Outputs LOW 11

O

Min Typ Max

(Note 3)

VI = VCC/VTT or GND Outputs Disabled 11

∆I

CC

(Note 5) Control Pins A or Control Inputs at V
C

i

C

I/O

Note 3: All typical values are at VCC = 3.3V and TA = 25°C.
Note 4: For conditions shown as Min, use the appropri at e v alue specified under recommended operating conditions.
Note 5: This is the increase in supply current for each input that is at the specif ied TTL voltage level rather than V
Note: GTLP V

addition, V
within the boundaries of the DC Absolu te M ax im um Ratings. Simil arly, V

A Port and VCC = 3.45V, One Input at V

or GND −0.6V

CC

CC

Control Pins VI = VCC or 0 3 pF
A Port VI = VCC or 0 5 pF
B Port V

and VTT are specified to 2 % tolerance sinc e s ignal integrity and noise margin ca n be significantly degraded if these supplies are noisy. In

REF

and R

TT

can be adjusted bey ond the recom mende d operating to accomm odate bac kplane impe dances o ther than 50 Ω, but must remain

TERM

= VTT or 0 5.5 pF

I

or GND.

CC

can be adjusted to optimize noise margin.

REF

AC Electrical Characteristics

Over recommended range of supply voltage and operating free-air temperature, V

CL = 30 pF for B Port and CL = 50 pF for A Port.

Symbol

t

PLH

t

PHL

t

PLH

t

PHL

t

RISE

t

FALL

t

RISE

t

FALL

Note 6: All typical values are at VCC = 3.3V, and TA = 25°C.

From To Min Typ Max

(Input) (Output) (Note 6)

AB

BA

Transition Time, B Outputs (20% to 80%) 1.5 ns
Transition Time, B Outputs (80% to 20%) 1.8 ns
Transition Time, A Outputs (10% to 90%) 2.5 ns
Transition Time, A Outputs (90% to 10%) 2.2 ns

= 1.0V (unless otherwise noted).

REF

1.2 2.9 7.3

0.8 2.0 4.5

1.4 2.5 4.4

1.6 2.7 5.0

Units

µA

mAor B Port I

2mA

Unit

ns

ns

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Test Circuits and Timing Waveforms

GTLP2T152

Tes t Circuit for A Outputs

Test Circuit for B Outputs

Test S

t

PLH/tPHL

t

PLZ/tPZL

t

Note: CL includes probes an d J ig c apacitance.

PHZ/tPZH

OPEN
6V
GND

Note: CL includes probes and Jig capacitance.
Note: For B Port, C

= 30 pF is used for worst case.

L

Voltage Waveforms Propagation Delay Voltage Waveform Enable and Disable Times

A or LVTTL

Pins

V

INHIGH

V

INLOW

V

M

V

X

V

Y

Note: Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control.

Note: All input pulses have the follow ing characteristic s :

Frequency = 10MHz, t

= t

= 2 ns (10% to 90%), ZO = 50Ω. The outputs are me as ured one at a time with one transition per m eas urement.

RISE

FALL

V

CC

0.0 0.0

VCC/2 1.0
VOL + 0.3V N/A
VOH − 0.3V N/A

B or GTLP

Pins

1.5

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Physical Dimensions inches (millimeters) unless otherwise noted

GTLP2T152

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M08A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

GTLP2T152 2-Bit LVTTL/GTLP Transceiver

8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

Fairchild does not assume any responsibility for use of any circuitry described , no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the l abe ling, can be rea­sonably expected to result in a significant injury to the
user.

Package Number MAB08A

Preliminary

2. A critical component in any com ponen t of a life s upp ort
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

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