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GTLP16612AA
Datasheet (PERIC)
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Datasheet GTLP16612AA Datasheet (PERIC)

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1
PS8431 09/24/99
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Product Description
Pericom Semiconductors GTLP series of logic circuits are produced using the Companys advanced 0.5 micron CMOS technology, achieving industry leading performance.
The GTLP16612A 18-bit universal transceiver provides TTL to GTLP signal level translation. The device is designed to provide high­speed interface between cards operating at TTL logic levels and a back plane operating at GTLP logic levels. High-speed back plane operation is a direct result of GTLPs reduced output swing (<1V), reduced input threshold levels, and output edge-rate control which minimizes signal settling times. Its function is similar to BTL or GTL but with modified driver output levels and receiver threshold. GTLP output low voltage is typically less than 0.5V, the output high is 1.5V, and the receiver threshold is 1.0V.
Features
 Bidirectional interface between GTLP and TTL
logic levels
 Designed with Edge Rate Control Circuit to
reduce output noise
VREF pin provides external supply reference voltage
for receiver threshold  5V tolerant inputs and outputs on A-Port  Increased B-Port Drive, 50mA  Bus-Hold data inputs on A-Port to eliminate the need for
pull-up resistors for unused inputs  Power up/down high impedance  TTL compatible Driver and Control inputs  A-Port Balanced Drive: 32mA/+32mA  Flow-through architecture  Open drain on GTLP to support wired-or connection  Package:
 56-pin 240 Mil Wide Plastic TSSOP (A)
Pin Configuration
Logic Block Diagram
GTLP16612A
CMOS 18-Bit TTL/GTLP Universal Bus Transceiver
CLK
CI
1D
CE
GTLP
OEAB
CEAB
LEAB
LEBA
CEBA
OEBA
A1
3
CLKAB
CLKBA
1
56
2
28
29
27
54
B1
55
30
V
CLK
CI
1D
CE
V
1 of 18 Channels
1 of 18 Channels
OEAB
LEAB
CEAB CLKAB
1 2
A1
A2 A3
A4
A6
A5
A7
A9
A8
A10
A12
A11
A13
A15
A14
A17
A18 B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
A16
3
GND 4
5 6 7
V
CC
(3.3V)
8 9 10
GND
11 12 13 14 15 16 17
GND 18
19 20 21
V
CC
(3.3V)
22 23 24
56 55
B
1
54
GND53 52 51
V
CCQ
(5.0V)
50 49 48 47
GND46 45 44 43 42 41 40
GND39 38 37 36
V
REF
35 34 33
GND 25
26 27
LEBA
OEBA
28
GND32 31
CLKBA30
CEBA29
56-Pin
A,V
2
PS8431 09/24/99
GTLP16612A
CMOS 18-Bit TTL/GTLP
Universal Bus Transceiver
Pin Descriptions
stupnI
BtuptuOedoM
BAECBAEOBAELBAKLCA
XHX X X Z
dehctaL egarotS
ataDAfo
LLL H X B
0
)2(
LLL L X B
0
)3(
XLH X L L
tnerapsnarT
XLH X H H
LLL
↑
LL
egarotSdekcolC
ataDAfo
LLL
↑
HH
HLL X X B
0
)3(
tibihnIkcolC
Notes:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA.
2. Output level before indicated steady-state input conditions were estab­lished, provided CLKAB was HIGH before LEAB went LOW.
3. Output level before indicated steady-state input conditions were estab­lished.
Truth Table
(1)
semaNniPnoitpircseD
BAEO)WOLevitcA(elbanEtuptuOB-ot-A
ABEO)WOLevitcA(elbanEtuptuOA-ot-B
BAEC)WOLevitcA(elbanEkcolCB-ot-A
ABEC)WOLevitcA(elbanEkcolCA-ot-B
BAEL)HGIHtnerapsnarT(elbanEhctaLB-ot-A
ABEL)HGIHtnerapsnarT(elbanEhctaLA-ot-B
BAKLCesluPkcolCB-ot-A
ABKLCesluPkcolCA-ot-B
FERVegatloVecnerefeRtupnIPLTG
81A-1A
rostupnIataDLTTB-ot-A
stuptuOetatS-3A-ot-B
81B-1BrostupnIataDPLTGA-ot-B
stuptuOniarDnepOB-ot-A
Functional Description
The PI74GTLP16612A combines a universal transceiver function with a TTL to GTLP translation. The A-Port and control pins operate at LVTTL or 5V TTL levels while the B-Port operates at GTLP levels. The transceiver logic includes D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clock mode. The functional operation is described below:
3
PS8431 09/24/99
GTLP16612A
CMOS 18-Bit TTL/GTLP
Universal Bus Transceiver
Storage Temperature (T
STG
) ............................................... 65°C to +150°C
Supply Voltage (VCC, V
CCQ
) ................................................... 0.5V to +7.0V
DC Input Voltage (VI) ........................................................... 0.5V to +7.0V
DC Output Voltage (VO)
Outputs 3-State .................................................................. 0.5V to +7.0V
Outputs Active
(5)
........................................................ 0.5V to VCC +0.5V
DC Output Current into A-Port I
OH /IOL
............................... 64mA/+64mA
DC Output Sink Current into B-Port in LOW State IOL......................100mA
DC Input Diode Current (IIK) V
I
< 0V ............................................................................................ 50mA
DC Output Diode Current (IOK) V
O
< 0V ........................................................................................... 50mA
V
O
> VCC.......................................................................................... +50mA
ESD Performance .............................................................................. >2000V
Notes:
4. The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristic tables are not guaranteed at the absolute maximum rating. The Recommended Operating Conditions table will define the conditions for actual device operation.
5. IO Absolute Maximum Rating must be observed
6. Unused inputs must be held HIGH or LOW.
Recommended Operating Condition
(6)
Absolute Maximum Ratings
(4)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage (VCC)
VCC
....................................................................................... 3.15V to 3.45V
V
CCQ
..................................................................................... 4.75V to 5.25V
Bus Termination Voltage (VTT) .............................................. 1.35V to 1.65V
Input Voltage (VI) on A-Port and Control Pins ........................ 0.0V to 5.5V
HIGH Level Output Current (IOH)
A-Port ............................................................................................ 32mA
LOW Level Output Current (IOL)
A-Port ............................................................................................ +32mA
B-Port ............................................................................................. +50mA
Operating Temperature (TA) ................................................ 40°C to +85°C
4
PS8431 09/24/99
GTLP16612A
CMOS 18-Bit TTL/GTLP
Universal Bus Transceiver
Notes:
7. All typical values are at VCC = 3.3V, V
CCQ
= 5.0V, and TA = 25°C
8. For conditions shown as Max. or Min., use the appropriate value specified under recommended operating conditions.
9. This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
DC Electrical Characteristics
(Over the Operating Free-Air Temperature Range, V
REF
= 1.0 (Unless otherwise noted)
lobmySsnoitidnoCtseT .niMpyT
)7(
.xaM stinU
V
HI
troP-BV
FER
1.0+V
TT
V
srehtO 0.2
V
LI
troP-B 0.0V
FER
1.0
srehtO 8.0
V
FER
0.1
V
KI
V
CC
,V51.3=
V
QCC
V57.4=
I
I
Am81=2.1
V
HO
troP-A
V
CC
V,
QCC
xaMot.niM=
)8(
I
HO
001= µAVCC2.0
V
CC
V51.3=
V
QCC
V57.4=
I
HO
Am8=4.2
I
HO
Am23=0.2
V
LO
troP-AV
CC
V,
QCC
xaMot.niM=
)8(
I
LO
001= µA2.0
V
CC
V51.3=
V
QCC
V57.4=
I
LO
Am23=5.0
troP-BV
CC
V,V51.3=
QCC
V57.4=ILOAm05=56.0
I
I
sniPlortnoCV
CC
V,
QCC
xaMro0=V
I
V0roV5.5=01±
µA
troP-AV
CC
V54.3=
V
QCC
V52.5=
VIV5.5=02
V
IV=CC
1
V
I
0=03
troP-B
V
CC
V54.3=V
I
V=
QCC
5
V
QCC
V52.5=V
I
0=5
I
FFO
troP-AV
CC
V=
QCC
0=
V
I
Vro
O
ot0=
V5.4
001
I
)DLOH(I
troP-AVCC,V51.3=
V
QCC
V57.4=
VIV8.0=57
V
I
V0.2=02
I
HZO
troP-A
V
CC
,V54.3=
V
QCC
V52.5=
V
O
V54.3=1
troP-BV
O
V5.1=5
I
LZO
troP-A
V
CC
V54.3=
V
QCC
V52.5=
V
O
0=02
troP-BV
O
V56.0=01
I
QCC
V(
QCC
)
BroA
stroP
V
CC
,V54.3=
V
QCC
V52.5=
,
IO0=
,
VIV=
QCC
DNGro
HGIHstuptuO0304
Am
WOLstuptuO0304
delbasiDstuptuO0304
I
CC
V(CC)
BroA
stroP
V
CC
V54.3=
,
V
QCC
V52.5=
,
IO0=
,
VIV=
QCC
DNGro
HGIHstuptuO01
WOLstuptuO01
delbasiDstuptuO01
Ι∆
CC
)9(
dnatroP-A
sniPlortnoC
V
CC
V54.3=
,
V
QCC
,V52.5=
VtastupnIlortnoCroA
CC
DNGro
V7.2tatupnIenO01
C
NI
sniPlortnoCV
I
V=
QCC
0ro8
Fp
C
O/I
troP-AV
I
V=
QCC
0ro9
C
O/I
troP-BV
I
V=
QCC
0ro
8
5
PS8431 09/24/99
GTLP16612A
CMOS 18-Bit TTL/GTLP
Universal Bus Transceiver
lobmyS.niM.xaMstinU
f
KCOLC
ycneuqerFkcolCxaM571zHM
t
W
noitaruDesluPHGIHABELroBAEL0.3
sn
WOLroHGIHABKLCroBAKLC2.3
t
S
emiTputeSBAKLCerofebA ↑ 5.0
ABKLCerofebB ↑ 1.3
BAELerofebA ↓ 3.1
ABELerofebB ↓ 7.3
BAKLCerofebBAEC ↑ 4.0 ABKLCerofebABEC ↑ 0.1
t
H
emiTdloHBAKLCretfaA ↑ 5.1
ABKLCretfaB ↑ 0.0
BAELretfaA ↓ 5.0
ABELretfaB ↓ 0.0
BAKLCretfaBAEC ↑ 5.1 ABKLCretfaABEC ↑ 7.1
AC Operating Requirements
(Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0 (Unless otherwise noted)
6
PS8431 09/24/99
GTLP16612A
CMOS 18-Bit TTL/GTLP
Universal Bus Transceiver
AC Electrical Characteristics
(Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0 (Unless otherwise noted) CL = 30pF for B-Port and CL = 50pF for A-Port.
lobmyS
morF
)tupnI(
oT
)tuptuO(
.niM.pyT
)01(
.xaMstinU
t
HLP
AB
0.13.45.6
sn
t
LHP
0.10.52.8
t
HLP
BAELB
8.15.47.6
t
LHP
5.13.56.8
t
HLP
BAKLCB
8.16.47.6
t
LHP
5.14.57.8
t
HLP
BAEOB
6.14.42.6
t
LHP
3.11.68.9
t
ESIR
B,emitnoitisnarT
)%08ot%02(stuptuo
6.2
t
LLAF
B,emitnoitisnarT
)%08ot%02(stuptuo
6.2
t
HLP
BA
0.26.52.8
t
LHP
4.10.52.7
t
HLP
ABELA
1.22.43.6
t
LHP
9.13.30.5
t
HLP
ABKLCA
3.24.48.6
t
LHP
2.25.32.5
t
,HZP
t
LZP
ABEOA
5.10.52.6
t
,ZHP
t
ZLP
9.19.39.7
Note 10 : All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA= 25°C
7
PS8431 09/24/99
GTLP16612A
CMOS 18-Bit TTL/GTLP
Universal Bus Transceiver
Test Circuits and Timing Waveforms
500
Ω
500
Ω
GND
6V
Open
S
CL includes probes and jig capacitance.
From Output Under Test
CL = 50pF
V
25
Ω
CL includes probes and jig capacitance.
For B-Port outputs, CL= 30pF is used for
worst case edge rate
From Output Under Test
30pF
1.5V (GTLP)
1.2V (GTL)
V
t
PHL
t
PLH
0V
1.5V
3.0V
INPUT
1.5V
V
OL
1.0V
V
OH
OUTPUT
1.0V
t
w
Vm V
Input
Vm V
3.0V
0V
Test Circuit for A Outputs
Test Circuit for B Outputs
Voltage Waveforms Pulse Duration
(Vm = 1.5V for A-Port and 1.0V for B-Port)
Voltage Waveforms Propagation Delay Times (A-Port to B-Port)
Voltage Waveforms Setup and Hold Times
(Vm = 1.5V for A-Port and 1.0V for B-Port)
Voltage Waveforms Propagation Delay Times (B-Port to A-Port)
Voltage Waveforms Enable and Disable
Times (A-Port)
t
PHL
t
PLH
0V
1.0V
1.5V
INPUT
1.0V
V
OL
1.5V
V
OH
OUTPUT
1.5V
All input pulses have the following characteristics: frequency = 10 MHz, tp = 4 = 2ns, Z
O
= 50Ω. The outputs are measured one at a time with one transition per measurement.
t
SU
t
h
Vm V
Vm V
Data Input
Timing Input
Vm V
3.0V
0V
3.0V
0V
All input pulses have the following characteristics: frequency = 10 MHz, tr=tf= 2ns, ZO=50
Ω.
The outputs are measured one at a time with one transition per measurement.
t
PZL
Output Control
0V
3.0V
1.5V
1.5V
1.5V
1.5V
t
PLZ
V
OL
3.0V
0V
t
PZH
t
PHZ
Output
Waveform 1
(S at 6V)
Output
Waveform 2
V
OH
VOH-0.3V
V
OL
+0.3V
Waveforn 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high when disabled by the output control. All input pulses have the following characteristics: frequency = 10 MHz, tr=tf= 2ns, ZO=50Ω. The outputs are measured one at a tim
e
with one transition per measurement.
8
PS8431 09/24/99
GTLP16612A
CMOS 18-Bit TTL/GTLP
Universal Bus Transceiver
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
56-Pin TSSOP (240 MIL WIDE) - Package Code: A56
.002 .006
SEATING PLANE
.07 .011
.004 .008
1
56
.236 .244
0.50
0.17
0.27
0.05
0.15
0.09
0.20
X.XX X.XX
DENOTES DIMENSIONS IN MILLIMETERS
.018 .030
0.45
0.75
.047 Max.
1.20
6.0
6.2
.547 .555
13.9
14.1
.319
8.1
.0197 BSC
BSC
N/PnoitpircseD
AA21661PLTG
,)POSST(egakcaPeniltuOllamSknirhSnihTdaeL-65
ediWmm1.6,351-OMCEDEJ
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