Datasheet GTL16612 Datasheet (Philips)

INTEGRATED CIRCUITS

GTL16612

+

18-bit GTL/GTL

to LVTTL/TTL

bidirectional latched translator (3-State)

Product specification




1999 Sep 13

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

+

18-bit GTL/GTL

to LVTTL/TTL bidirectional

GTL16612

latched translator (3-State)

FEA TURES

•18-bit bidirectional bus interface

•Translates between GTL/GTL+ logic levels (B ports) and

LVTTL/TTL logic levels (A ports)

•5 V I/O tolerant on the LVTTL/TTL side (A ports)

•No bus current loading when LVTTL/TTL output is tied to 5 V bus

•3-State buffers

•Output capability: +64 mA/-32 mA on the LVTTL/TTL side

(A ports); +40 mA on the GTL side (B ports)

•TTL input levels on control pins

•Power-up reset

•Power-up 3-State

•Positive edge triggered clock inputs

•Latch-up protection exceeds 500 mA per JESD78

•ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

QUICK REFERENCE DATA

t

PLH

t

PHL

C
C
I

CCZ

Propagation delay
An to Bn or Bn to An

Input capacitance (Control pins) VI = 0 V or V

IN

I/O pin capacitance Outputs disabled; V

I/O

Total supply current Outputs disabled 12 mA

CL = 50 pF 1.9 ns

DESCRIPTION

The GTL16612 is a high-performance BiCMOS product designed for
V

operation at 3.3 V with I/O compatibility up to 5 V .

CC

This device is an 18-bit universal transceiver featuring non-inverting
3-State bus compatible outputs in both send and receive directions.
Data flow in each direction is controlled by output enable (OEAB
OEBA

), latch enable (LEAB and LEBA), and clock (CPAB and
CPBA) inputs. For A-to-B data flow, the device operates in the
transparent mode when LEAB is High. When LEAB is Low, the A
data is latched if CPAB is held at a High or Low logic level. If LEAB
is Low, the A-bus data is stored in the latch/flip-flop on the
Low-to-High transition of CPAB. When OEAB
active. When OEAB
state. The clocks can be controlled with the clock-enable inputs
(CEBA/CEAB).

Data flow for B-to-A is similar to that of A-to-B but uses OEBA
LEBA and CPBA.

CONDITIONS

T

= 25°C

amb

CC

= 0 V or V

I/O

is High, the outputs are in the high-impedance

CC

is Low, the outputs are

TYPICAL

3.3 V

4 pF
8 pF

and

,

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DWG NUMBER

56-Pin Plastic TSSOP Type II –40°C to +85°C GTL16612 DGG SOT364-1

1999 Sep 13 853–2166 22326

2

Philips Semiconductors Product specification

18-bit GTL/GTL+ to LVTTL/TTL bidirectional
latched translator (3-State)

PIN CONFIGURATION

1

OEAB

2

LEAB

3

A0

4

GND

A1

5

A2

6
7

V

CC

8

A3

9

A4

10

A5

11

GND

12

A6

13

A7

14

A8

15

A9

16

A10

17

A11

18

GND GND

19

A12

20

A13

21

A14

22

V

CC

23

A15

24

A16

25

GND

A17

26
27

OEBA

28 29

LEBA

SW00485

56

CEAB
CPAB

55

B0

54
53

GND
B1

52

B2

51

NC

50

B3

49

B4

48

B5

47
46

GND
B6

45

B7

44

B8

43

B9

42

B10

41

B11

40
39

B12

38

B13

37

B14

36
35

V

REF

B15

34

B16

33
32

GND
B17

31

CPBA

30

CEBA

GTL16612

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

1, 27 OEAB/OEBA A-to-B/ B-to-A Output enable

29, 56 CEBA/CEAB B-to-A/A-to-B clock enable

2, 28 LEAB/LEBA A-to-B/B-to-A Latch enable input

55,30 CPAB/CPBA A-to-B/B-to-A Clock input

3, 5, 6, 8, 9, 10,

12, 13, 14, 15,
16, 17, 19, 20,

A0-A17 Data inputs/outputs (A side)

21, 23, 24, 26

54, 52, 51, 49,
48, 47, 45, 44,
43, 42, 41, 40,

B0-B17 Data inputs/outputs (B side)

38, 37, 36, 34,

33, 31

4, 11, 18, 25,

GND Ground (0 V)

32, 39, 46, 53

7, 22 V

35 V

CC

REF

50 NC No connection

input (active Low)

(active rising edge)

Positive supply voltage
GTL reference voltage

1999 Sep 13

3

Philips Semiconductors Product specification

18-bit GTL/GTL+ to LVTTL/TTL bidirectional
latched translator (3-State)

LOGIC SYMBOL (Positive Logic)

1

OEAB

56

CEAB

55

CPAB

2

LEAB

28

LEBA

30

CPBA

29

CEBA

27

OEBA

3

A0

CE

1D

C1

CLK

CE
1D
C1

CLK

GTL16612

54

B0

To 17 other channels

SW00254

FUNCTION TABLE

INPUTS

CEAB1OEAB1LEAB1CPAB

1

X H X X X Z
X L H X L L
X L H X H H
H L L X X B
H L L X X B
L L L ↑ L L
L L L ↑ H H
L L L H X B
L L L L X B

X = Don’t care
H = High voltage level
L = Low voltage level
↑ = Low to High
Z = High impedance “off” state

1. A-to-B data flow is shown: B-to-A flow is similar but uses OEBA

2. Output level before the indicated steady-state input conditions were established.

3. Output level before the indicated steady-state input conditions were established, provided that CP AB was Low before LEAB went Low.

OUTPUT

A

B

2

O

2

O

2

O

3

O

, LEBA, CPBA, and CEBA.

1999 Sep 13

4

Philips Semiconductors Product specification

V

DC input voltage

3

V

V

DC output voltage

3

IOLCurrent into any output in the LOW state

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

VTTTermination voltage

V

V

GTL reference voltage

V

V

Input voltage

V

VIHHIGH-level input voltage

V

VILLOW-level input voltage

V

IOLLOW-level output current

mA

18-bit GTL/GTL+ to LVTTL/TTL bidirectional

GTL16612

latched translator (3-State)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

I

I

OK

I

OH

T

DC supply voltage –0.5 to +4.6 V

CC

DC input diode current VI < 0 –50 mA

IK

I

p

DC output diode current VO < 0; A port –50 mA

O

p

Current into any output in the HIGH state A port –64 mA
Storage temperature range –65 to +150 °C

stg

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

p

1, 2

A port –0.5 to +7.0
B port –0.5 to +4.6

Output in Off or High state; A port –0.5 to +7.0 V
Output in Off or High state; B port –0.5 to +4.6 V

A port 128 mA
B port 80 mA

RECOMMENDED OPERATING CONDITIONS

T

V

I

REF

OH

amb

DC supply voltage 3.0 3.6 V

CC

I

p

p

p

HIGH-level output current A port –32 mA

p

Operating free-air temperature range –40 +85 °C

3.3 V RANGE LIMITS

MIN MAX

GTL 1.14 1.26

+

GTL

1.35 1.65

GTL 0.74 0.87

+

GTL

0.9 1.10

B port 0 V

Except B port 0 5.5

B port V

REF

+50 mV

Except B port 2.0

B port V

REF

–50 mV

Except A port 0.8

B port 40
A port 64

TT

1999 Sep 13

5

Philips Semiconductors Product specification

VOHHigh-level output voltage

A port

V

A port

V

Control pins

A

IIInput leakage current

4

A ort

I

Bus Hold current, A outputs

A

A-Port

B-Port

18-bit GTL/GTL+ to LVTTL/TTL bidirectional
latched translator (3-State)

DC ELECTRICAL CHARACTERISTICS (3.3 V "0.3 V RANGE)

SYMBOL PARAMETER TEST CONDITIONS

V

V

I

OFF

HOLD

I

I

PU/PD

I

CCH

I

CCL

I

CCZ

I

CCH

I

CCL

∆I

NOTES:

1. All typical values are at V

2. This is the increase in supply current for each LVTTL input at the specified voltage level other than V

3. This parameter is valid for any V
a transition time of 100 µsec is permitted. This parameter is valid for T

4. Unused pins at V

5. I

CCZ

Input clamp voltage VCC = 3.0 V; IIK = –18 mA –0.85 –1.2 V

IK

p

VCC = 3.0 to 3.6 V; IOH = –100 µA
VCC = 3.0 V; IOH = –32 mA

p

VCC = 3.0 V; IOL = 100 µA 0.07 0.2

Low–level output voltage

OL

VCC = 3.0 V; IOL = 16 mA
VCC = 3.0 V; IOL = 32 mA

p

VCC = 3.0 V; IOL = 64 mA 0.4 0.55
VCC = 3.0 V; IOL = 40 mA B port 0.4 0.5 V
VCC = 3.6 V; VI = VCC or GND
VCC = 0 or 3.6 V; VI = 5.5 V

p

VCC = 3.6 V; VI = 5.5 V
VCC = 3.6 V; VI = V

CC

I/O Data pins

p

A port

VCC = 3.6 V; VI = 0
VCC = 3.6 V; VI = VTT or GND B port ±5 µA

Output off current VCC = 0 V; VI or VO = 0 to 4.5 V 0.1 ±100 µA

VCC = 3 V; VI = 0.8 V 75 130

p

VCC = 3 V; VI = 2.0 V –75 –140

Current into an output in the

EX

High state when VO > V
Power up/down 3-State

output current

3

VO = 5.5 V; VCC = 3.0 V A port 10 125 µA

CC

VCC ≤ 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC
OE

= Don’t care
Outputs high 5.0 9.0
Outputs low 10.5 18.5

5

VCC = 3.6 V

Disabled

VI = GND or V

CC,

IO = 0
Outputs high 9.7 17.5
Outputs low 7.0 12.0

Additional supply current per

CC

is measured with outputs pulled up to VCC or pulled down to ground.

input pin

2

or GND.

CC

= 3.3 V and T

CC

CC

VCC = 3 V to 3.6 V; One input at VCC–0.6 V ,
Other inputs at VCC or GND

= 25°C.

amb

between 0 V and 1.2 V with a transition time of up to 10 msec. From V

= 25°C only.

amb

GTL16612

LIMITS

Temp = –40°C to +85°C UNIT

MIN TYP1MAX

VCC–0.2 V

2.0 2.3

or GND

CC

CC

= 1.2 V to VCC = 3.3 V ± 0.3 V

CC

0.25 0.4

0.3 0.5

0.1 ±1

0.1 10

0.1 20

0.5 10

0.1 -5

1.0 ±100 µA

6.0 11.5

0.04 0.2 mA

µ

µA

µ

mA

1999 Sep 13

6

Philips Semiconductors Product specification

UNIT

UNIT

18-bit GTL/GTL+ to LVTTL/TTL bidirectional
latched translator (3-State)

AC CHARACTERISTICS (A PORT)

GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 Ω; T

GTL16612 An Port

SYMBOL PARAMETER WAVEFORM MIN TYP

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PHZ

t

PZL

t

PLZ

Bn to An 2 1.6 3.0 5.0 1.6 3.0 5.0 ns
Bn to An 2 3.0 4.9 6.3 3.0 4.9 6.3 ns
LEBA to An 3 1.6 2.7 4.2 1.6 2.7 4.2 ns
LEBA to An 3 1.6 2.8 4.3 1.6 2.8 4.3 ns
CPBA to An 1 1.9 3.4 4.7 1.9 3.4 4.7 ns
CPBA to An 1 1.8 3.8 5.2 1.8 3.8 5.2 ns
OEBA to An 5 1.5 2.6 4.2 1.5 2.6 4.2 ns
OEBA to An 5 1.4 2.9 4.8 1.4 2.9 4.8 ns
OEBA to An 6 1.3 2.4 3.8 1.3 2.4 3.8 ns
OEBA to An 6 1.2 2.2 3.5 1.2 2.2 3.5 ns

NOTE:

1. T ypical values are at V

= 3.3 V, T

CC

= +25°C.

amb

= –40°C to +85°C.

amb

VCC = 3.3 V ±0.3 V VCC = 3.3 V ±0.3 V

V

REF

GTL GTL+

= 0.8 V V

1

MAX MIN TYP

REF

= 1.0 V

GTL16612

1

MAX

AC CHARACTERISTICS (B PORT)

GND = 0 V; tr = tf = 2.5 ns; CL = 30 pF; RL = 25 Ω; T

GTL16612 Bn Port

SYMBOL PARAMETER WAVEFORM MIN TYP

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

An to Bn 2 1.4 2.4 3.7 1.3 2.4 3.7 ns
An to Bn 2 1.3 2.5 4.0 1.4 2.6 4.2 ns
LEAB to Bn 3 1.7 3.0 4.4 1.8 3.0 4.6 ns
LEAB to Bn 3 2.1 3.5 5.4 2.3 3.6 5.5 ns
CPAB to Bn 1 1.8 3.1 4.5 1.9 3.1 4.8 ns
CPAB to Bn 1 2.3 3.6 5.4 2.4 3.8 5.8 ns
OEAB to Bn 7 1.1 2.1 3.3 1.4 2.0 3.5 ns
OEAB to Bn 7 1.6 2.8 4.4 1.0 2.9 4.5 ns

NOTE:

1. T ypical values are at V

= 3.3 V, T

CC

= +25°C.

amb

= –40°C to +85°C.

amb

VCC = 3.3 V ±0.3 V VCC = 3.3 V ±0.3 V

V

REF

GTL GTL+

= 0.8 V V

1

MAX MIN TYP

REF

= 1.0 V

1

MAX

1999 Sep 13

7

Philips Semiconductors Product specification

,g

,g

,g

,g

,g

,g

,g

,g

18-bit GTL/GTL+ to LVTTL/TTL bidirectional
latched translator (3-State)

AC SETUP REQUIREMENTS (3.3 V ±0.3 V RANGE)

A Port: GND = 0 V; Input tr = tf = 2.5 ns; CL = 50 pF; RL = 500 Ω; T
B Port: GND = 0 V; Input t

SYMBOL PARAMETER WAVEFORM

ts(H)
ts(L)
ts(H)
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
ts(H)
ts(L)
th(H)
th(L)
tw(H)
tw(L)

tw(H)

Setup time, High or Low
Bn to CPBA

Setup time, High or Low
An to CPAB

Hold time, High or Low
Bn to CPBA, or An to CPAB

Setup time, High or Low
Bn to LEBA, or An to LEAB

Hold time, High or Low
Bn to LEBA, or An to LEAB

Setup time, High or Low
CEAB to CPAB, or CEBA to CPBA

Hold time, High or Low
CEAB to CPAB, or CEBA to CPBA

Pulse width, High or Low
CPBA or CPAB

Pulse width, High
LEBA or LEAB

= tf = 2.5 ns; CL = 30 pF; RL = 25 Ω; V

r

= –40°C to +85°C; V

amb

= 0.8 V or 1.0 V.

REF

= 0.8 V or 1.0 V.

REF

4 1.5 ns
4 1.5 ns
4 2.0 ns
4 3.0 ns
4 1.0 ns
4 1.0 ns
4 1.0 ns
4 1.0 ns
4 1.5 ns
4 1.5 ns
4 1.0 ns
4 1.0 ns
4 1.5 ns
4 1.0 ns
4 2.0 ns
4 2.0 ns

3 1.5 ns

GTL16612

LIMITS

VCC = 3.3 V ±0.3 V

MIN MAX

UNIT

1999 Sep 13

8

Philips Semiconductors Product specification

18-bit GTL/GTL+ to LVTTL/TTL bidirectional

GTL16612

latched translator (3-State)

AC WAVEFORMS

VM = 1.5 V at VCC w 3.0 V. VM = 1.5 V for A ports and control pins; VM = 0.8 V for B ports in GTL mode; VM = 1.0 V for B ports in GTL+ mode.
V

= VOL + 0.3 V at VCC w 3.0 V.

X

= VOH – 0.3 V at VCC w 3.0 V.

V

Y

1/f

CPBA or

CPAB

An or Bn

MAX

V

M

t

tW(L)

PHL

tW(H)

V

M

V

M

t

PLH

V

M

3.0 V or VCC,
whichever is
less

0V

V

OH

V

OL

SW00181

Waveform 1. Propagation delay, clock input to output, clock

pulse width, and maximum clock frequency

3.0V or VCC,
whichever is

An or Bn

An or Bn

V

M

t

PLH

V

M

t

PHL

V

M

V

less

0V

V

OH

M

V

OL

SW00176

Waveform 2. Propagation delay, transparent mode

OEBA

V

M

t

PHZ

An or Bn

V

M

t

PZH

V

M

Waveform 5. 3-State output enable time to high level

and output disable time from high level

OEBA

An or Bn

V

M

t

PZL

V

M

V

M

t

PLZ

Waveform 6. 3-State output enable time to low level

and output disable time from low level

3.0 V or VCC,
whichever is
less

V

OH

V

Y

SW00223

3.0 V or VCC,
whichever is
less

V

X

V

OL

SW00224

LEAB or

LEBA

An or Bn

V

M

tW(H)

t

PHL

V

M

V

M

V

M

t

PLH

Waveform 3. Propagation delay, enable to output,

and enable pulse width

An or Bn
CEAB or CEBA

V

VMV

t

(H) th(H)

S

CPAB or CPBA,
LEAB or LEBA

M

(L)

t

S

V

M

V

M

M

t

V

M

Waveform 4. Data setup and hold times

V

M

(L)

h

3.0V or VCC,
whichever is
less

0V

V

OH

V

OL

SW00177

3.0 V or V

CC

whichever is
less

0V

3.0 V or VCC,
whichever is
less

0V

SW00222

OEAB

Bn

V

M

t

PLH

V

M

V

M

t

PHL

V

M

3.0 V or VCC,
whichever is
less

V

OL

SW00495

Waveform 7. Output enable time on open collector output

with pullup

,

1999 Sep 13

9

Philips Semiconductors Product specification

18-bit GTL/GTL+ to LVTTL/TTL bidirectional
latched translator (3-State)

TEST CIRCUIT

R

=

L

500 Ω

RL =
500 Ω

6.0 V or VCC x 2

Open

GND

V

V

PULSE

GENERATOR

IN

D.U.T.

R

T

Test Circuit for A Outputs

FROM OUTPUT

UNDER TEST

= 30 pF

C

(INCLUDES PROBE AND JIG CAPACITANCE)

L

Load Circuit for B Outputs

CC

V

OUT

C

1.2 V

25 Ω

TEST POINT

L

90%

NEGATIVE
PULSE

POSITIVE
PULSE

10%

GTL16612

t

W

V

M

10% 10%

t

(tF)

THL

t

(tR)t

TLH

90% 90%

V

M

t

W

90%

V

M

0 V

(tR)

t

TLH

(tF)

THL

V

M

10%

0 V

V

IN

V

IN

SWITCH POSITION

TEST SWITCH

t

PLZ/tPZL

t

PLH/tPHL

t

PHZ/tPZH

6 V

Open

GND

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.
C

= Load capacitance includes jig and probe capacitance:

L

See AC CHARACTERISTICS for value.

= Termination resistance should be equal to Z

R

T

pulse generators.

OUT

of

FAMILY

74GTL16

INPUT PULSE REQUIREMENTS

Amplitude Rep. Rate t

3.0 V or V
whichever

CC

v10 MHz 500 ns

is less

W

t

R

v2.5 ns v2.5 ns

t

F

SW00255

1999 Sep 13

10

Philips Semiconductors Product specification

18-bit GTL/GTL+ to LVTTL/TTL bidirectional

GTL16612

latched translator (3-State)

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm SOT364-1

1999 Sep 13

11

Philips Semiconductors Product specification

18-bit GTL/GTL+ to LVTTL/TTL bidirectional
latched translator (3-State)

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

GTL16612

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1999

All rights reserved. Printed in U.S.A.

Date of release: 09-99

Document order number: 9397-750-06414




1999 Sep 13

12