Datasheet GT28F160B3-B120 Datasheet (Intel Corporation)

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

SMART 3 ADVANCED BOOT BLOCK

4-MBIT (256K X 16), 8-MBIT (512K X 16),

16-MBIT (1024K X 16)

FLASH MEMORY FAMILY

Flexible SmartVoltage Technology

2.7V–3.6V Program/Erase

2.7V–3.6V Read Operation 12V VPP Fast Production Programming

2.7V or 1.8V I/O Option Reduces Overall System Power

Optimized Block Sizes

Eight 4-KW Blocks for Data, Top or Bottom Locations Up to Thirty-One 32-KW Blocks for Code

High Performance

2.7V–3.6V: 120 ns Max Access Time

Block Locking

VCC-Level Control through WP#

Low Power Consumption

20 mA Maximum Read Current

Absolute Hardware-Protection

VPP = GND Option VCC Lockout Voltage

Extended Temperature Operation

–40°C to +85°C

WORD-WIDE

28F400B3, 28F800B3, 28F160B3

Supports Code Plus Data Storage

Optimized for FDI, Flash Data Integrator Software Fast Program Suspend Capability Fast Erase Suspend Capability

Extended Cycling Capability

10,000 Block Erase Cycles

Automated Word Program and Block Erase

Command User Interface Status Registers

SRAM-Compatible Write Interface

Automatic Power Savings Feature

Reset/Deep Power-Down

1 µA ICCTypical Spurious Write Lockout

Standard Surface Mount Packaging

48-Ball µBGA* Package 48-Lead TSOP Package

Footprint Upgradeable

Upgradeable from 2-, 4- and 8-Mbit Boot Block

ETOX™ V (0.4 µ) Flash Technology

PRELIMINARY

The new Smart 3 Advanced Boot B lock , m anufac tured on I ntel’ s l ates t 0. 4µ tec hnology, represent s a feat urerich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability (2.7V read, program and erase) with high-speed, low-power operation. Several new features have been added, including the ability to drive the I /O at 1.8V, which significantly reduces system active power and interfaces to 1.8V cont rollers. A new bloc king schem e enables code and data s torage within a si ngle device. Add to this the Intel-dev eloped Flash Data Integrator (FDI) software and you hav e the most cost-effect ive, monolithic code plus dat a storage solution on the market today . Smart 3 Advanced Boot B lock Word-Wide products will be available in 48-lead TSOP and 48-ball µBGA* packages. Additional information on this product family can be obtained by accessing Intel’s WWW page: http://www.intel.com/design/flcomp.

May 1997 Order Number: 290580-002

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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. The 28F400B3, 28F800B3, 28F160B3 may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are available on request. *Third-party brands and names are the property of their respective owners. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from:

Intel Corporation P.O. Box 7641 Mt. Prospect, IL 60056-7641

or call 1-800-879-4683

or visit Intel’s website at http:\\www.intel.com

brands and names are the property of their respective owners

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

PAGE PAGE

1.0 INTRODUCTION .............................................5

1.1 Smart 3 Advanced Boot Block Flash

Memory Enhancements ..............................5

1.2 Product Overview.........................................6

2.0 PRODUCT DESCRIPTION..............................6

2.1 Package Pinouts..........................................7

2.2 Block Organization.....................................11

2.2.1 Parameter Blocks................................11

2.2.2 Main Blocks.........................................11

3.0 PRINCIPLES OF OPERATION .....................14

3.1 Bus Operation............................................14

3.1.1 Read....................................................15

3.1.2. Output Disable....................................15

3.1.3 Standby...............................................15

3.1.4 Deep Power-Down / Reset..................15

3.1.5 Write....................................................15

3.2 Modes of Operation....................................15

3.2.1 Read Array..........................................16

3.2.2 Read Intelligent Identifier.....................17

3.2.3 Read Status Register ..........................17

3.2.4 Program Mode.....................................18

3.2.5 Erase Mode.........................................19

3.3 Block Locking.............................................26

3.3.1 V

3.3.2 WP# = V

3.3.3 WP# = V

3.4 V

= VIL for Complete Protection .......26

for Block Locking................26

for Block Unlocking............26

Program and Erase Voltages ..............26

3.5 Power Consumption...................................26

3.5.1 Active Power .......................................26

3.5.2 Automatic Power Savings (APS) .........27

3.5.3 Standby Power....................................27

3.5.4 Deep Power-Down Mode.....................27

3.6 Power-Up/Down Operation.........................27

3.6.1 RP# Connected to System Reset ........27

3.6.2 V

3.7 Power Supply Decoupling ..........................28

3.7.1 V

4.0 ABSOLUTE MAXIMUM RATINGS................29

5.0 OPERATING CONDITIONS (V

3.6V).............................................................29

5.1 DC Characteristics: V

6.0 OPERATING CONDITIONS (V

2.2V).............................................................34

6.1 DC Characteristics: V

7.0 AC CHARACTERISTICS...............................39

7.1 Reset Operations .......................................43

APPENDIX A: Ordering Information .................45

APPENDIX B: Write State Machine

Current/Next States.....................................46

APPENDIX C: Access Speed vs. Capacitive

Load.............................................................47

APPENDIX D: Architecture Block Diagram ......48

APPENDIX E: Additional Information ...............49

, VPP and RP# Transitions.............27

Trace On Printed Circuit Boards ...28

= 2.7V–

CCQ

= 2.7V–3.6V.......30

CCQ

= 1.8V–

CCQ

= 1.8V–2.2V.......34

CCQ

PRELIMINARY

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

REVISION HISTORY

Number Description

-001 Original version

-002 Section 3.4, Updated Figure 9: Automated Block Erase Flowchart Updated Figure 10: Erase Suspend/Resume Flowchart (added program op. to table) Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)

maximum specification change from ±25 µA to ±50 µA

PPR

Program and Erase Suspend Latency specification change Updated Appendix A: Ordering Information (included 8M and 4M information) Updated Figure, Appendix D: Architecture Block Diagram (Block info. in Words not

bytes) Minor wording changes

VPP Program and Erase Voltages

, added

PRELIMINARY

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1.0 INTRODUCTION

This preliminary datasheet contains the specifications for the Advanced Boot Block flash memory family, which is optimized for low power, portable systems. This family of products features

1.8V–2.2V or 2.7V–3.6V I /Os and a low V

operating range of 2.7V–3.6V for read and program/erase operations. In addit ion thi s fam ily i s capable of fast programming at 12V. Throughout this document, the term “2.7V” refers to the full voltage range 2.7V–3.6V (except where noted otherwise) and “V Section 1 and 2 provides an overv iew of the flash memory family incl uding applications, pinouts and pin descriptions. Section 3 desc ribes the memory organization and operation for these products. Finally, Sections 4, 5, 6 and 7 contain the operating specifications.

= 12V” refers to 12V ±5%.

CC/VPP

1.1 Smart 3 Advanced Boot Block Flash Memory Enhancements

The new 4-Mbit, 8-Mbit, and 16-Mbit Smart 3 Advanced Boot Block flash memory provides a

Table 1. Smart 3 Advanced Boot Block Feature Summary

Feature 28F160B3 Reference

VCC Read Voltage 2.7V– 3.6V Table 9, Table 12 V

I/O Voltage 1.8V–2.2V or 2.7V– 3.6V Table 9, Table 12

CCQ

VPP Program/Erase Voltage 2.7V– 3.6V or 11.4V– 12.6V Table 9, Table 12 Bus Width 16 bit Table 2 Speed 120 ns Table 15 Memory Arrangement 256-Kbit x 16 (4-Mbit), 512-Kbit x 16 (8-Mbit),

Blocking (top or bottom) Eight 4-Kword parameter blocks (4/8/16) &

Locking WP# locks/unlocks parameter blocks

Operating Temperature Extended: –40°C to +85°C Table 9, Table 12 Program/Erase Cycling 10,000 cycles Table 9, Table 12 Packages 48-Lead TSOP, 48-Ball µBGA* CSP Figures 1, 2, 3,

1024-Kbit x 16 (16-Mbit)

Seven 32-Kword blocks (4-Mbit) Fifteen 32-Kword blocks (8-Mbit) Thirty-one 32-Kword main blocks (16-Mbit)

All other blocks protected using V

convenient upgrade from and/or compatibility to previous 4-Mbit and 8-Mbit Boot Block products. The Smart 3 product functi ons are s imilar t o lower density products in both command sets and operation, providing simil ar pi nouts to ease density upgrades.

The Smart 3 Advanced Boot Block flash memory features

• Enhanced blocking for easy segmentation of code and data or additional design flexibility

• Program Suspend command which permits program suspend to read

• WP# pin to lock and unlock t he upper two (or lower two, depending on location) 4-Kword blocks

• V

• Maximum program time specification for

input for 1.8V–2.2V on all I/Os. See

CCQ

Figure 1-4 for pinout diagrams and V location

improved data storage.

Section 2.2 Figures 5 and 6

switch

Section 3.3 Table 8

and 4

CCQ

PRELIMINARY

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

1.2 Product Overview

Intel provides the most flexible voltage solution in the flash industry, providing three discrete volt age supply pins: V swing, and V Discrete supply pins allow system designers to use the optimal voltage lev els for t heir design. All Sm art 3 Advanced Boot Block flash memory products provide program/erase capability at 2.7V or 12V and read with V read from the flash memory a l arge percentage of the time, 2.7V V substantial power savings. The 12V V maximizes program and erase performanc e during production programming.

The Smart 3 Advanced Boot Block flash memory products are high-performance devices with low power operation. The available densi ties for wordwide devices (x16) are

a. 4-Mbit (4,194,304-bit) flash memory

organized as 256-Kwords of 16 bits each

b. 8-Mbit (8,388,608-bit) flash memory

organized as 512-Kwords of 16 bits each

c. 16-Mbit (16,777,216-bit) flash memory

organized as 1024-Kwords of 16 bits each.

For byte-wide devices (x8) see the

Advanced Boot Block Byte-Wide Flash Memory Family

datasheet.

The parameter blocks are located at either the top (denoted by -T suffix) or the bot tom (-B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The upper two (or lower two) parameter blocks can be locked to provide complete code security for system initialization code. Locking and unlocking is controlled by WP# (see Section 3.3 for details).

The Command User Interface (CUI) s erves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or word program completion and status.

for read operation, V

for program and erase operation.

at 2.7V. Since many designs

operation can provide

for output

CCQ

option

Smart 3

Program and erase automation allows program and erase operations to be executed using an indust rystandard two-write command sequence t o the CUI. Data writes are performed in word increments. Each word in the flash memory can be program m ed independently of other memory locations; every erase operation erases all locations within a bl ock simultaneously. Program suspend allows system software to suspend the program comm and in order to read from any other block. Erase suspend allows system software to suspend the block erase command in order to read from or program data to any other block.

The Smart 3 Advanced Boot B lock flas h memory is also designed with an Automatic Power Savings (APS) feature which minimizes system current drain, allowing for very low power designs. This mode is entered immediately following the completion of a read cycle.

When the CE# and RP# pins are at V

, the I

CMOS standby mode is enabled. A deep powerdown mode is enabled when the RP# pin is at GND, minimizing power consum ption and providing write protection. I

1 µA typical (2.7V V t

is required from RP# switching high until

PHQV

current in deep power-down is

). A minimum reset time of

outputs are valid to read attempts. With RP# at GND, the WSM is reset and Status Register is cleared. Section 3.5 c ontains additional inf ormation on using the deep power-down feature, along wi th other power consumption issues.

The RP# pin provides additional protection agai nst unwanted command writes that may occur during system reset and power-up/down sequences due to invalid system bus conditions (see Section 3.6).

Refer to the DC Characteristi cs Table, Sec tions 5.1 and 6.1, for complete current and voltage specifications. Refer to the AC Characteristics Table, Section 7.0, for read, program and erase performance specifications.

2.0 PRODUCT DESCRIPTION

This section explains device pin description and package pinouts.

PRELIMINARY

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

2.1 Package Pinouts

The Smart 3 Advanced Boot B lock flas h memory is available in 48-lead TSOP (see Figure 1) and 48ball µBGA packages (see Figures 2-4). In Figure 1, pin changes from one density to the next are circled. Both pack ages, 48-lead TSOP and 48-ball

µBGA

package, are 16-bits wide and fully upgradeable across product densities (f rom 4 Mb to 16 Mb).

8F400B3

NC NC

WE#

RP#

WP#

NC NC

28F800B3

NC NC

WE#

RP#

VPPV

WP#

A A A A A A A A

NC NC

WE#

RP#

WP#

A A A A A A A A A A

28F400B328F800B3

CCQ

GND DQ DQ DQ DQ DQ DQ DQ DQ

DQ DQ DQ DQ DQ DQ DQ DQ OE# GND CE# A

CCQ

GND DQ

OE# GND CE# A

0580_01

15 14 13 12 11 10 9 8

19 18 17

7 6 5 4 3 2 1

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

16-Mbit

Advanced Boot Block

48-Lead TSOP

12 mm x 20 mm

TOP VIEW

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

CCQ

GND DQ DQ DQ DQ DQ DQ DQ DQ

DQ DQ DQ DQ DQ DQ DQ DQ OE# GND CE# A

15 7 14 6 13 5 12

11 3 10

2 9 1 8 0

Figure 1. 48-Lead TSOP Package

PRELIMINARY

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

1234 567 8

CCQ

WE# RP# NC A

WP# NC A

CE# A

GND

GND D

OE#

NOTE:

Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades. Routing is not recommended in this area.

Figure 2. 4-Mbit 48-Ball µBGA* Chip Size Package

1234 567 8

GND D

CCQ

WE# RP# A

WP# NC A

CE# A

GND

OE#

NOTE:

Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades. Routing is not recommended in this area.

Figure 3. 8-Mbit 48-Ball µBGA* Chip Size Package

PRELIMINARY

0580_02

0580_03

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

12345678

CCQ

GND D

WE# RP# A

WP# A

CE# A

GND

OE#

NOTE:

Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades. Routing is not recommended in this area.

Figure 4. 16-Mbit 48-Ball µBGA* Chip Size Package

(Top View, Ball Down)

0580_04

PRELIMINARY

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

The pin descriptions table details the usage of each device pin.

Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions

Symbol Type Name and Function

A0–A

DQ0–DQ7INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and

DQ8–DQ15INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and

CE# INPUT CHIP ENABLE: Activates the internal control logic, input buffers,

OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data

WE# INPUT WRITE ENABLE: Controls writes to the Command Register and memory

RP# INPUT RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to

WP# INPUT WRITE PROTECT: Provides a method for locking and unlocking the two

INPUT

ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle.

28F400B3: A[0-17], 28F800B3: A[0-18], 28F160B3: A[0-19]

WE# cycle during a Program command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. Outputs array, Intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled.

WE# cycle during a Program command. Data is internally latched. Outputs array and intelligent identifier data. The data pins float to tri-state when the chip is de-selected.

decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. If CE# and RP# are high, but not at a CMOS high level, the standby current will increase due to current flow through the CE# and RP# inputs.

buffers during an array or status register read. OE# is active low.

array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse.

control reset/deep power-down mode.

When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State

Machine, and draws minimum current. When RP# is at logic high, the device is in standard operation.

When RP# transitions from logic-low to logic-high, the device defaults to the read array mode.

lockable parameter blocks. When WP# is at logic low, the lockable blocks are locked,

preventing program and erase operations to those blocks. If a program or erase operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed.

When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased.

See Section 3.3 for details on write protection.

PRELIMINARY

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions (Continued)

Symbol Type Name and Function

VCCQ INPUT OUTPUT VCC: Enables all outputs to be driven to 2.0V ±10% while the

GND GROUND: For all internal circuitry. All ground inputs must be

NC NO CONNECT: Pin may be driven or left floating.

is at 2.7V. When this mode is used, the VCC should be regulated to

2.7V–2.85V to achieve lowest power operation (see Section 6.1: DC Characteristics: V

This input may be tied directly to V See the DC Characteristics for further details.

DEVICE POWER SUPPLY: 2.7V–3.6V PROGRAM/ERASE POWER SUPPLY: For erasing memory array

blocks or programming data in each block, a voltage of either 2.7V–3.6V or 12V ± 5% must be applied to this pin. When V are locked and protected against Program and Erase commands.

Applying 11.4V-12.6V to V cycles on the main blocks and 2500 cycles on the parameter blocks. V

may be connected to 12V for a total of 80 hours maximum (see

Section 3.4 for details).

connected.

= 1.8V–2.2V).

CCQ

(2.7V–3.6V).

< V

can only be done for a maximum of 1000

PPL

all blocks

2.2 Block Organization

The Smart 3 Advanced Boot Block is an asymmetrically-blocked architecture that enables system integration of code and data within a single flash device. Each block can be erased independently of the others up t o 10,000 times . For the address locations of each block, see the memory maps in Figure 5 (top boot blocking) and Figure 6 (bottom boot blocking).

PRELIMINARY

2.2.1 PARAMETER BLOCKS

The Smart 3 Advanced Boot Block flash memory architecture includes parameter blocks to facilitate storage of frequently updated small parameters (e.g., data that would normally be stored in an EEPROM). By using software techniques, t he wordrewrite functionality of EEPROMs can be emulated. Each 4-/8-/16-Mbit device contai ns eight parameter blocks of 4-Kwords (4,096-words) each.

2.2.2 MAIN BLOCKS

After the parameter blocks, the remainder of the array is divided into equal size main blocks for data or code storage. Each 16-Mbit device contains thirty-one 32-Kword (32,768-word) blocks. Each 8-Mbit device contains fifteen 32-Kword blocks. Each 4-Mbit device contains seven 32-Kword blocks.

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

16-Mbit Advanced Boot

FFFFF FF000

FEFFF FE000

FDFFF FD000

FCFFF FC000

FBFFF FB000

FAFFF FA000

F9FFF

F9000

F8FFF

F8000

F7FFF

F0000

EFFFF E8000

E7FFF E0000 DFFFF D8000 D7FFF D0000 CFFFF C8000 C7FFF C0000

BFFFF B8000

B7000 B0000

AFFFF A8000

A7FFF A0000

9FFFF

98000

97FFF

90000

8FFFF

88000

87FFF

80000

7FFFF

78000

77FFF

70000

6FFFF

68000

67FFF

60000

5FFFF

58000

57FFF

50000

4FFFF

48000

47FFF

40000

3FFFF

38000

37FFF

30000

2FFFF

28000

27FFF

20000

1FFFF

18000

17FFF

10000

0FFFF

08000

07FFF

00000

Block

4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block

32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block

8-Mbit Advanced Boot

38 37

36 35 34 33 32 31 30

25 24

13 12

7FFFF 7F000

7EFFF 7E000

7DFFF

7D000

7CFFF

7C000 7BFFF

7B000 7AFFF

7A000 79FFF

79000 78FFF 78000 77FFF

70000 6FFFF

68000 67FFF

60000 5FFFF

58000 57FFF

50000 4FFFF

48000 47FFF

40000 3FFFF

38000 37FFF

30000 2FFFF

28000 27FFF

20000 1FFFF

18000 17FFF

10000 0FFFF 08000 07FFF 00000

Block

4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block

22 21

20 19 18 17 16 15 14

4-Mbit Advanced Boot

3FFFF 3F000

3EFFF 3E000

3DFFF 3D000

3CFFF 3C000

3BFFF 3B000

3AFFF 3A000

39FFF

39000

38FFF

38000

37FFF

30000

2FFFF

28000

27FFF

20000

1FFFF

18000

17FFF

10000

0FFFF

08000

07FFF

00000

Block

4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block

32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block

14 13

12 11 10

9 8 7

6 5

0580_05

Figure 5. 4-/8-/16-Mbit Advanced Boot Block Word-Wide Top Boot Memory Maps

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

16-Mbit Advanced Boot

FFFFF F8000 F7FFF F0000 EFFFF

E8000 E7FFF

E0000 DFFFF

D8000 D7FFF

D0000 CFFFF

C8000 C7FFF C0000 BFFFF

B8000 B7FFF

B0000 AFFFF A8000 A7FFF

A0000 9FFFF

98000

97FFF

90000

8FFFF

88000

87FFF

80000

7FFFF

78000

77FFF

70000

6FFFF

68000

67FFF

60000

5FFFF

58000

57FFF

50000

4FFFF

48000

47FFF

40000

3FFFF

38000

37FFF

30000

2FFFF

28000

27FFF

20000

1FFFF

18000

17FFF

10000

0FFFF

08000

07FFF

07000

06FFF

06000

05FFF

05000

04FFF

04000

03FFF

03000

02FFF

02000

01FFF

01000

00FFF

00000

Block

32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block

4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block

8-Mbit Advanced Boot

7FFFF

78000

77FFF

70000

6FFFF

68000

67FFF

60000

5FFFF

58000

57FFF

50000

4FFFF

48000

47FFF

40000

3FFFF

38000

37FFF

30000

2FFFF

28000

27FFF

20000

1FFFF

18000

17FFF

10000

0FFFF

08000

07FFF

07000

06FFF

06000

05FFF

05000

04FFF

04000

03FFF

03000

02FFF

02000

01FFF

01000

00FFF

00000

Block

32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block

32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block

4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block

22 21

20 19 18 17 16 15 14

4-Mbit Advanced Boot

3FFFF 38000 37FFF

30000 2FFFF

28000 27FFF

20000 1FFFF

18000 17FFF

10000 0FFFF

08000 07FFF 07000

06FFF 06000

05FFF 05000

04FFF 04000

03FFF 03000

02FFF 02000

01FFF 01000 00FFF

00000

Block

32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block 32-Kword Block

4-Kword Block 4-Kword Block

4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block 4-Kword Block

14 13

12 11 10

9 8 7

0580_06

Figure 6. 4-/8-/16-Mbit Advanced Boot Block Word-Wide Top Boot Memory Maps

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

3.0 PRINCIPLES OF OPERATION

Flash memory combines EEPROM functionality with in-circuit electrical program and erase capability. The Smart 3 Advanc ed Boot Block flash memory family utilizes a Command User Interface (CUI) and automated algorithms to s impli fy program and erase operations. The CUI allows for 100% CMOS-level control inputs, fixed power supplies during erasure and programming, and maximum EEPROM compatibility.

When V following commands successfully: Read Array, Read Status Register, Clear Status Register and Read Intelligent Identifier. The device provides standard EEPROM read, standby and output disable operations. Manufac turer identification and device identification data c an be accessed through the CUI. In addition, 2.7V or 12V on V program and erase of the device. All functions

Read 1,2,3 V Output Disable 2 V Standby 2 V Deep Power-Down 2,9 V Intelligent Identifier (Mfr.) 2,4 V Intelligent Identifier (Dvc.) 2,4,5 V Write 2,6,7,8V

< V

, the device will only execute the

PPLK

allows

Table 3. Bus Operations for Word-Wide Mode

Mode Notes RP# CE# OE# WE# WP# A0V

X X X X X X High Z

associated with altering memory contents, namely program and erase, are accessible via the CUI. The internal Write State Mac hi ne (WS M) completely automates program and erase operati ons while the CUI signals the start of an operation and the stat us register reports status . The CUI handles the WE# interface to the data and address latches, as well as system status requests during WSM operation.

3.1 Bus Operation

Smart 3 Advanced Boot Block flash memory devices read, program and erase in-system via the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash component: CE#, OE#, WE# and RP#. These bus operations are summarized in Table 3.

XXXD X X X High Z

X X X X X High Z

XVILX 0089 H XVIHX See Table 5 XXV

PPH

0–15

OUT

NOTES:

1. Refer to DC Characteristics.

2. X must be V

3. See DC Characteristics for V

4. Manufacturer and device codes may also be accessed via a CUI write sequence, A

5. See Table 5 for device IDs.

6. Refer to Table 6 for valid D

7. Command writes for block erase or word program are only executed when V

8. To program or erase the lockable blocks, hold WP# at V

9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.

, VIH for control pins and addresses, V

, V

PPH1

, V

PPH2

PPLK

during a write operation.

PPLK

voltages.

, V

or V

PPH1

PPH2

. See Section 3.3.

for VPP.

= V

1–A19

PPH1

= X

or V

PPH2

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

3.1.1 READ

The flash memory has three read modes av ailable: read array, read identifier, and read status. These modes are accessible independent of the V voltage. The appropriate read mode c om m and must be issued to the CUI to enter the corresponding mode. Upon initial device power-up or after exit from deep power-down mode, the device automatically defaults to read array mode.

CE# and OE# must be driven active to obtain dat a at the outputs. CE# is the device s election control; when active it enables the flash memory device. OE# is the data output (DQ

drives the selected m emory data onto the I/O bus. For all read modes, WE# and RP# must be at V Figure 15 illustrates a read cycle.

3.1.2 OUTPUT DISABLE

With OE# at a logic-high level (V outputs are disabled. Output pins DQ placed in a high-impedance state.

3.1.3 STANDBY

Deselecting the device by bri nging CE# to a logichigh level (V which substantially reduces device power consumption. In standby, outputs DQ placed in a high-impedance state independent of OE#. If deselected during program or erase operation, the device cont inues to consume active power until the program or erase operation is complete.

) places the device in standby mode,

–DQ15) control and it

), the device

–DQ15 are

–DQ

are

After return from power-down, a time t required until the initial mem ory access out puts are valid. A delay (t return from power-down before a write sequence can be initiated. After this wake-up interval, normal

operation is restored. The CUI resets t o read array mode, and the status register is set to 80H (ready).

If RP# is taken low for time t or erase operation, the operation will be aborted and the memory contents at the aborted location are no longer valid. After returni ng from an aborted operation, time t before a read or write operation is initiated respectively.

3.1.5 WRITE

A write is any command t hat alters the content s of the memory array. There are two write c ommands: Program (40H) and Erase (20H). Writing either of these commands to the internal Command User Interface (CUI) initiates a sequence of internallytimed functions that culminate in the c ompletion of the requested task (unless that operat ion is aborted by either RP# being driven to V appropriate suspend command).

The Command User Interface does not occupy an addressable memory location. Instead, commands are written into the CUI using standard microprocessor write timings when WE# and CE# are low, OE# = V data (command) are presented. The command is latched on the rising edge of the f irst WE# or CE# pulse, whichever occurs first. Figure 16 illustrates a write operation.

or t

PHWL

or t

PHQV

, and the proper address and

) is required after

PHEL

during a program

PLPH

PHWL/tPHEL

PHQV

must be met

for t

PLRH

or an

3.1.4 DEEP POWER-DOWN / RESET

RP# at V sometimes referred to as reset mode.

From read mode, RP# going low for time t accomplishes the following:

1. deselects the memory

2. places output drivers in a high-impedance

initiates the deep power-down mode,

state

PLPH

PRELIMINARY

Device operations are selected by writing specific commands into the CUI. Table 4 defines the available commands. A ppendix B provides det ailed information on moving between t he different modes of operation.

3.2 Modes of Operation

The flash memory has three read modes and two write modes. The read modes are read array, read identifier, and read status. The write modes are program and block erase. Three additional modes

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

(erase suspend to program, erase sus pend to read and program suspend to read) are available only during suspended operations. These modes are

When the device is in the read array mode, four control signals must be c ontrolled to obtain data at

the outputs. reached using the commands summarized in Table 4. A comprehensive chart showing the state transitions is in Appendix B.

3.2.1 READ ARRAY

When RP# transitions from V

(reset) to VIH, the

device will be in the read array mode and will respond to the read control inputs (CE#, address

• WE# must be logic high (V

• CE# must be logic low (V

• OE# must be logic low (V

• RP# must be logic high (V

)

In addition, the address of the desired l ocat ion mus t

be applied to the address pins. inputs, and OE#) without any commands being written to the CUI.

If the device is not in read array mode, as would be

the case after a program or erase operation, the

Read Array command (FFH) must be written to t he

CUI before array reads can take place.

Table 4. Command Codes and Descriptions

Code Device Mode Description

00 Invalid/

Reserved

Unassigned commands that should not be used. Intel reserves the right to redefine these codes for future functions.

FF Read Array Places the device in read array mode, such that array data will be output on the

data pins.

40 Program

Set-Up

This is a two-cycle command. The first cycle prepares the CUI for a program operation. The second cycle latches addresses and data information and initiates the WSM to execute the Program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read Array command is required after programming to read array data. See Section 3.2.4.

10 Alternate

(See 40H/Program Set-Up)

Program Set-Up

20 Erase

Set-Up

Prepares the CUI for the Erase Confirm command. If the next command is not an Erase Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,” (b) place the device into the read status register mode,

and (c) wait for another command. See Section 3.2.5.

D0 Program

Resume

Erase Resume/

Erase Confirm

If the previous command was an Erase Set-Up command, then the CUI will close the address and data latches, and begin erasing the block indicated on the address pins. If a program or erase operation was previously suspended, this command will resume that operation.

During program/erase, the device will respond only to the Read Status Register, Program Suspend/Erase Suspend commands and will output status register data when CE# or OE# is toggled.

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Page 17

E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

(

Table 4. Command Codes and Descriptions (Continued)

Code Device Mode Description

B0 Program

Suspend

Erase

Suspend

70 Read Status

50 Clear Status

90 Intelligent

Identifier

NOTE:

See Appendix B for mode transition information.

Issuing this command will begin to suspend the currently executing program/erase operation. The status register will indicate when the operation has been successfully suspended by setting either the program suspend (SR.2) or erase suspend (SR.6) and the WSM Status bit (SR.7) to a “1” (ready). The

WSM will continue to idle in the SUSPEND state, regardless of the state of all input control pins except RP#, which will immediately shut down the WSM and the remainder of the chip if it is driven to V

This command places the device into read status register mode. Reading the device will output the contents of the status register, regardless of the address presented to the device. The device automatically enters this mode after a program or erase operation has been initiated. See Section 3.2.3.

The WSM can set the Block Lock Status (SR.1) , VPP Status (SR.3), Program Status (SR.4), and Erase Status (SR.5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this command clears those bits to “0.”

Puts the device into the intelligent identifier read mode, so that reading the device will output the manufacturer and device codes (A

= 1 for device, all other address inputs are ignored). See Section 3.2.2.

. See Sections 3.2.4.1 and 3.2.5.1.

= 0 for manufacturer,

3.2.2 READ INTELLIGENT IDENTIFIER

To read the manufacturer and device codes, the device must be in read intelligent identifier mode, which can be reached by writing the Intelligent Identifier command (90H). Once in intelligent identifier mode, A identification code and A code. See Table 5 for product signatures. To return to read array mode, write the Read Array comm and (FFH).

Table 5. Intelligent Identifier Table

Size Mfr. ID -T

4-Mbit 0089H 8894H 8895H 8-Mbit 0089H 8892H 8893H 16-Mbit 0089H 8890H 8891H

= 0 outputs the manufacturer’s

= 1 outputs the device

Device ID

(Top Boot)

-B

Bottom

Boot)

PRELIMINARY

3.2.3 READ STATUS REGISTER

The device status register indicates when a

program or erase operation is complete, and the

success or failure of that operation. To read the

status register issue the Read Status Register

(70H) command to the CUI. This causes all

subsequent read operations to output dat a from the

status register until anot her command is written to

the CUI. To return to reading from the array, iss ue

the Read Array (FFH) command.

The status register bits are output on DQ

The upper byte, DQ

Read Status Register command.

The contents of the st atus register are latched on

the falling edge of OE# or CE#. This prevents

possible bus errors which might occur if status

OE# must be toggled with each subsequent s tatus

read, or the status register will not indicate

completion of a program or erase operation.

–DQ15, outputs 00H during a

–DQ7.

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

When the WSM is active, SR.7 will indicate the status of the WSM; t he remaining bits in the st atus register indicate whether or not the WSM was successful in performi ng the desired operation (see Table 7).

3.2.3.1 Clearing the Status Register

The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6 and 7 to “0,” but cannot clear status bits 1 or 3 through 5 to “0.” Becaus e bits 1, 3, 4 and 5 indicate various error conditions, these bits can only be cleared by the controlling CPU t hrough the use of the Clear Status Register (50H) command. By allowing the system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the status register to determine if an error occurred during that series. Clear the Status Regist er before beginning another command or sequence. Note, agai n, that the Read Array command must be issued before dat a can be read from the memory array.

3.2.4 PROGRAM MODE

Programming is executed using a two-write sequence. The Program Setup command (40H) is written to the CUI foll owed by a sec ond write which specifies the address and data to be programmed. The WSM will execute the following sequence of internally timed events:

1. Program the desired bits of the addressed

memory.

2. Verify that the desired bits are sufficiently

programmed.

Programming of the memory res ults in spec ific bits within an address location being changed t o a “0.” I f the user attempts to program “1”s, there will be no change of the memory cell contents and no error occurs.

The status register indicates programming status: while the program sequence is exec uting, bit 7 of the status register i s a “0.” The status register c an be polled by toggling either CE# or OE#. While programming, the only valid commands are Read Status Register, Program Suspend, and Program Resume.

When programming is complete, the Program

Status bits shoul d be checked. If the programming

operation was unsuccessf ul, bit SR.4 of the status

is set then V

was not within acceptable l i m i ts, and

the WSM did not execute t he program command. If

SR.1 is set, a program operati on was attempted to

a locked block and the operation was aborted.

The status register should be cleared before

attempting the next operat ion. Any CUI instruction

can follow after programming is completed;

however, to prevent inadvertent status register

reads, be sure to reset the CUI to read array mode.

3.2.4.1 Suspending and Resuming Program

The Program Suspend command allows program suspension in order to read data in other locations of memory. Once the programming proces s starts, writing the Program Suspend command to the CUI requests that the WSM suspend the program sequence (at predetermined points in t he program algorithm). The device continues to output status register data after the Program Sus pend command is written. Polling s tat us regi st er bits SR. 7 and SR. 2 will determine when the program operation has been suspended (both will be set to “1”). t

WHRH1/tEHRH1

specify the program suspend latency.

A Read Array command can now be writt en to the CUI to read data from blocks other than that which is suspended. The only other valid commands, while program is suspended, are Read Status Register and Program Resume. Af ter the Program Resume command is written to t he flash memory, the WSM will continue with the program process and status register bits SR.2 and SR.7 will automatically be cleared. After the Program Resume command is written, the device automatically outputs status register data when read (see Figure 8, Program Suspend/Resume Flowchart). V used for program while in program suspend mode. RP# must also remain at V

must remain at the same VPP level

IH.

3.2.4.2 VPP Supply Voltage during Program

supply voltage considerations are outlined in

Section 3.4

PRELIMINARY

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

3.2.5 ERASE MODE

To erase a block, write the Erase Set-up and Eras e Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is iss ued. Block erasure results in all bits within the block being s et to “1.” Only one

block can be erased at a time. The WSM will execute the following sequence of

internally timed events to:

1. Program all bits within the block to “0.”

2. Verify that all bits within the block are sufficiently programmed to “0.”

3. Erase all bits within the block to “1.”

4. Verify that all bits within the block are sufficiently erased.

While the erase sequence is executing, bit 7 of the status register is a “0.”

When the status register indicates that erasure is complete, check t he Erase Status bit to verify that the erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status register will be set to a “1,” indicating an erase failure. If V the Erase Confirm command was issued, t he WSM will not execute the erase sequence; instead, SR.5 of the status register is set to indicate an erase error, and SR.3 is set to a “1” t o identify that V supply voltage was not within acceptable limits.

was not within acceptable l imits after

3.2.5.1 Suspending and Resuming Erase

Since an erase operation requires on the order of seconds to complete, an Erase Suspend c ommand is provided to allow erase-s equence interruption in order to read data from or program data to another block in memory. Once the erase sequence is started, writing the Erase Suspend com mand to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase algorithm. The status register will indicate if/when the erase operation has been suspended.

A Read Array/Program command can now be written to the CUI in order to read/write data f rom/to blocks other than that which is suspended. The Program command can subsequently be suspended to read yet another array location. The only valid commands whil e erase is sus pended are Erase Resume, Program, Program Resume, Read Array, or Read Status Register.

During erase suspend mode, the chip can be placed in a pseudo-standby mode by taking CE # to V

. This reduces active current consumption.

Erase Resume continues t he eras e s equenc e when CE# = V operation, the status register must be read and cleared before the next instruction is issued.

3.2.5.2 V

Section 3.4.

. As with the end of a standard erase

Supply Voltage during Erase

supply voltage considerations are outlined in

After an erase operation, cl ear the Status Regis ter (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed; however, to prevent inadvertent status register reads, it is adv isable to reset the flash to read array after the erase is complete.

PRELIMINARY

Page 20

SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

DATA

Table 6. Command Bus Definitions

First Bus Cycle Second Bus Cycle

Command Notes Oper Addr Data Oper Addr Data

Read Array 5 Write X FFH Intelligent Identifier 2,3.5 Write X 90H Read IA ID Read Status Register 5 Write X 70H Read X SRD Clear Status Register 5 Write X 50H Write (Program) 4,5 Write X 40H Write PA PD Alternate Write (Program) 4,5 Write X 10H Write PA PD Block Erase/Confirm 5 Write X 20H Write BA D0H Program/Erase Suspend 5 Write X B0H Program/Erase Resume 5 Write X D0H

ADDRESS

BA = Block Address SRD = Status Register Data IA = Identifier Address ID = Identifier Data PA = Program Address PD = Program Data

X = Don’t Care

NOTES:

1. Bus operations are defined in Table 3.

2. A

= 0 for manufacturer code, A0 = 1 for device code.

3. Following the Intelligent Identifier command, two read operations access manufacturer and device codes.

4. Either 40H or 10H command is valid.

5. When writing commands to the device, the upper data bus [DQ

draw.

–DQ15] should be either VIL or VIH, to minimize current

PRELIMINARY

Page 21

E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

indication of V

level. The WSM interrogates V

has not been switched on. The V

the WSM. The V

Status bit is not guaranteed to

Table 7. Status Register Bit Definition

WSMS ESS ES PS VPPS PSS BLS R

76543210

NOTES:

SR.7 WRITE STATE MACHINE STATUS

SR.6 = ERASE-SUSPEND STATUS (ESS)

SR.5 = ERASE STATUS (ES)

SR.4 = PROGRAM STATUS (PS)

SR.3 = VPP STATUS (VPPS)

SR.2 = PROGRAM SUSPEND STATUS (PSS)

SR.1 = Block Lock Status

SR.0 = RESERVED FOR FUTURE

1 = Ready (WSMS) 0 = Busy

1 = Erase Suspended 0 = Erase In Progress/Completed

1 = Error In Block Erasure 0 = Successful Block Erase

1 = Error in Word Program 0 = Successful Word Program

1 = V

Low Detect, Operation Abort

0 = V

1 = Program Suspended 0 = Program in Progress/Completed

1 = Program/Erase attempted on locked block; Operation aborted 0 = No operation to locked blocks

ENHANCEMENTS (R)

Check Write State Machine bit first to determine Word Program or Block Erase completion, before checking Program or Erase Status bits.

When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to

“1.” ESS bit remains set to “1” until an Erase

Resume command is issued. When this bit is set to “1,” WSM has applied the

max. number of erase pulses to the block and is still unable to verify successful block erasure.

When this bit is set to “1,” WSM has attempted but failed to program a word.

The V

Status bit does not provide continuous

PPL

and

level only after the Program or Erase command sequences have been entered, and informs the system if V is also checked before the operation is verified by

report accurate feedback between V V

PPH

When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to “1.” PSS bit remains set to “1” until a Program Resume command is issued.

If a program or erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode.

These bits are reserved for future use and should be masked out when polling the Status Register.

PRELIMINARY

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

Start

Write 40H

Program Address/Data

Read Status Register

SR.7 = 1?

Yes

Full Status

Check if Desired

Program Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

SR.3 =

SR.4 =

VPP Range Error

Programming Error

SR.1 =

Attempted Program to

Locked Block - Aborted

Program Successful

Bus Operation

Write

Read

Standby

Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of

program operations. Write FFH after the last program operation to reset device to read array mode.

Bus Operation

Standby

SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.

SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are programmed before full status is checked.

If an error is detected, clear the status register before attempting retry or other error recovery.

Command

Program Setup

Program

Command Comments

Comments

Data = 40H

Data = Data to Program Addr = Location to Program

Status Register Data Toggle CE# or OE# to Update Status Register Data

Check SR.7 1 = WSM Ready 0 = WSM Busy

Check SR.3

Low Detect

1 = V

Check SR.4

Program Error

1 = V

Check SR.1 1 = Attempted Program to Locked Block - Program Aborted

0580_07

Figure 7. Automated Word Programming Flowchart

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

Start

Write B0H

Read Status Register

SR.7 =

SR.2 =

Write FFH

Read Array Data

Done

Reading

Yes

Program Completed

Bus Operation

Write

Read

Standby

Write

Read

Write Program Resume

Write FFHWrite D0H

Command

Program Suspend

Read Array

Comments

Data = B0H Addr = X

Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X

Check SR.7 1 = WSM Ready 0 = WSM Busy

Check SR.2 1 = Program Suspended 0 = Program Completed

Data = FFH Addr = X

Read array data from block other than the one being programmed.

Data = D0H Addr = X

Program Resumed Read Array Data

Figure 8. Program Suspend/Resume Flowchart

PRELIMINARY

0580_08

Page 24

SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

Start

Write 20H

Write D0H and

Block Address

Read Status Register

SR.7 =

Suspend Erase

Full Status

Check if Desired

Block Erase Complete

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

SR.3 =

SR.4,5 =

VPP Range Error

Command Sequence

Block Erase ErrorSR.5 =

SR.1 =

Attempted Erase of

Locked Block - Aborted

Block Erase

Successful

Error

Suspend

Erase Loop

Yes

Bus Operation

Write

Read

Standby

Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of

block erasures. Write FFH after the last write operation to reset device to read array mode.

Bus Operation

Standby

SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine.

SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are erased before full status is checked.

If an error is detected, clear the status register before attempting retry or other error recovery.

Command

Erase Setup

Erase Confirm

Command Comments

Comments

Data = 20H Addr = Within Block to Be Erased

Data = D0H Addr = Within Block to Be Erased

Status Register Data Toggle CE# or OE# to Update Status Register Data

Check SR.7 1 = WSM Ready 0 = WSM Busy

Check SR.3

Low Detect

1 = V

Check SR.4,5 Both 1 = Command Sequence Error

Check SR.5 1 = Block Erase Error

Check SR.1 1 = Attempted Erase of Locked Block - Erase Aborted

0580_09

Figure 9. Automated Block Erase Flowchart

PRELIMINARY

Page 25

E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

Start

Write B0H

Read Status Register

SR.7 =

SR.6 =

Write FFH/40H

Read Array Data/

Program Array

Done

Reading and/or

Programming

Yes

Erase Completed

Write FFHWrite D0H

Bus Operation

Write

Read

Standby

Write

Read

Program

Write Erase Resume

Erase Suspend

Read Array

Command

Comments

Data = B0H Addr = X

Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X

Check SR.7 1 = WSM Ready 0 = WSM Busy

Check SR.6 1 = Erase Suspended 0 = Erase Completed

Data = FFH Addr = X

Read array data from block other than the one being erased.

Program data to block other than the one being erased.

Data = D0H Addr = X

Erase Resumed Read Array Data

Figure 10. Erase Suspend/Resume Flowchart

PRELIMINARY

0580_10

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

3.3 Block Locking

The Smart 3 Advanced Boot Block flash memory architecture features two hardware-lockable parameter blocks so that the kernel code for the system can be kept secure while other parameter blocks are programmed or erased as necessary.

3.3.1 V

The V

= VIL FOR COMPLETE

PROTECTION

programming voltage can be held low for complete write protection of all blocks in the flash device. When V erase operation will result in a error, prompt ing the

is below V

, any program or

PPLK

corresponding Status Register bit (SR.3) to be set.

3.3.2 WP# = V

FOR BLOCK LOCKING

The lockable blocks are locked when WP# = V any program or erase operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two parameter blocks (blocks #37 and #38 for the 16-Mbit, blocks #21 and #22 for the 8-Mbit, and blocks #13 and #14 for the 4-Mbit) are lockable. For the bottom configuration, t he bottom two parameter blocks (blocks #0 and #1 for 4-/8-/16-Mbit) are lockable. Unlocked blocks can be programmed or erased normally (unless V

3.3.3 WP# = V

WP# = V

unlocks all lockable blocks.

is below V

FOR BLOCK UNLOCKING

PPLK

These blocks can now be programmed or erased. Note that RP# does not override WP# locking as in

previous Boot Block devices. WP# cont rol s all block locking and V

provides protection against

spurious writes. Table 8 defi nes the writ e protec tion methods.

3.4 VPP Program and Erase

Voltages

Intel’s Smart 3 products provide in-system programming and erase at 2.7V–3.6V V customers requiring fast programming in their manufacturing environment, Smart 3 includes an additional low-cost, backward-compatible 12V programming feature.

. For

The 12V V

mode enhances programming

performance during the short period of time typically found in manufacturing processes; however, it is not intended for extended use. 12V may be applied to V

during program and erase operations for a

maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. V connected to 12V for a total of 80 hours maximum. Stressing the devic e beyond these limits may cause permanent damage.

Table 8. Write Protection Truth Table for

Advanced Boot Block Flash Memory Family

WP# RP# Write Protection

XXVILAll Blocks Locked

≥ V

;

PPLKVIL

≥ V

PPLKVIH

XVIHAll Blocks Locked

All Blocks Unlocked

Lockable Blocks

3.5 Power Consumption

While in operation, the flash device consumes active power. However, Int el Flash devices have a three-tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the device is idle. If the CE# is deasserted, the flash enters its standby mode, where current consumption is even lower. If RP# = V enters a deep power-down mode, where current is at a minimum. The combination of these features can minimize overall memory power consumption, and therefore, overall system power consumption.

3.5.1 ACTIVE POWER

With CE# at a logic-low level and RP# at a logichigh level, the device is in the ac ti ve m ode. Refer t o the DC Characteristic s t ables for I Active power is the largest contributor to overall system power consumption. Minimizing the active current could have a profound effect on system power consumption, especi ally for battery-operated devices.

may be

Provided

Locked

the flash

current values.

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

3.5.2 AUTOMATIC POWER SAVINGS (APS)

Automatic Power Savings provides low-power operation during active mode. Power Reduction Control (PRC) circuitry allows the flash to put itself into a low current state when not being accessed. After data is read from the memory array, PRC

logic controls the device’s power consumption by entering the APS mode where typical I comparable to I state with outputs valid until a new location is read.

APS reduces active current to standby current levels for 2.7V–3.6V CMOS input levels.

3.5.3 STANDBY POWER

With CE# at a logic-high level (V read mode, the flash memory i s in standby mode, which disables much of the device’s circuitry and substantially reduces power consumption. Outputs (DQ

–DQ15) are placed in a high-impedance st ate

independent of the status of the OE# signal. If CE# transitions to a logic-high level during erase or program operations, the device will continue to perform the operation and consume corresponding active power until the operation is completed.

System engineers should anal yz e the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This will provide a more accurate measure of applic ation-specif ic power and energy requirements.

3.5.4 DEEP POWER-DOWN MODE

The deep power-down mode of the Smart 3 Advanced Boot Block products switc hes the dev ice into a low power savings m ode, which is especially important for battery-based devices. This mode is activated when RP# = V

During read modes, RP# going low de-selects the memory and places the output drivers in a high impedance state. Recovery from the deep powerdown state, requires a minim um ti me equal to t (see AC Characteristics table).

During program or erase modes, RP# transi tioning low will abort the operation, but the memory contents of the address being programm ed or the block being erased are no longer valid as the data integrity has been compromised by the abort.

. The flash stays in this static

CCS

(GND ± 0.2V).

current is

) and the CUI in

PHQV

During deep power-down, all internal circuits are switched to a low power savings mode (RP# transitioning to V clears the status register).

or turning off power to the devic e

3.6 Power-Up/Down Operation

The device is protected against accidental block erasure or programming during power transitions. Power supply sequencing is not required, since the device is indifferent as to which power supply , V or VCC, powers-up first.

3.6.1 RP# CONNECTED TO SYSTEM

The use of RP# during system reset is important with automated program/erase devices since the system expects to read from the flash memory when it comes out of res et. If a CPU reset occ urs without a flash memory reset, proper CPU initialization will not occur because the flash memory may be providing status information instead of array data. Int el recommends c onnecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization following system reset.

System designers must guard against spurious writes when V is active. Since both WE# and CE# mus t be low for a command write, driving either signal to V inhibit writes to the device. The CUI architecture provides additional protection since alteration of memory contents can only occur after successful completion of the two-step command sequences. The device is also disabl ed until RP# is brought to V

holding the device in reset (RP# connected to system PowerGood) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection.

3.6.2 V

The CUI latches commands as issued by system software and is not altered by V transitions or WSM actions. Its default state upon power-up, after exit from deep power-down mode or after V is read array mode.

RESET

voltages are above V

, regardless of the stat e of its c ontrol inputs. By

, VPP AND RP# TRANSITIONS

transitions above V

LKO

(Lockout voltage),

and V

will

or CE#

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

After any program or block erase operation is complete (even after V V

), the CUI must be reset t o read array mode

PPLK

transitions down to

via the Read Array command if access to the fl ash memory array is desired.

Refer to

Using V

AP-617 Additional Flash Data Protection

, RP#, and WP#

for a circuit-level description of how to implement the protection schemes discussed in Section 3.5.

3.7 Power Supply Decoupling

Flash memory’s power switching characteristics require careful device decoupling. System designers should consider three supply current issues:

1. Standby current levels (I

2. Active current levels (I

3. Transient peaks produced by falling and rising

edges of CE#.

CCR

CCS

)

Transient current magnitudes depend on t he dev ice outputs’ capacitiv e and inductive loading. Two-line control and proper decoupling capacitor selection will suppress these transient voltage peaks. Each flash device should have a 0.1 µF ceramic capacitor connected between eac h V and between its V

and GND. These high-

and GND,

frequency, inherently low-inductance capacitors should be placed as close as possible to the package leads.

3.7.1 V

TRACE ON PRINTED CIRCUIT

BOARDS

Designing for in-system writes to the flash memory requires special consideration of the V supply trace by the printed circuit board designer. The V

pin supplies the flash m emory c ells c urrent

for programming and erasing. V

trace widths and

layout should be similar to that of V V

supply traces, and decoupling capacitors

. Adequate

power

placed adjacent to the component, will decrease spikes and overshoots.

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4.0 ABSOLUTE MAXIMUM

RATINGS*

Extended Operating Temperature

During Read............................ –40°C to +85°C

During Block Erase

and Program............................ –40°C to +85°C

Temperature Under Bias ......... –40°C to +85°C

Storage Temperature................... –65°C to +125°C

Voltage on Any Pin

(except V

with Respect to GND............... –0.5V to +5.0V

VPP Voltage (for Block

Erase and Program)

with Respect to GND.........–0.5V to +13.5V

VCC and V

with Respect to GND............... –0.2V to +5.0V

Output Short Circuit Current...................... 100 mA

5.0 OPERATING CONDITIONS (V

, VCCQ and VPP)

Supply Voltage

CCQ

1,2,4

CCQ

NOTICE: This datasheet contains preliminary information on new products in production. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design.

* WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may effect device reliability.

NOTES:

1. Minimum DC voltage is –0.5V on input/output pins. During transitions, this level may undershoot to –2.0V for periods < 20 ns. Maximum DC voltage on input/output pins is V transitions, may overshoot to V

1 3

20 ns.

2. Maximum DC voltage on V for periods < 20 ns.

3. Output shorted for no more than one second. No more than one output shorted at a time.

4. V

Program voltage is normally 2.7V–3.6V.

Connection to supply of 11.4V–12.6V can only be done for 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. V be connected to 12V for a total of 80 hours maximum. See Section 3.4 for details.

+ 0.5V which, during

+ 2.0V for periods <

may overshoot to +14.0V

= 2.7V–3.6V)

may

Table 9. Temperature and Voltage Operating Conditions4

Symbol Parameter Notes Min Max Units

V V V V

CCQ PP1

PP2

Operating Temperature –40 +85 °C

2.7V–3.6V VCC Supply Voltage 1,4 2.7 3.6 Volts

2.7V–3.6V I/O Supply Voltage 1,2,4 2.7 3.6 Volts Program and Erase Voltage 4 2.7 3.6 Volts

3 11.4 12.6 Volts

Cycling Block Erase Cycling 5 10,000 Cycles

NOTES:

1. See DC Characteristics tables for voltage range-specific specifications.

2. The voltage swing on the inputs, V

3. Applying V

and 2500 cycles on the parameter blocks. V for details.

4. V

5. For operating temperatures of –25°C– +85°C the device is projected to have a minimum block erase cycling of 10,000 to 30,000 cycles.

= 11.4V–12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main blocks

, V

and V

CCQ

must share the same supply when all three are between 2.7V and 3.6V.

PP1

is required to match V

may be connected to 12V for a total of 80 hours maximum. See Section 3.4

CCQ

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

5.1 DC Characteristics: V

= 2.7V–3.6V

CCQ

Table 10. DC Characteristics

Sym Parameter Notes VCC = 2.7V–3.6V Unit Test Conditions

Typ Max

= VCCMax = V

Input Load Current 1 ± 1.0 µA

Output Leakage Current 1 ± 10 µA

CCS

CCDVCC

Standby Current 1,7 20 50 µA CMOS INPUTS

Deep Power-Down

1,7 1 10 µA

Current

CCRVCC

CCWVCC

Read Current 1,5,7 10 20 mA

Program Current 1,4,7 8 20 mA V

820mAV

VCC Erase Current 1,4,7 8 20 mA V

CCE

820mAV

CCESVCC

Erase Suspend

1,2,4,7 20 50 µA CE# = V

Current

CCWSVCC

Program Suspend

1,2,4,7 20 50 µA CE# = V

Current

VPP Deep Power-Down

PPD

1 0.2 5 µA RP# = GND ± 0.2V

= V

CE# = RP# = V

or GND

CCQ

= VCCMax = V

= V

or GND

CCQ

= VCCMax = V

CCQ

CMOS INPUTS

= VCCMax = V

= V

or GND

RP# = GND ± 0.2V

CMOS INPUTS

= VCCMax = V

OE# = V f = 5 MHz, I

OUT

Inputs = V

Program in Progress

Erase in Progress

Erase Suspend in Progress

Program Suspend in Progress

= 0 mA

= V

PPH1

= V

PPH2

= V

PPH1

= V

PPH2

, CE# =V

or V

(3V)

(12V)

(3V)

(12V)

Current

VPP Read Current 1 2 ±50 µA V

PPR

≤ V

CCQ

Max

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

Table 10. DC Characteristics (Continued)

Sym Parameter Notes VCC = 2.7V–3.6V Unit Test Conditions

Typ Max

PPWVPP

PPE

PPESVPP

PPWSVPP

Program Current 1,4 15 40 mA VPP = V

Program in Progress

10 25 mA VPP = V

Program in Progress

VPP Erase Current 1,4 13 25 mA VPP = V

Erase in Progress

Erase Suspend

Current

Program Suspend

Current

825mAV

1,4 50 200 µA VPP = V

= V

Erase in Progress

Erase Suspend in Progress

Program Suspend in Progress

PPH1

PPH2

PPH1

PPH2

PPH1

(3V)

(12V)

(3V)

(12V)

or V

PPH2

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

Table 10. DC Characteristics (Continued)

Sym Parameter Notes VCC = 2.7V–3.6V Unit Test Conditions

Min Max

Input Low Voltage –0.4 0.4 V

CCQ –

Input High Voltage

Output Low Voltage 0.10 V VCC = VCCMin= VCCQMin

Output High Voltage VCCQ –

PPLKVPP

PPH1

PPH2

LKO

LKO2

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at nominal V

2. I

CCES

3. Erase and Program are inhibited when V

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I

6. Applying V and 2500 cycles on the parameter blocks. V for details.

7. Includes the sum of V

Lock-Out Voltage 3 1.5 V Complete Write Protection

during Prog/Erase

Operations

Program/Erase Lock

Voltage V

Program/Erase

CCQ

Lock Voltage

and I and I

are specified with device de-selected. If device is read while in erase suspend, current draw is sum of

CCWS

. If the device is read while in program suspend, current draw is the sum of I

CCR

= 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks

and V

CCQ

current.

0.4V

0.1V

3 2.7 3.6 V

3,6 11.4 12.6 V

1.5 V

1.2 V

< V

and not guaranteed outside the valid VPP ranges of V

PPLK

to approximately standby levels in static operation (CMOS inputs).

CCR

may be connected to 12V for a total of 80 hours maximum. See Section 3.4

= 100 µA

VVCC = VCCMin = VCCQMin

= –100 µA

, TA = +25°C.

and I

CCWA

CCR

PPH1

and V

PPH2

Table 11. Capacitance (TA = 25°C, f = 1 MHz)

Sym Parameter Notes Typ Max Units Conditions

Input Capacitance 1 6 8 pF VIN = 0V

Output Capacitance 1 10 12 pF V

OUT

NOTE:

1. Sampled, not 100% tested.

= 0V

OUT

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

Case Speed Conditions

CCQ

0.0

NOTE:

AC test inputs are driven at V

Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are when V

for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at V

CCQ

TEST POINTSINPUT

Figure 11. 2.7V–3.6V Input Range and Measurement Points

Test Configuration Component Values for Worst

CCQ

Test Configuration CL (pF) R1 (Ω)R2 (Ω)

2.7V Standard Test 50 25K 25K

Device

under

Test

Out

NOTE:

includes jig capacitance.

CCQ

= 2.7V.

CCQ

OUTPUT

0580_11

/2.

CCQ

NOTE:

See table for component values.

Figure 12. Test Configuration

PRELIMINARY

0580_12

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

6.0 OPERATING CONDITIONS (V

= 1.8V–2.2V)

CCQ

Table 12. Temperature and VCC Operating Conditions

Symbol Parameter Notes Min Max Units

V V V V V V

CC1

CC2

CCQ PP1

PP2

PP3

Operating Temperature –40 +85 °C

2.7V–2.85V VCC Supply Voltage 1 2.7 2.85 Volts

2.7V–3.3V VCC Supply Voltage 1 2.7 3.3 Volts

1.8V–2.2V I/O Supply Voltage 1,4 1.8 2.2 Volts Program and Erase Voltage 1 2.7 2.85 Volts

1 2.7 3.3 Volts

1,2 11.4 12.6 Volts

Cycling Block Erase Cycling 3 10,000 Cycles

NOTES:

1. See DC Characteristics tables for voltage range-specific specifications.

2. Applying V

and 2500 cycles on the parameter. V details.

3. For operating temperatures of –25°C– +85°C the device is projected to have a minimum block erase cycling of 10,000 to 30,000 cycles.

4. The voltage swing on the inputs, V

6.1 DC Characteristics: V

= 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks

may be connected to 12V for a total of 80 hours maximum. See Section 3.4 for

is required to match V

= 1.8V–2.2V

CCQ

These tables are valid for the following power supply combinations only:

1. V

2. V

CC1 CC2

and V and V

CCQ CCQ

and (V and (V

PP1 PP2

Wherever the input voltage V

or V

)

PP3

or V

)

PP3

is mentioned, it is required that VIN matches the chosen V

PRELIMINARY

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

Table 13. DC Characteristics: V

Sym Parameter Notes

2.7V–2.85V V

2.7V–3.3V

Typ Max

Input Load Current 1 ± 1.0 µA

Output Leakage Current 1 ± 10 µA

CCS

Standby Current 1,7 20 50 µA CMOS INPUTS

150 250 µA CMOS INPUTS

CCDVCC

Deep Power-Down

1,7 1 10 µA

Current

CCRVCC

Read Current 1,5,7 8 18 mA

12 23 mA

CC1

CC2

= 1.8V–2.2V

CCQ

Unit Test Conditions

= VCCMax

= V

CCQ

= V

CCQ

= V

CCQ

= V

CCQ

= V

CC1

= V

CCQ

CE# = RP# = V

= V

CC2

= V

CCQ

CE# = RP# = V

CMOS INPUTS

= VCCMax (V

= V

CCQ

= V

RP# = GND ± 0.2V

CMOS INPUTS

= V

CC1

= V

CCQ

OE# = V f = 5 MHz, I

Inputs = V

CMOS INPUTS

= V

CC2

= V

CCQ

OE# = V f = 5 MHz, I

Inputs = GND ± 0.2V or V

Max

or GND Max

Max

or GND

Max (2.7V–2.85V)

Max

CCQ

Max (2.7V–3.3V)

Max

CCQ

or V

CC1

Max

or GND

Max (2.7V–2.85V)

Max

CCQ

, CE# = V

OUT

or V

= 0 mA

Max (2.7V–3.3V)

Max

CCQ

, CE# = V

OUT

= 0 mA

CC2

CCQ

)

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

Table 13. DC Characteristics: V

Sym Parameter Notes

CCWVCC

CCE

CCESVCC

CCWSVCC

PPD

PPR

Program Current 1,4,7 8 20 mA V

VCC Erase Current 1,4,7 8 20 mA V

Erase Suspend

1,2,4,7 20 50 µA CE# = V

Current

Program Suspend

1,2,4,7 20 50 µA CE# = V

Current VPP Deep Power-Down

1 0.2 5 µA RP# = GND ± 0.2V

Current VPP Read and Standby

1 2 ±50 µA V

Current

PPWVPP

PPE

PPESVPP

Program Current 1,4 15 40 mA VPP = V

VPP Erase Current 1,4 13 25 mA

Erase Suspend

1 50 200 µA VPP = V

Current

PPWSVPP

Program Suspend

Current

1 50 200 µA VPP = V

= 1.8V–2.2V (Continued)

CCQ

CC1

2.7V–2.85V V

CC2

Unit Test Conditions

2.7V–3.3V

Typ Max

= V

Program in Progress

820mAV

= V

Program in Progress

= V

Erase in Progress

= V

Erase in Progress

Erase Suspend in Progress

Program Suspend in Progress

≤ V

Program in Progress

10 25 mA VPP = V

Program in Progress V

= V

Erase in Progress

825mAV

= V

Erase in Progress

Erase Suspend in Progress

Program Suspend in Progress

PPH1

PPH3

PPH1

PPH3

PPH1

PPH3

PPH1

PPH3

PPH1

or V

(12V)

or V

(12V)

or V

(12V)

or V

(12V)

, V

PPH2

, or V

PPH3

PRELIMINARY

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

Table 13. DC Characteristics: V

Sym Parameter Notes

2.7V–2.85V

= 1.8V–2.2V (Continued)

CCQ

CC1

Unit Test Conditions

CC2

2.7V–3.3V

Min Max

V V

V V V

NOTES:

1. All currents are in RMS unless otherwise noted. Typical values at nominal V

2. I

3. Erases and Writes inhibited when V

4. Sampled, not 100% tested.

5. Automatic Power Savings (APS) reduces I

6. Applying V

7 Includes the sum of V

Input Low Voltage –0.2 0.2 V

–

Input High Voltage

Output Low Voltage –0.10 0.10 V VCC = VCCMin

Output High Voltage V

PPLKVPP

PPH1

PPH2

PPH3

LKO1

LKO2

CCES

device is read while in program suspend , current draw is I

and 2500 cycles on the parameter blocks. V for details.

Lock-Out Voltage 3 1.5 V Complete Write Protection

during Program/

Erase Operations

3,6 11.4 12.6 V

Program/Erase Lock

Voltage V

Program/Erase

CCQ

Lock Voltage

and I

are specified with device de-selected. If device is read while in erase suspend, current draw is I

CCWS

< V

PPLK

= 11.4V–12.6V during program/erase can only be done for a maximum of 1000 cycles on the main blocks

and V

CCQ

current

CCQ

0.2V

–

CCQ

0.1V

3 2.7 2.85 V

3 2.7 3.3 V

1.5 V

1.2 V

, and not guaranteed outside the valid V

to approximately standby levels in static operation (CMOS inputs).

CCR

may be connected to 12V for a total of 80 hours maximum. See Section 3.4

CCR

VVCC = VCCMin

, TA = +25°C.

= V

CCQ

= 100 µA

= V

CCQ

= –100 µA

ranges of V

CCQ

Min

PPH1,VPPH2

Table 14. Capacitance (TA = 25°C, f = 1 MHz)

Sym Parameter Notes Typ Max Units Conditions

Input Capacitance 1 6 8 pF VIN = 0V

Output Capacitance 1 10 12 pF V

OUT

NOTE:

1. Sampled, not 100% tested.

OUT

= 0V

CCR

. or V

. If the

PPH3.

PRELIMINARY

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

Case Speed Conditions

CCQ

0.0

CCQ

TEST POINTSINPUT

NOTE:

AC test inputs are driven at V

for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at V

CCQ

Input rise and fall times (10%–90%) <10 ns. For worst case speed conditions V

Figure 13. 1.8V—2.2V Input Range and Measurement Points

Test Configuration Component Values for Worst

CCQ

Test Configuration CL (pF) R1 (Ω)R2 (Ω)

1.8V Standard Test 50 16.7K 16.7K

Device

under

Test

Out

NOTE:

includes jig capacitance.

CCQ

= 1.8V.

CCQ

OUTPUT

0580_11

/2.

CCQ

NOTE:

See table for component values.

Figure 14. Test Configuration

0580_12

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

7.0 AC CHARACTERISTICS

AC Characteristics are applicable to both V

Table 15. AC Characteristics: Read Operations (Extended Temperature)

# Symbol Parameter V

R1 t

AVAV

R2 t

AVQV

R3 t

ELQV

R4 t

GLQV

R5 t

PHQV

R6 t

ELQX

R7 t

GLQX

R8 t

EHQZ

R9 t

GHQZ

R10 t

NOTES:

1. See AC Input/Output Reference Waveform for timing measurements.

2. OE# may be delayed up to t

3. Sampled, but not 100% tested.

4. See Test Configuration (Figures 12 and 14), 2.7V–3.6V and 1.8V–2.2V Standard Test component values.

Read Cycle Time 120 150 ns Address to Output Delay 120 150 ns CE# to Output Delay 2 120 150 ns OE# to Output Delay 2 65 65 ns RP# to Output Delay 600 600 ns CE# to Output in Low Z 3 0 0 ns OE# to Output in Low Z 3 0 0 ns CE# to Output in High Z 3 40 40 ns OE# to Output in High Z 3 40 40 ns Output Hold from Address, CE#,

or OE# Change, Whichever Occurs First

ELQV–tGLQV

after the falling edge of CE# without impact on t

CCQ

ranges.

Load CL = 50 pF

ELQV

Prod 120 ns 150 ns

Notes Min Max Min Max

30 0 ns

2.7V–3.6V

Units

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

ADDRESSES (A)

CE# (E)

OE# (G)

WE# (W)

DATA (D/Q)

RP#(P)

Device and

Address Select ion

Address Stable

High Z

Valid Output

Figure 15. AC Waveform: Read Operations

Data

Valid Standby

R10

High Z

0580_15

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

Table 16. AC Characteristics: Write Operations (Extended Temperature)

Load 50 pF

# Symbol Parameter V

2.7V–3.6V

2.7V-3.6V

Units

Prod 120 ns 150 ns

Notes Min Max Min Max

W1 t

PHWL

PHEL

W2 t

ELWL

WLEL

W3 t

WLWH

ELEH

W4 t

DVWH

DVEH

W5 t

AVWH

AVEH

W6 t

WHEH

EHWH

W7 t

WHDX

EHDX

W8 t

WHAX

EHAX

W9 t

WHWL

EHEL

W10 t

VPWH

VPEH

W11 t

QVVL

LOCK

NOTES:

1. Read timing characteristics during program suspend and erase suspend are the same as during read-only operations. Refer to AC Characteristics during read mode.

2. Refer to command definition table for valid A

3. Refer to command definition table for valid D

4. Sampled, but not 100% tested.

5. See Test Configuration (Figures 12 and 14),

6. Time t

LOCK

RP# High Recovery to

600 600 ns

WE# (CE#) Going Low CE# (WE#) Setup to

00ns

WE# (CE#) Going Low WE# (CE#) Pulse Width 90 90 ns

Data Setup to WE#

370 70 ns

(CE#) Going High Address Setup to WE#

290 90 ns

(CE#) Going High CE# (WE#) Hold Time

00ns

from WE# (CE#) High Data Hold Time from

30 0 ns

WE# (CE#) High Address Hold Time from

20 0 ns

WE# (CE#) High WE# (CE#) Pulse Width

30 30 ns

High V

Setup to WE# (CE#)

4 200 200 ns

Going High V

Hold from Valid SRD 4 0 0 ns

Block Unlock / Lock

4, 6 200 200 ns

Delay

(Table 6).

2.7V–3.6V and 1.8V–2.2V Standard Test component values.

is required for successful locking and unlocking of all lockable blocks.

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

AB C D E F

WP#

High Z

PPH

PPLK

(Note 1)

W3 W4 W7

W10

Valid SRD

W11

0580_16

ADDRESSES [A]

CE#(WE#) [E(W)]

OE# [G]

WE#(CE#) [W(E)]

DATA [D/Q]

RP# [P]

V [V]

NOTES:

1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register Data.

A. V

Power-Up and Standby.

B. Write Program or Erase Setup Command. C. Write Valid Address and Data (for Program) or Erase Confirm Command. D. Automated Program or Erase Delay. E. Read Status Register Data (SRD): reflects completed program/erase operation. F. Write Read Array Command.

Figure 16. AC Waveform: Program and Erase Operations

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

7.1 Reset Operations

RP# (P)

(A) Reset during Read Mode

RP# (P)

(B) Reset during Program or Block Erase, <

RP# (P)

PLPH

Abort

Complete

PLRH

PLPH

PLRH

PLPH

Abort

Complete

Deep

Power-

Down

PHQV

PHWL

PHEL

PHQV

PHWL

PHEL

PLPHtPLR

PHQV

PHWL

PHEL

PLPHtPLRH

Figure 17. AC Waveform: Deep Power-Down/Reset Operation

Reset Specifications

VCC = 2.7–3.6V

Symbol Parameter Notes Min Max Unit

PLPH

RP# Low to Reset during Read (If RP# is tied to V

, this specification is not

1,3 100 ns

applicable)

PLRH

NOTES:

1. If t

2. If RP# is asserted while a block erase or

3. Sampled, but not 100% tested.

RP# Low to Reset during Block Erase or Program 2,3 22 µs

is < 100 ns the device may still RESET but this is not guaranteed.

PLPH

word program operation is not executing, the reset will complete within 100 ns.

0580_17

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

Table 17. Erase and Program Timings

VPP = 2.7V VPP = 12V

Sym Parameter Notes Typ

BWPB

Block Program Time

2 0.10 0.30 0.03 0.10 sec

(Parameter)

BWMB

WHQV1

EHQV1

WHQV2

EHQV2

WHQV3

EHQV3

WHRH1

EHRH1

WHRH2

EHRH2

NOTES:

1. Typical values measured at T

2. Excludes external system-level overhead.

3. Sampled, but not 100% tested.

Block Program Time (Main) 2 0.80 2.40 0.24 0.80 sec Program Time 2 22 200 8 185 µs

Block Erase Time (Parameter) 2 1 5.0 0.8 4.8 sec

Block Erase Time (Main) 2 1.8 8.0 1.1 7.0 sec

Program Suspend Latency 3 5 10 5 10 µs

Erase Suspend Latency 3 5 20 6 12 µs

= +25°C and nominal voltages.

Max

Typ

Max

Unit

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

APPENDIX A

ORDERING INFORMATION

T E 2 8 F 1 6 0 B 3 T 1 2 0

Package

TE = 48-Lead TSOP

GT = 48-Ball µBGA* CSP

Product line designator

for all Intel Flash products

Device Density

160 = x16 (16 Mbit) 800 = x16 (8 Mbit) 400 = x 16 (4 Mbit)

VALID COMBINATIONS

Extended 16M TE28F160B3T120 GT28F160B3T120

Extended 8M TE28F800B3T120 GT28F800B3T120

Extended 4M TE28F400B3T120 GT28F400B3T120

Access Speed (ns)

(120, 150)

T =

Top Blocking

B =

Bottom Blocking

Product Family

B3 = Smart 3 Advanced Boot Block

= 2.7V - 3.6V

= 2.7V - 3.6V or 11.4V - 12.6V

48-Lead TSOP 48-Ball µBGA* CSP

TE28F160B3B120 GT28F160B3B120

TE28F160B3T150 GT28F160B3T150 TE28F160B3B150 GT28F160B3B150

TE28F800B3B120 GT28F800B3B120

TE28F800B3T150 GT28F800B3T150 TE28F800B3B150 GT28F800B3B150

TE28F400B3B120 GT28F400B3B120

TE28F400B3T150 GT28F400B3T150 TE28F400B3B150 GT28F400B3B150

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

APPENDIX B

WRITE STATE MACHINE CURRENT/NEXT STATES

Command Input (and Next State)

Current

State

Read Array “1” Array Read

Program

Setup

Program

(Not Comp.)

Program

(Complete)

Program

Suspend to

Status

SR.7 Data

“1” Status Pgm.

“0” Status Program Pgm Susp.

“1” Status Read

“1” Status Prog.

When Read

Read Array (FFH)

Array

Susp. to

Array

Program

Setup

(40/10H)

Program

Setup

Program

Setup

Program Suspend

to Array

Erase Setup

(20H)

Erase Setup

Erase

Confirm

Program (Command input = Data to be programmed)

Program Program

Program /

(D0H)

Erase Susp. (B0H)

Read Array Read

to Status

Read Array Read

Susp. to

Array

Program /

Erase

Resume

(D0)

Program Prog.

Read

Status

(70H)

Status

Susp. to

Status

Clear

Status

(50H)

Read Array

Program

Read Array

Program Suspend to

Read ID

(90H)

Read

Identifier

Read

Identifier

Array

Program

Suspend to

Array

Erase Setup “1” Status Erase Command Error Erase Erase

Erase

Cmd. Error

Erase

(Not Comp)

Erase

(Complete)

Erase

Suspend to

Status

Erase. Susp.

to Array

Read Status “1” Status Read

Read

Identifier

“1” Array Prog.

Susp. to

“1” Status Read

“0” Status Erase Ers. Susp.

“1” Status Read

“1” Status Erase

Susp. to

“1” Array Erase

Susp. to

“1” ID Read

Array

Program Suspend

to Array

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Program

Setup

Erase Setup

Erase

Susp. to

Array

Erase

Susp. to

Array

Erase Setup

Program Program

Susp. to

Array

Cmd. Err.

Read Array Read

to Status

Read Array Read

Erase Erase

Susp. to

Array

Erase Erase

Susp. to

Array

Read Array Read

Program Prog.

Susp. to

Erase Erase Command Error

Erase Erase

Susp. to

Erase Erase

Susp. to

Status

Prog.

Susp. to

Array

Read Array

Erase

Read Array

Erase Suspend

to Array

Erase Suspend

to Array

Read Array

Prog.

Susp. to

Array

Read

Identifier

Read

Identifier

Read

Identifier

Read

Identifier

1. You cannot program “1”s to the flash. Writing FFH following the Program Setup will initiate the internal program algorithm of the WSM. Although the algorithm will execute, array data is not changed. The WSM returns to read status mode without reporting any error. Assuming V array mode.

> V

writing a second FFH while in read status mode will return the flash to read

PPLK

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

APPENDIX C

ACCESS TIME VS. CAPACITIVE LOAD

AVQV

Access Time vs. Load Capacita nce

124 123 122 121 120 119 118

Access Time(ns)

117 116 115

30 50 70 100

Load Capacitance(pF)

vs. CL)

Derating Cu rve

Smart 3 A dva nc ed Boot Block

NOTE:

= 2.7V

CCQ

This chart shows a derating curve for device acc ess time with respec t to capacitive l oad. The value in the DC characteristics section of the specification corresponds to C

NOTE:

Sampled, but not 100% tested

= 50 pF.

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SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE E

APPENDIX D

ARCHITECTURE BLOCK DIAGRAM

DQ0-DQ

CCQ

A0-A

Input Buffer

Address

Latch

Address Counter

Power

Reduction

Control

Y-Decoder

X-Decoder

Output Buffer

Output

Multiplexer

Y-Gating/Sensing

4-KWord

Parameter Block

Identifier

Status

Comparator

4-KWord

32-KWord

Parameter Block

Data

Main Block

32-KWord

Main Block

Input Buffer

Command

User

Interface

Write State

Machine

I/O Logic

Program/Erase Voltage Switch

CE# WE# OE#

RP# WP#

GND

0580-20

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E SMART 3 ADVANCED BOOT BLOCK–WORD-WIDE

APPENDIX E

ADDITIONAL INFORMATION

Order Number Document/Tool

210830 290605

292172

NOTE:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office.

2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools.

1997 Flash Memory Databook Smart 3 Advanced Boot Block Byte-Wide 8-Mbit (1024K x8), 16-Mbit

(2056K x 8) Flash Memory Family Datasheet AP-617 Additional Flash Data Protection Using VPP, RP# and WP#

(1,2)

PRELIMINARY

Datasheet GT28F160B3-B120 Datasheet (Intel Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

REVISION HISTORY

1.0 INTRODUCTION

1.1 Smart 3 Advanced Boot Block Flash Memory Enhancements

Table 1. Smart 3 Advanced Boot Block Feature Summary

1.2 Product Overview

2.0 PRODUCT DESCRIPTION

2.1 Package Pinouts

Figure 1. 48-Lead TSOP Package

Figure 2. 4-Mbit 48-Ball µBGA* Chip Size Package

Figure 3. 8-Mbit 48-Ball µBGA* Chip Size Package

Figure 4. 16-Mbit 48-Ball µBGA* Chip Size Package

Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions

2.2 Block Organization

2.2.1 PARAMETER BLOCKS

2.2.2 MAIN BLOCKS

Figure 5. 4-/8-/16-Mbit Advanced Boot Block Word-Wide Top Boot Memory Maps

Figure 6. 4-/8-/16-Mbit Advanced Boot Block Word-Wide Top Boot Memory Maps

3.0 PRINCIPLES OF OPERATION

Table 3. Bus Operations for Word-Wide Mode

3.1 Bus Operation

3.1.1 READ

3.1.2 OUTPUT DISABLE

3.1.3 STANDBY

3.1.5 WRITE

3.1.4 DEEP POWER-DOWN / RESET

3.2 Modes of Operation

3.2.1 READ ARRAY

Table 4. Command Codes and Descriptions

3.2.2 READ INTELLIGENT IDENTIFIER

Table 5. Intelligent Identifier Table

3.2.3 READ STATUS REGISTER

3.2.3.1 Clearing the Status Register

3.2.4 PROGRAM MODE

3.2.4.1 Suspending and Resuming Program

3.2.4.2 VPP Supply Voltage during Program

3.2.5 ERASE MODE

3.2.5.1 Suspending and Resuming Erase

Table 6. Command Bus Definitions

Table 7. Status Register Bit Definition

Figure 7. Automated Word Programming Flowchart

Figure 8. Program Suspend/Resume Flowchart

Figure 9. Automated Block Erase Flowchart

Figure 10. Erase Suspend/Resume Flowchart

3.3 Block Locking

3.5 Power Consumption

3.5.1 ACTIVE POWER

3.5.3 STANDBY POWER

3.5.4 DEEP POWER-DOWN MODE

3.6 Power-Up/Down Operation

3.7 Power Supply Decoupling

Table 10. DC Characteristics

Table 11. Capacitance (TA = 25°C, f = 1 MHz)

Figure 11. 2.7V–3.6V Input Range and Measurement Points

Figure 12. Test Configuration

Table 12. Temperature and VCC Operating Conditions

Table 14. Capacitance (TA = 25°C, f = 1 MHz)

Figure 13. 1.8V—2.2V Input Range and Measurement Points

Figure 14. Test Configuration

7.0 AC CHARACTERISTICS

Table 15. AC Characteristics: Read Operations (Extended Temperature)

Figure 15. AC Waveform: Read Operations

Table 16. AC Characteristics: Write Operations (Extended Temperature)

Figure 16. AC Waveform: Program and Erase Operations

7.1 Reset Operations

Figure 17. AC Waveform: Deep Power-Down/Reset Operation

Table 17. Erase and Program Timings